Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.18 95.53 94.11 95.38 94.93 97.57 99.59


Total tests in report: 2931
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
40.83 40.83 49.57 49.57 49.41 49.41 22.44 22.44 64.15 64.15 59.28 59.28 0.13 0.13 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2804499219
47.99 7.16 53.75 4.19 58.16 8.75 22.67 0.23 70.43 6.29 81.96 22.68 0.96 0.83 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.3801139284
53.24 5.25 64.82 11.07 65.66 7.49 25.74 3.07 80.32 9.88 81.96 0.00 0.96 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.3456255541
57.65 4.41 74.16 9.33 68.12 2.47 32.67 6.93 80.65 0.33 81.96 0.00 8.34 7.38 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_random.2452591743
60.95 3.30 74.16 0.00 68.12 0.00 52.19 19.52 80.65 0.00 82.13 0.17 8.45 0.11 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3183575122
64.00 3.05 74.16 0.00 68.12 0.00 52.19 0.00 80.65 0.00 82.13 0.00 26.75 18.31 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.1045663226
67.05 3.05 79.07 4.91 71.82 3.69 55.74 3.55 82.32 1.67 86.60 4.47 26.75 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2705954519
69.76 2.71 79.07 0.00 71.85 0.03 55.74 0.00 82.32 0.00 86.60 0.00 43.00 16.25 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_error.1582871506
72.15 2.39 80.61 1.54 74.59 2.74 61.07 5.33 84.18 1.86 86.94 0.34 45.52 2.51 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.3568729788
74.03 1.88 80.61 0.00 74.61 0.02 61.07 0.00 84.18 0.00 86.94 0.00 56.75 11.23 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.1249608365
75.66 1.64 80.61 0.00 74.61 0.00 61.07 0.00 84.18 0.00 86.94 0.00 66.57 9.82 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.2768234582
77.14 1.48 82.18 1.57 75.37 0.77 64.19 3.12 84.85 0.67 89.69 2.75 66.57 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.966656007
78.59 1.44 82.18 0.00 75.37 0.00 64.19 0.00 84.85 0.00 89.69 0.00 75.23 8.66 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.2613224659
80.00 1.41 84.69 2.51 77.37 2.00 65.29 1.10 87.69 2.84 89.69 0.00 75.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.783541754
81.40 1.41 84.84 0.14 77.48 0.11 73.13 7.84 87.87 0.18 89.86 0.17 75.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.409617219
82.51 1.11 86.78 1.94 78.65 1.17 75.43 2.29 88.79 0.92 90.21 0.34 75.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.1274657404
83.44 0.93 87.76 0.99 79.95 1.30 75.74 0.31 89.70 0.91 92.27 2.06 75.24 0.01 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.888918103
84.32 0.88 87.76 0.00 79.95 0.00 81.02 5.28 89.70 0.00 92.27 0.00 75.24 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.3797971557
85.18 0.86 88.84 1.08 80.69 0.74 82.91 1.89 90.77 1.07 92.61 0.34 75.26 0.01 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.345063367
86.03 0.85 88.89 0.04 81.45 0.76 83.62 0.71 90.82 0.06 92.61 0.00 78.78 3.52 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.887811093
86.81 0.78 88.89 0.00 82.29 0.84 83.62 0.00 90.87 0.05 92.61 0.00 82.58 3.80 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.3846087227
87.52 0.71 89.17 0.29 82.38 0.09 83.63 0.01 90.97 0.10 96.39 3.78 82.58 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2049180090
88.17 0.65 89.17 0.00 82.39 0.01 83.63 0.00 90.97 0.00 96.39 0.00 86.44 3.87 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_stress_all.3134261838
88.78 0.61 89.17 0.00 82.45 0.06 83.63 0.00 90.97 0.00 96.39 0.00 90.06 3.62 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.2340823318
89.34 0.56 89.81 0.64 84.34 1.89 84.11 0.47 91.33 0.37 96.39 0.00 90.06 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.379378088
89.81 0.47 89.81 0.00 84.35 0.01 84.11 0.00 91.33 0.00 96.39 0.00 92.89 2.83 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_error.1204015755
90.28 0.47 90.72 0.91 85.24 0.89 84.41 0.30 92.05 0.71 96.39 0.00 92.89 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1715428404
90.71 0.43 91.76 1.04 85.78 0.54 84.92 0.51 92.53 0.48 96.39 0.00 92.89 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.3476841053
91.11 0.40 91.77 0.01 85.79 0.01 87.13 2.21 92.53 0.00 96.56 0.17 92.89 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.2993421647
91.49 0.37 91.88 0.12 87.48 1.70 87.13 0.00 92.56 0.03 96.56 0.00 93.29 0.40 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_tl_errors.2306453688
91.83 0.34 92.69 0.81 87.82 0.34 87.81 0.67 92.75 0.19 96.56 0.00 93.33 0.04 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.416694914
92.12 0.30 92.69 0.00 87.82 0.00 89.58 1.78 92.75 0.00 96.56 0.00 93.33 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.1577548564
92.40 0.28 93.12 0.43 88.31 0.49 89.84 0.25 93.24 0.49 96.56 0.00 93.33 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.3892148446
92.64 0.24 93.12 0.00 88.32 0.01 89.84 0.00 93.24 0.00 96.56 0.00 94.78 1.46 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.2614548661
92.86 0.22 93.12 0.00 88.32 0.01 89.84 0.00 93.24 0.00 96.56 0.00 96.09 1.30 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_random_large_delays.4142587622
93.08 0.22 93.47 0.35 88.36 0.04 90.73 0.89 93.27 0.03 96.56 0.00 96.09 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.3628032784
93.28 0.21 93.83 0.36 88.68 0.32 90.95 0.22 93.60 0.32 96.56 0.00 96.09 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_output.678828618
93.48 0.20 93.83 0.00 89.85 1.17 90.95 0.00 93.60 0.00 96.56 0.00 96.10 0.01 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_tl_errors.3087653719
93.65 0.17 93.83 0.00 89.85 0.00 90.95 0.00 93.60 0.00 96.56 0.00 97.12 1.02 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2672018602
93.79 0.14 93.98 0.15 89.96 0.11 91.44 0.50 93.68 0.08 96.56 0.00 97.12 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2956470742
93.93 0.14 94.08 0.10 90.66 0.70 91.46 0.02 93.68 0.00 96.56 0.00 97.12 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.1432698559
94.06 0.13 94.08 0.00 91.02 0.37 91.47 0.01 94.10 0.42 96.56 0.00 97.12 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3156953921
94.18 0.12 94.15 0.07 91.10 0.07 92.03 0.55 94.14 0.04 96.56 0.00 97.12 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.4281504144
94.29 0.11 94.15 0.00 91.10 0.00 92.67 0.64 94.14 0.00 96.56 0.00 97.12 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.651980874
94.38 0.09 94.15 0.00 91.10 0.01 92.67 0.00 94.14 0.00 96.56 0.00 97.67 0.55 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_error.1928136020
94.47 0.09 94.15 0.00 91.10 0.00 93.20 0.53 94.14 0.00 96.56 0.00 97.67 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.929849168
94.55 0.08 94.21 0.06 91.16 0.06 93.35 0.15 94.17 0.02 96.74 0.17 97.67 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1937631534
94.62 0.07 94.21 0.00 91.59 0.43 93.35 0.00 94.17 0.00 96.74 0.00 97.67 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/9.chip_tl_errors.3925611326
94.69 0.07 94.22 0.01 91.77 0.18 93.35 0.00 94.38 0.21 96.74 0.00 97.67 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1043174068
94.74 0.06 94.34 0.12 91.82 0.05 93.51 0.16 94.39 0.01 96.74 0.00 97.67 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.3788989422
94.80 0.05 94.44 0.10 91.89 0.06 93.60 0.09 94.46 0.07 96.74 0.00 97.67 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.1219457540
94.85 0.05 94.44 0.00 91.89 0.00 93.90 0.31 94.46 0.00 96.74 0.00 97.67 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prod.669297114
94.90 0.05 94.51 0.08 91.95 0.06 94.00 0.10 94.53 0.07 96.74 0.00 97.67 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.801543852
94.95 0.05 94.54 0.03 91.97 0.02 94.06 0.06 94.56 0.02 96.91 0.17 97.67 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.3956585919
95.00 0.05 94.54 0.00 92.10 0.13 94.06 0.00 94.60 0.05 96.91 0.00 97.78 0.11 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.630799109
95.04 0.04 94.54 0.00 92.14 0.04 94.06 0.00 94.60 0.00 96.91 0.00 97.98 0.20 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.1345121350
95.08 0.04 94.61 0.07 92.14 0.00 94.20 0.15 94.61 0.01 96.91 0.00 97.98 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.1203387156
95.11 0.04 94.62 0.01 92.16 0.02 94.20 0.00 94.62 0.01 97.08 0.17 97.99 0.01 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/10.chip_sw_all_escalation_resets.3391362748
95.15 0.04 94.62 0.01 92.17 0.01 94.21 0.01 94.63 0.01 97.25 0.17 98.00 0.01 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1276284038
95.18 0.04 94.63 0.01 92.18 0.01 94.22 0.01 94.64 0.01 97.42 0.17 98.01 0.01 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/26.chip_sw_all_escalation_resets.2977316124
95.22 0.03 94.63 0.00 92.39 0.21 94.22 0.00 94.64 0.00 97.42 0.00 98.01 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_tl_errors.384196617
95.25 0.03 94.63 0.00 92.47 0.08 94.27 0.05 94.71 0.07 97.42 0.00 98.01 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.1863343544
95.29 0.03 94.63 0.00 92.68 0.20 94.27 0.00 94.71 0.00 97.42 0.00 98.01 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_0.3986022575
95.32 0.03 94.63 0.00 92.68 0.01 94.28 0.01 94.71 0.00 97.59 0.17 98.01 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.118203695
95.35 0.03 94.63 0.00 92.68 0.00 94.28 0.00 94.71 0.00 97.59 0.00 98.20 0.19 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.4213670191
95.38 0.03 94.63 0.00 92.68 0.00 94.45 0.18 94.71 0.00 97.59 0.00 98.20 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3966776728
95.40 0.03 94.70 0.07 92.71 0.03 94.46 0.01 94.76 0.05 97.59 0.00 98.20 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.637825479
95.43 0.02 94.70 0.00 92.72 0.01 94.51 0.05 94.76 0.00 97.59 0.00 98.27 0.07 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.2883889557
95.45 0.02 94.72 0.02 92.84 0.11 94.51 0.00 94.76 0.00 97.59 0.00 98.27 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_rw.491808424
95.47 0.02 94.72 0.00 92.89 0.06 94.51 0.00 94.77 0.02 97.59 0.00 98.33 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_stress_all.3115730381
95.49 0.02 94.78 0.06 92.94 0.05 94.51 0.00 94.80 0.02 97.59 0.00 98.33 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sleep_pin_wake.3386673507
95.51 0.02 94.81 0.03 92.96 0.01 94.56 0.05 94.82 0.02 97.59 0.00 98.33 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3175876439
95.53 0.02 94.82 0.01 92.98 0.02 94.64 0.08 94.82 0.00 97.59 0.00 98.33 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.541786646
95.55 0.02 94.82 0.00 93.08 0.10 94.64 0.00 94.82 0.00 97.59 0.00 98.33 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.821078507
95.56 0.02 94.82 0.00 93.16 0.08 94.64 0.00 94.83 0.02 97.59 0.00 98.33 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/21.xbar_stress_all.606326422
95.58 0.02 94.82 0.00 93.16 0.00 94.74 0.10 94.83 0.00 97.59 0.00 98.33 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_flash_rma_unlocked.1944168171
95.59 0.02 94.82 0.00 93.16 0.00 94.74 0.00 94.83 0.00 97.59 0.00 98.43 0.09 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3851216549
95.61 0.02 94.82 0.00 93.25 0.09 94.74 0.00 94.83 0.00 97.59 0.00 98.43 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.1775662653
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96.09 0.01 94.95 0.00 94.10 0.01 95.36 0.00 94.93 0.00 97.59 0.00 99.59 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.3858523362
96.09 0.01 94.95 0.00 94.10 0.01 95.36 0.00 94.93 0.00 97.59 0.00 99.59 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2981241326
96.09 0.01 94.95 0.00 94.11 0.01 95.36 0.00 94.93 0.00 97.59 0.00 99.59 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_10.811803906
96.09 0.01 94.95 0.00 94.11 0.00 95.36 0.01 94.93 0.00 97.59 0.00 99.59 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_tap_straps_testunlock0.161020939
96.09 0.01 94.95 0.00 94.11 0.00 95.37 0.01 94.93 0.00 97.59 0.00 99.59 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.4196158391
96.09 0.01 94.95 0.00 94.11 0.00 95.37 0.01 94.93 0.00 97.59 0.00 99.59 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.3786823887
96.09 0.01 94.95 0.00 94.11 0.00 95.37 0.01 94.93 0.00 97.59 0.00 99.59 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.4147140705
96.09 0.01 94.95 0.00 94.11 0.00 95.37 0.01 94.93 0.00 97.59 0.00 99.59 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.4193480499
96.09 0.01 94.95 0.00 94.11 0.00 95.38 0.01 94.93 0.00 97.59 0.00 99.59 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.4174128314
96.09 0.01 94.95 0.00 94.11 0.00 95.38 0.01 94.93 0.00 97.59 0.00 99.59 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.3594780872
96.09 0.01 94.95 0.00 94.11 0.00 95.38 0.01 94.93 0.00 97.59 0.00 99.59 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/29.chip_sw_all_escalation_resets.3580902224
96.09 0.01 94.95 0.00 94.11 0.00 95.38 0.01 94.93 0.00 97.59 0.00 99.59 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3127146354

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.3422483655
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.229809923
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.1753199764
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.2293549491
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.36693175
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_same_csr_outstanding.2583462940
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.2403216786
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.43306931
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2526226992
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.3515439928
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_large_delays.302333736
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.1199841103
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.3988118552
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.2667472691
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.166412602
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.4091164458
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2236271718
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1387464026
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.2332665604
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1907673175
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_aliasing.2826545400
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.1370472340
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3107137442
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.2462596342
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.113698629
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2460728535
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.1222272265
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.472410092
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2164720546
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.1819001895
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.3385505343
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.107726232
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.2148134732
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.974797400
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.2657313555
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.4204427462
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.88989000
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.3640935772
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1090642167
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.4155889984
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.1976700062
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.1471247011
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.2702462961
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.3809321559
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.1233483003
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3218392653
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.1687149148
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.61035834
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.2194472164
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.29809922
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.262406218
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.3026677079
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.336729242
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.4004501254
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.601966302
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.798036381
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.3487232797
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.2638127842
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1259715177
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_unmapped_addr.2600790989
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.4136087462
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_csr_rw.1991544286
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.chip_same_csr_outstanding.923154785
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device.2843992436
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2186386387
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.4290388987
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_error_random.3127123594
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random.3360266234
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_large_delays.497542041
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_slow_rsp.2713912906
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_random_zero_delays.1886721368
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_same_source.3409575790
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke.3667678867
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_large_delays.3476637548
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2358489906
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3298926155
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all.2713982755
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_error.72002778
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.485014937
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/11.xbar_unmapped_addr.3710324597
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.2821476627
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_csr_rw.3771306908
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_same_csr_outstanding.4000727392
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.chip_tl_errors.3249406847
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device.101978626
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2456113845
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1411672913
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_error_random.3379714252
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random.2079745068
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_large_delays.1035632458
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_slow_rsp.192987933
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_random_zero_delays.588318207
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_same_source.1412685343
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke.567479783
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_large_delays.3024536433
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2429404969
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1084953150
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all.560058383
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_error.1263588825
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3246558513
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_unmapped_addr.1966759494
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.3133230751
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_csr_rw.3889352769
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_same_csr_outstanding.2519038809
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.chip_tl_errors.1715447953
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device.3861412633
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3454523753
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3878057062
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_error_random.1908832603
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random.1786622810
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/13.xbar_random_large_delays.3677671653
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Total test records in report: 2931
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TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_rom.379508285 Sep 18 11:56:44 PM UTC 24 Sep 18 11:58:17 PM UTC 24 2464809416 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2804499219 Sep 18 11:59:35 PM UTC 24 Sep 19 12:03:57 AM UTC 24 3717016783 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_setuprx.4281504144 Sep 18 11:57:30 PM UTC 24 Sep 19 12:04:19 AM UTC 24 3956080190 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_entropy.4104699241 Sep 19 12:02:04 AM UTC 24 Sep 19 12:05:33 AM UTC 24 2188439926 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_flash.1985707565 Sep 19 12:02:05 AM UTC 24 Sep 19 12:05:40 AM UTC 24 3158854818 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_manufacturer.2765731423 Sep 19 12:02:52 AM UTC 24 Sep 19 12:05:46 AM UTC 24 3302747582 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.966656007 Sep 19 12:02:20 AM UTC 24 Sep 19 12:06:12 AM UTC 24 2850461179 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.50372898 Sep 19 12:00:55 AM UTC 24 Sep 19 12:06:36 AM UTC 24 3061376244 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pattgen_ios.1164157666 Sep 19 12:02:11 AM UTC 24 Sep 19 12:06:49 AM UTC 24 2923587238 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_vbus.720908375 Sep 19 12:02:35 AM UTC 24 Sep 19 12:06:58 AM UTC 24 2467830760 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.3788989422 Sep 19 12:01:54 AM UTC 24 Sep 19 12:07:01 AM UTC 24 3296967514 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.4269229683 Sep 19 12:02:27 AM UTC 24 Sep 19 12:07:02 AM UTC 24 3169128884 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sival_flash_info_access.321020042 Sep 19 12:02:11 AM UTC 24 Sep 19 12:07:14 AM UTC 24 2793197302 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3911457397 Sep 19 12:02:25 AM UTC 24 Sep 19 12:07:22 AM UTC 24 2685514394 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.614335431 Sep 18 11:59:34 PM UTC 24 Sep 19 12:07:30 AM UTC 24 4102289372 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3183575122 Sep 19 12:01:34 AM UTC 24 Sep 19 12:07:32 AM UTC 24 3775962056 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3175876439 Sep 19 12:02:10 AM UTC 24 Sep 19 12:07:51 AM UTC 24 2761288036 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.1863343544 Sep 19 12:01:41 AM UTC 24 Sep 19 12:08:14 AM UTC 24 3585863144 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.2332114648 Sep 18 11:59:34 PM UTC 24 Sep 19 12:08:21 AM UTC 24 4712230754 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.4178240947 Sep 19 12:06:39 AM UTC 24 Sep 19 12:08:29 AM UTC 24 2113015701 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1662851250 Sep 18 11:59:04 PM UTC 24 Sep 19 12:08:52 AM UTC 24 4922673000 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.1862175508 Sep 19 12:02:07 AM UTC 24 Sep 19 12:09:05 AM UTC 24 5958299144 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.2423303251 Sep 19 12:02:47 AM UTC 24 Sep 19 12:09:11 AM UTC 24 3594371084 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1908942941 Sep 18 11:58:29 PM UTC 24 Sep 19 12:09:19 AM UTC 24 5554775000 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.4246524295 Sep 19 12:07:17 AM UTC 24 Sep 19 12:09:23 AM UTC 24 3511015751 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.3476841053 Sep 19 12:01:13 AM UTC 24 Sep 19 12:09:39 AM UTC 24 4202814696 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.635476742 Sep 19 12:00:38 AM UTC 24 Sep 19 12:10:23 AM UTC 24 4171295844 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.2282847378 Sep 19 12:02:06 AM UTC 24 Sep 19 12:10:31 AM UTC 24 4903288370 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3455453963 Sep 19 12:01:41 AM UTC 24 Sep 19 12:10:34 AM UTC 24 4209880133 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.3964790781 Sep 19 12:02:05 AM UTC 24 Sep 19 12:10:47 AM UTC 24 4129534040 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_aon_pullup.480506318 Sep 19 12:02:46 AM UTC 24 Sep 19 12:11:06 AM UTC 24 4319448068 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.651980874 Sep 19 12:07:00 AM UTC 24 Sep 19 12:11:11 AM UTC 24 3160442990 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3575018595 Sep 19 12:09:07 AM UTC 24 Sep 19 12:11:12 AM UTC 24 2907575796 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3822888826 Sep 19 12:06:57 AM UTC 24 Sep 19 12:11:27 AM UTC 24 3147035868 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2550971248 Sep 19 12:10:04 AM UTC 24 Sep 19 12:11:41 AM UTC 24 2287937146 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.4122011025 Sep 19 12:02:36 AM UTC 24 Sep 19 12:11:43 AM UTC 24 3846769138 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_rand_baudrate.3592660719 Sep 19 12:02:27 AM UTC 24 Sep 19 12:11:51 AM UTC 24 4067748500 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.345063367 Sep 19 12:02:46 AM UTC 24 Sep 19 12:12:09 AM UTC 24 5248119880 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops.3321968503 Sep 19 12:02:05 AM UTC 24 Sep 19 12:12:28 AM UTC 24 4159941610 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.385152399 Sep 19 12:02:52 AM UTC 24 Sep 19 12:12:34 AM UTC 24 4715751080 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.541786646 Sep 18 11:57:39 PM UTC 24 Sep 19 12:12:42 AM UTC 24 8012885890 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through.2254739404 Sep 19 12:01:20 AM UTC 24 Sep 19 12:12:43 AM UTC 24 6350492930 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4265030950 Sep 19 12:10:46 AM UTC 24 Sep 19 12:12:44 AM UTC 24 2211542168 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx3.3889100424 Sep 19 12:02:26 AM UTC 24 Sep 19 12:13:02 AM UTC 24 3914713348 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_rst.3589127670 Sep 19 12:10:42 AM UTC 24 Sep 19 12:14:18 AM UTC 24 2756918200 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3343026243 Sep 19 12:02:38 AM UTC 24 Sep 19 12:14:28 AM UTC 24 4580447652 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_data_integrity_escalation.118203695 Sep 19 12:02:31 AM UTC 24 Sep 19 12:15:23 AM UTC 24 6637909572 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3421246215 Sep 19 12:13:07 AM UTC 24 Sep 19 12:15:47 AM UTC 24 3354704451 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_req.742012860 Sep 19 12:10:18 AM UTC 24 Sep 19 12:15:51 AM UTC 24 3232168250 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3166971225 Sep 19 12:00:24 AM UTC 24 Sep 19 12:16:41 AM UTC 24 5435669510 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1047706780 Sep 19 12:11:37 AM UTC 24 Sep 19 12:17:19 AM UTC 24 4256911496 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.929849168 Sep 19 12:06:55 AM UTC 24 Sep 19 12:17:37 AM UTC 24 6482358880 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3782050239 Sep 19 12:14:02 AM UTC 24 Sep 19 12:18:08 AM UTC 24 3433124392 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access.269333427 Sep 19 12:01:57 AM UTC 24 Sep 19 12:18:27 AM UTC 24 5277127268 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2456384507 Sep 19 12:02:12 AM UTC 24 Sep 19 12:19:24 AM UTC 24 5759110984 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pwm_pulses.3260679775 Sep 19 12:01:53 AM UTC 24 Sep 19 12:19:34 AM UTC 24 7899033320 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_irq.1605540844 Sep 19 12:14:01 AM UTC 24 Sep 19 12:19:46 AM UTC 24 2383853400 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3326065704 Sep 19 12:10:51 AM UTC 24 Sep 19 12:20:12 AM UTC 24 8135049131 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2956470742 Sep 19 12:13:40 AM UTC 24 Sep 19 12:20:23 AM UTC 24 5948428760 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.1798838163 Sep 19 12:14:29 AM UTC 24 Sep 19 12:21:02 AM UTC 24 3410243353 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_inputs.4093073302 Sep 19 12:13:58 AM UTC 24 Sep 19 12:21:10 AM UTC 24 2893014007 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1203319761 Sep 19 12:14:16 AM UTC 24 Sep 19 12:21:32 AM UTC 24 4917620904 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc.1787105266 Sep 19 12:17:22 AM UTC 24 Sep 19 12:21:41 AM UTC 24 2192168760 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2417241240 Sep 19 12:14:35 AM UTC 24 Sep 19 12:21:46 AM UTC 24 5031527020 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_irq.1505633222 Sep 19 12:14:12 AM UTC 24 Sep 19 12:22:07 AM UTC 24 4088135604 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1534122863 Sep 19 12:12:46 AM UTC 24 Sep 19 12:22:44 AM UTC 24 6283347818 ps
T669 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en.610275733 Sep 19 12:17:25 AM UTC 24 Sep 19 12:22:52 AM UTC 24 3023226710 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.768776380 Sep 19 12:14:26 AM UTC 24 Sep 19 12:23:12 AM UTC 24 5106848560 ps
T670 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_idle.289139607 Sep 19 12:18:04 AM UTC 24 Sep 19 12:23:14 AM UTC 24 2685520280 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_cpu_info.3956585919 Sep 19 12:11:15 AM UTC 24 Sep 19 12:23:14 AM UTC 24 5661707738 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.409617219 Sep 19 12:09:28 AM UTC 24 Sep 19 12:23:34 AM UTC 24 8566177205 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_kat.474678588 Sep 19 12:22:53 AM UTC 24 Sep 19 12:31:38 AM UTC 24 3764219364 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.666480288 Sep 19 12:12:55 AM UTC 24 Sep 19 12:23:40 AM UTC 24 7290976916 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_masking_off.229362256 Sep 19 12:18:17 AM UTC 24 Sep 19 12:23:45 AM UTC 24 3390732266 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3769760827 Sep 19 12:14:12 AM UTC 24 Sep 19 12:23:54 AM UTC 24 7179704400 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.334734311 Sep 19 12:14:30 AM UTC 24 Sep 19 12:24:00 AM UTC 24 19983109606 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.2992898134 Sep 19 12:06:57 AM UTC 24 Sep 19 12:24:47 AM UTC 24 12020224606 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.420868362 Sep 19 12:04:43 AM UTC 24 Sep 19 12:25:00 AM UTC 24 8708375304 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.586064397 Sep 19 12:13:58 AM UTC 24 Sep 19 12:25:07 AM UTC 24 4229897223 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.3568729788 Sep 19 12:18:53 AM UTC 24 Sep 19 12:25:23 AM UTC 24 3387772640 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.3594780872 Sep 19 12:16:07 AM UTC 24 Sep 19 12:25:49 AM UTC 24 3427039186 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_timeout.1429806627 Sep 19 12:19:22 AM UTC 24 Sep 19 12:26:07 AM UTC 24 3331265312 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_entropy.1474775899 Sep 19 12:21:49 AM UTC 24 Sep 19 12:26:23 AM UTC 24 3089869981 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.731246041 Sep 19 12:14:08 AM UTC 24 Sep 19 12:26:28 AM UTC 24 9284436840 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2763377831 Sep 19 12:05:03 AM UTC 24 Sep 19 12:26:32 AM UTC 24 8427458724 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_entropy.635270714 Sep 19 12:21:53 AM UTC 24 Sep 19 12:26:35 AM UTC 24 3041635324 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_kat_test.1367767649 Sep 19 12:22:48 AM UTC 24 Sep 19 12:27:05 AM UTC 24 2474249380 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_escalation.887521398 Sep 19 12:19:19 AM UTC 24 Sep 19 12:27:12 AM UTC 24 5192988856 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1276284038 Sep 19 12:20:53 AM UTC 24 Sep 19 12:27:29 AM UTC 24 3265370000 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_config_host.1173167053 Sep 19 12:01:28 AM UTC 24 Sep 19 12:27:34 AM UTC 24 8530348456 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3620689289 Sep 19 12:03:16 AM UTC 24 Sep 19 12:27:36 AM UTC 24 8465864812 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1204448432 Sep 19 12:11:04 AM UTC 24 Sep 19 12:28:58 AM UTC 24 6135909666 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.461294849 Sep 19 12:01:58 AM UTC 24 Sep 19 12:29:10 AM UTC 24 8316149507 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2081034058 Sep 19 12:25:11 AM UTC 24 Sep 19 12:29:41 AM UTC 24 2614890920 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_kat_test.3539351165 Sep 19 12:25:13 AM UTC 24 Sep 19 12:29:47 AM UTC 24 3252140840 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en.3527167769 Sep 19 12:26:09 AM UTC 24 Sep 19 12:30:19 AM UTC 24 3108097860 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_randomness.400339558 Sep 19 12:14:35 AM UTC 24 Sep 19 12:30:20 AM UTC 24 6592114250 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1353849249 Sep 19 12:11:14 AM UTC 24 Sep 19 12:30:21 AM UTC 24 12011754350 ps
T671 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_idle.2549492738 Sep 19 12:26:06 AM UTC 24 Sep 19 12:30:44 AM UTC 24 3260890620 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1135944512 Sep 19 12:10:57 AM UTC 24 Sep 19 12:31:13 AM UTC 24 11980683887 ps
T902 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3318511678 Sep 19 12:14:14 AM UTC 24 Sep 19 12:31:13 AM UTC 24 10963879880 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc.2257632083 Sep 19 12:25:51 AM UTC 24 Sep 19 12:31:40 AM UTC 24 3513840952 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.3786823887 Sep 19 12:22:50 AM UTC 24 Sep 19 12:31:46 AM UTC 24 2704487016 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2981241326 Sep 19 12:16:42 AM UTC 24 Sep 19 12:32:01 AM UTC 24 5058399688 ps
T903 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_oneshot.382307849 Sep 19 12:26:11 AM UTC 24 Sep 19 12:32:17 AM UTC 24 2780330168 ps
T267 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_rnd.3270788716 Sep 19 12:16:41 AM UTC 24 Sep 19 12:32:30 AM UTC 24 6146206332 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_idle.2576169787 Sep 19 12:28:47 AM UTC 24 Sep 19 12:32:39 AM UTC 24 3435397748 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_app_rom.1286566647 Sep 19 12:28:46 AM UTC 24 Sep 19 12:33:11 AM UTC 24 2623246536 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_cshake.2983347634 Sep 19 12:28:23 AM UTC 24 Sep 19 12:33:27 AM UTC 24 2983789440 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2149815164 Sep 19 12:25:05 AM UTC 24 Sep 19 12:33:28 AM UTC 24 4298293520 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3966776728 Sep 19 12:23:41 AM UTC 24 Sep 19 12:33:28 AM UTC 24 5978773808 ps
T904 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1958370568 Sep 19 12:28:47 AM UTC 24 Sep 19 12:34:21 AM UTC 24 2445789783 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.3620083958 Sep 19 12:31:38 AM UTC 24 Sep 19 12:35:40 AM UTC 24 3221898553 ps
T905 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac.118187237 Sep 19 12:28:36 AM UTC 24 Sep 19 12:35:59 AM UTC 24 3396544504 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.317663037 Sep 19 12:02:24 AM UTC 24 Sep 19 12:36:04 AM UTC 24 23005657202 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.2993421647 Sep 19 12:22:50 AM UTC 24 Sep 19 12:36:09 AM UTC 24 3847229576 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.934948217 Sep 19 12:21:09 AM UTC 24 Sep 19 12:36:31 AM UTC 24 5344499176 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1937631534 Sep 19 12:29:55 AM UTC 24 Sep 19 12:36:57 AM UTC 24 3732275450 ps
T277 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_plic_sw_irq.2163830495 Sep 19 12:33:28 AM UTC 24 Sep 19 12:37:57 AM UTC 24 2285480080 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1715428404 Sep 19 12:31:39 AM UTC 24 Sep 19 12:39:41 AM UTC 24 5807564216 ps
T906 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_aes_trans.589838121 Sep 19 12:33:34 AM UTC 24 Sep 19 12:39:42 AM UTC 24 4405763558 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1066406858 Sep 19 12:31:36 AM UTC 24 Sep 19 12:39:53 AM UTC 24 6392728168 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3629253851 Sep 19 12:29:37 AM UTC 24 Sep 19 12:40:07 AM UTC 24 4784244296 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1807017284 Sep 19 12:29:13 AM UTC 24 Sep 19 12:40:17 AM UTC 24 9195599422 ps
T907 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2990697358 Sep 19 12:34:22 AM UTC 24 Sep 19 12:41:09 AM UTC 24 4399443844 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs.4147140705 Sep 19 12:26:03 AM UTC 24 Sep 19 12:41:16 AM UTC 24 5559693956 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.211635368 Sep 19 12:25:29 AM UTC 24 Sep 19 12:41:46 AM UTC 24 5648075149 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2244228642 Sep 19 12:34:30 AM UTC 24 Sep 19 12:41:55 AM UTC 24 5156319843 ps
T908 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1725571307 Sep 19 12:33:33 AM UTC 24 Sep 19 12:41:56 AM UTC 24 5034703448 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_10.3892148446 Sep 19 12:33:30 AM UTC 24 Sep 19 12:42:30 AM UTC 24 3723128120 ps
T659 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.1937078432 Sep 19 12:20:23 AM UTC 24 Sep 19 12:42:35 AM UTC 24 7511994680 ps
T909 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.4096313705 Sep 19 12:30:33 AM UTC 24 Sep 19 12:42:50 AM UTC 24 7162146636 ps
T910 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_sw_mode.1076540190 Sep 19 12:23:40 AM UTC 24 Sep 19 12:42:51 AM UTC 24 5197549790 ps
T673 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_reset_frequency.55642363 Sep 19 12:37:17 AM UTC 24 Sep 19 12:43:19 AM UTC 24 2748444912 ps
T911 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2715591099 Sep 19 12:34:29 AM UTC 24 Sep 19 12:43:54 AM UTC 24 5035573636 ps
T912 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter.1476280773 Sep 19 12:38:41 AM UTC 24 Sep 19 12:44:04 AM UTC 24 2842916155 ps
T913 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_frequency.179729811 Sep 19 12:37:39 AM UTC 24 Sep 19 12:44:05 AM UTC 24 2949859128 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1231276599 Sep 19 12:34:30 AM UTC 24 Sep 19 12:44:14 AM UTC 24 4664173656 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.416694914 Sep 19 12:20:41 AM UTC 24 Sep 19 12:44:30 AM UTC 24 14403615748 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.2409617038 Sep 19 12:30:32 AM UTC 24 Sep 19 12:44:33 AM UTC 24 7405224102 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1468054689 Sep 19 12:10:46 AM UTC 24 Sep 19 12:44:36 AM UTC 24 10694412674 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.3858523362 Sep 19 12:10:53 AM UTC 24 Sep 19 12:44:36 AM UTC 24 11951237160 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_alert.637825479 Sep 19 12:31:39 AM UTC 24 Sep 19 12:44:56 AM UTC 24 6223836824 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.1055530477 Sep 19 12:40:11 AM UTC 24 Sep 19 12:45:16 AM UTC 24 4711804825 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_20.783541754 Sep 19 12:33:23 AM UTC 24 Sep 19 12:45:23 AM UTC 24 4504829900 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1304304327 Sep 19 12:35:04 AM UTC 24 Sep 19 12:45:33 AM UTC 24 4876742960 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_dpi.611408698 Sep 19 12:01:40 AM UTC 24 Sep 19 12:45:37 AM UTC 24 12104090024 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.3797971557 Sep 19 12:28:02 AM UTC 24 Sep 19 12:46:19 AM UTC 24 7238808652 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2693362066 Sep 19 12:37:13 AM UTC 24 Sep 19 12:46:36 AM UTC 24 4018581692 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.879703143 Sep 19 12:21:09 AM UTC 24 Sep 19 12:46:48 AM UTC 24 7590218320 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_prod.3666621159 Sep 19 12:44:55 AM UTC 24 Sep 19 12:47:38 AM UTC 24 2495193522 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.303750730 Sep 19 12:42:04 AM UTC 24 Sep 19 12:47:56 AM UTC 24 3550269626 ps
T914 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1042321080 Sep 19 12:37:14 AM UTC 24 Sep 19 12:48:16 AM UTC 24 4764063752 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.801543852 Sep 19 12:42:04 AM UTC 24 Sep 19 12:48:46 AM UTC 24 7655638250 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3524998251 Sep 19 12:36:24 AM UTC 24 Sep 19 12:49:22 AM UTC 24 4099259560 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3339520094 Sep 19 12:37:14 AM UTC 24 Sep 19 12:49:25 AM UTC 24 4516183496 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.1938434759 Sep 19 12:41:01 AM UTC 24 Sep 19 12:49:25 AM UTC 24 3684618600 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2811015956 Sep 19 12:40:24 AM UTC 24 Sep 19 12:49:31 AM UTC 24 5070446888 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3812561282 Sep 19 12:45:54 AM UTC 24 Sep 19 12:49:34 AM UTC 24 2971205278 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.3738037456 Sep 19 12:43:42 AM UTC 24 Sep 19 12:49:38 AM UTC 24 4273604332 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3978911137 Sep 19 12:46:48 AM UTC 24 Sep 19 12:50:06 AM UTC 24 2571046577 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3663699182 Sep 19 12:43:40 AM UTC 24 Sep 19 12:50:10 AM UTC 24 4789020880 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2049180090 Sep 19 12:46:14 AM UTC 24 Sep 19 12:50:29 AM UTC 24 2741305348 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_reset.1219457540 Sep 19 12:14:11 AM UTC 24 Sep 19 12:50:38 AM UTC 24 23663383806 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.3839932543 Sep 19 12:42:53 AM UTC 24 Sep 19 12:50:47 AM UTC 24 6647878352 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2179968071 Sep 19 12:28:46 AM UTC 24 Sep 19 12:51:02 AM UTC 24 8010812196 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation.1275107596 Sep 19 12:26:34 AM UTC 24 Sep 19 12:51:35 AM UTC 24 9324126954 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.3960551993 Sep 19 12:43:47 AM UTC 24 Sep 19 12:51:43 AM UTC 24 5463677464 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1563541911 Sep 19 12:11:15 AM UTC 24 Sep 19 12:51:44 AM UTC 24 27969578393 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.3456255541 Sep 19 12:33:31 AM UTC 24 Sep 19 12:51:48 AM UTC 24 5856000320 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.719452358 Sep 19 12:44:31 AM UTC 24 Sep 19 12:51:51 AM UTC 24 5223549775 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2623852358 Sep 19 12:47:28 AM UTC 24 Sep 19 12:52:05 AM UTC 24 2888377559 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1451787079 Sep 19 12:47:32 AM UTC 24 Sep 19 12:52:14 AM UTC 24 3011111135 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usb_ast_clk_calib.1165990887 Sep 19 12:46:40 AM UTC 24 Sep 19 12:52:22 AM UTC 24 3701379459 ps
T915 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3307200224 Sep 19 12:48:39 AM UTC 24 Sep 19 12:52:39 AM UTC 24 3569566468 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.1203387156 Sep 19 12:44:48 AM UTC 24 Sep 19 12:52:55 AM UTC 24 6117418621 ps
T916 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_write_clear.4204483162 Sep 19 12:46:49 AM UTC 24 Sep 19 12:53:05 AM UTC 24 2905302450 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3800996808 Sep 19 12:43:46 AM UTC 24 Sep 19 12:53:21 AM UTC 24 5106069040 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.2800526111 Sep 19 12:44:48 AM UTC 24 Sep 19 12:53:31 AM UTC 24 5493156008 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.192854234 Sep 19 12:44:03 AM UTC 24 Sep 19 12:53:59 AM UTC 24 5095884772 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3574348953 Sep 19 12:26:50 AM UTC 24 Sep 19 12:54:13 AM UTC 24 9033543534 ps
T917 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_multistream.2407869666 Sep 19 12:26:12 AM UTC 24 Sep 19 12:54:24 AM UTC 24 7728421870 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.210976662 Sep 19 12:25:40 AM UTC 24 Sep 19 12:55:02 AM UTC 24 7469449540 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.60746349 Sep 19 12:10:45 AM UTC 24 Sep 19 12:55:10 AM UTC 24 27195006952 ps
T918 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_outputs.1777179802 Sep 19 12:40:58 AM UTC 24 Sep 19 12:55:26 AM UTC 24 7245523992 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2125169615 Sep 19 12:46:45 AM UTC 24 Sep 19 12:56:10 AM UTC 24 4645504701 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_crash_alert.2992832633 Sep 19 12:46:39 AM UTC 24 Sep 19 12:58:11 AM UTC 24 5164024152 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_peri.1887511530 Sep 19 12:33:28 AM UTC 24 Sep 19 12:58:29 AM UTC 24 11524390000 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_scrambling_smoketest.1102173462 Sep 19 12:55:11 AM UTC 24 Sep 19 12:58:37 AM UTC 24 2848682604 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3810752572 Sep 19 12:49:00 AM UTC 24 Sep 19 12:58:58 AM UTC 24 6054758837 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.4193480499 Sep 19 12:28:00 AM UTC 24 Sep 19 12:59:22 AM UTC 24 10038437460 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_idle_load.29562774 Sep 19 12:52:22 AM UTC 24 Sep 19 01:00:56 AM UTC 24 4235697250 ps
T919 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.316081678 Sep 19 12:46:48 AM UTC 24 Sep 19 01:02:28 AM UTC 24 7364249677 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_mem_access.3680200599 Sep 19 12:40:21 AM UTC 24 Sep 19 01:03:39 AM UTC 24 13457935710 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_sleep_load.1511379114 Sep 19 12:54:55 AM UTC 24 Sep 19 01:04:16 AM UTC 24 10536374092 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1699245490 Sep 19 12:42:50 AM UTC 24 Sep 19 01:04:45 AM UTC 24 20987852478 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3187487722 Sep 19 12:14:29 AM UTC 24 Sep 19 01:06:38 AM UTC 24 20679606920 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2051575183 Sep 19 12:42:56 AM UTC 24 Sep 19 01:09:02 AM UTC 24 22445970158 ps
T920 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2681905618 Sep 19 12:51:40 AM UTC 24 Sep 19 01:09:48 AM UTC 24 6097414700 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1318036371 Sep 19 12:48:24 AM UTC 24 Sep 19 01:11:03 AM UTC 24 10637227031 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_stream.131404121 Sep 19 12:02:07 AM UTC 24 Sep 19 01:11:16 AM UTC 24 19156853652 ps
T921 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1939106939 Sep 19 12:32:05 AM UTC 24 Sep 19 01:16:05 AM UTC 24 29725114185 ps
T922 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3700610727 Sep 19 12:12:39 AM UTC 24 Sep 19 01:17:49 AM UTC 24 43643049730 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.1274657404 Sep 19 12:54:33 AM UTC 24 Sep 19 01:18:57 AM UTC 24 5936840440 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.2011751752 Sep 19 12:49:21 AM UTC 24 Sep 19 01:21:05 AM UTC 24 24994833461 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.4174128314 Sep 19 12:28:46 AM UTC 24 Sep 19 01:23:00 AM UTC 24 11340428104 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3827399400 Sep 19 12:15:13 AM UTC 24 Sep 19 01:27:06 AM UTC 24 18126106083 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2163311720 Sep 19 12:15:12 AM UTC 24 Sep 19 01:30:35 AM UTC 24 17366496870 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_rma_unlocked.1577548564 Sep 19 12:01:41 AM UTC 24 Sep 19 01:36:52 AM UTC 24 43039837224 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_volatile_raw_unlock.1803240746 Sep 19 01:37:36 AM UTC 24 Sep 19 01:39:39 AM UTC 24 2955237043 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_raw_unlock.3114053678 Sep 19 01:40:23 AM UTC 24 Sep 19 01:45:43 AM UTC 24 5712006186 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.3628032784 Sep 19 01:11:45 AM UTC 24 Sep 19 01:46:46 AM UTC 24 11058182840 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.791275556 Sep 19 01:01:10 AM UTC 24 Sep 19 01:47:31 AM UTC 24 12016266740 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3745115647 Sep 19 01:00:38 AM UTC 24 Sep 19 01:47:55 AM UTC 24 10843454386 ps
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T250 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_rma.1197849347 Sep 19 12:09:08 AM UTC 24 Sep 19 01:54:31 AM UTC 24 46638156067 ps
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T926 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_smoketest.897819348 Sep 19 01:48:37 AM UTC 24 Sep 19 01:55:44 AM UTC 24 2739301376 ps
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T928 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_asm_init_test_unlocked0.3806288118 Sep 19 01:04:32 AM UTC 24 Sep 19 01:58:35 AM UTC 24 11327083011 ps
T929 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_keymgr_functest.684848399 Sep 19 01:47:28 AM UTC 24 Sep 19 01:58:49 AM UTC 24 5395823750 ps
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T390 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.19652343 Sep 19 01:00:37 AM UTC 24 Sep 19 02:04:18 AM UTC 24 14640908714 ps
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T939 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_smoketest.3419543341 Sep 19 02:00:21 AM UTC 24 Sep 19 02:04:39 AM UTC 24 2879802096 ps
T940 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_flash.2646114158 Sep 19 02:01:05 AM UTC 24 Sep 19 02:05:30 AM UTC 24 2254347880 ps
T941 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.4257873583 Sep 19 01:02:07 AM UTC 24 Sep 19 02:05:34 AM UTC 24 14591721620 ps
T942 /workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_concurrency.3594054504 Sep 19 02:01:47 AM UTC 24 Sep 19 02:05:49 AM UTC 24 3099110594 ps
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