Unified Coverage Report :: Group Instance : rv_core_ibex__cored

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	500	1			T572	1		T560	1		T569	1
small_delay	683	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

---

Summary for Variable cp_rsp_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_rsp_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1

Summary for Variable cp_req_dly

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_req_dly

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
big_delay	200	1			T572	1		T569	1		T598	1
small_delay	983	1			T274	1		T275	1		T563	1
zero	617	1			T91	1		T92	1		T93	1