| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| big_delay | 500 | 1 | T572 | 1 | T560 | 1 | T569 | 1 | ||||
| small_delay | 683 | 1 | T274 | 1 | T275 | 1 | T563 | 1 | ||||
| zero | 617 | 1 | T91 | 1 | T92 | 1 | T93 | 1 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |