Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	491	1			T827	1		T561	2		T853	2
all_values[1]	506	1			T690	1		T867	1		T602	3
all_values[2]	474	1			T827	1		T561	1		T461	1
all_values[3]	517	1			T461	1		T602	2		T853	2
all_values[4]	538	1			T499	1		T602	1		T490	3
all_values[5]	496	1			T827	1		T561	2		T499	1
all_values[6]	520	1			T827	1		T561	2		T499	2
all_values[7]	496	1			T561	2		T488	1		T602	2
all_values[8]	514	1			T499	1		T602	6		T853	1
all_values[9]	504	1			T561	2		T488	1		T499	2
all_values[10]	494	1			T827	1		T561	1		T488	1
all_values[11]	532	1			T461	1		T602	1		T853	2
all_values[12]	520	1			T827	1		T561	3		T867	1
all_values[13]	489	1			T827	1		T561	3		T602	2
all_values[14]	554	1			T827	1		T561	1		T690	1
all_values[15]	491	1			T473	1		T827	2		T499	1
all_values[16]	515	1			T827	1		T561	1		T499	1
all_values[17]	518	1			T561	1		T602	1		T853	2
all_values[18]	528	1			T561	1		T488	1		T602	3
all_values[19]	507	1			T561	2		T690	1		T499	1
all_values[20]	509	1			T636	2		T490	3		T612	3
all_values[21]	513	1			T827	1		T561	3		T461	1
all_values[22]	512	1			T409	1		T827	2		T499	1
all_values[23]	484	1			T827	2		T561	2		T461	1
all_values[24]	514	1			T827	3		T561	1		T602	1
all_values[25]	509	1			T409	1		T561	2		T461	1
all_values[26]	530	1			T561	2		T602	1		T853	1
all_values[27]	537	1			T409	1		T561	2		T488	1
all_values[28]	547	1			T827	1		T561	2		T602	3
all_values[29]	515	1			T561	1		T690	1		T488	1
all_values[30]	486	1			T827	1		T561	1		T488	1
all_values[31]	505	1			T561	1		T488	1		T499	1
all_values[32]	520	1			T473	1		T827	2		T561	4
all_values[33]	506	1			T827	2		T561	1		T499	2
all_values[34]	501	1			T827	3		T561	2		T602	2
all_values[35]	513	1			T561	1		T602	2		T853	2
all_values[36]	502	1			T561	3		T461	1		T499	1
all_values[37]	523	1			T473	3		T827	1		T561	1
all_values[38]	507	1			T827	4		T499	1		T602	2
all_values[39]	499	1			T561	1		T461	1		T602	1
all_values[40]	499	1			T850	1		T827	2		T561	1
all_values[41]	534	1			T827	1		T602	7		T853	1
all_values[42]	497	1			T827	1		T561	2		T461	1
all_values[43]	528	1			T827	2		T561	1		T461	1
all_values[44]	503	1			T561	1		T488	2		T499	1
all_values[45]	517	1			T473	2		T827	1		T561	2
all_values[46]	509	1			T561	3		T461	2		T499	1
all_values[47]	538	1			T827	2		T561	1		T488	1
all_values[48]	520	1			T827	1		T488	1		T499	2
all_values[49]	516	1			T409	1		T827	1		T461	1