Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3678	1			T526	3		T827	7		T561	3
all_values[1]	3758	1			T474	3		T275	2		T526	1
all_values[2]	3738	1			T474	1		T275	3		T458	1
all_values[3]	3722	1			T474	2		T275	1		T526	2
all_values[4]	3749	1			T474	2		T275	1		T526	2
all_values[5]	3827	1			T474	4		T275	1		T526	1
all_values[6]	3694	1			T474	1		T275	1		T526	1
all_values[7]	3749	1			T474	4		T275	1		T526	2
all_values[8]	3729	1			T474	1		T526	4		T458	2
all_values[9]	3813	1			T474	4		T275	1		T526	2
all_values[10]	3697	1			T474	2		T275	1		T526	2
all_values[11]	3759	1			T474	4		T275	1		T526	1
all_values[12]	3852	1			T474	1		T275	1		T526	1
all_values[13]	3793	1			T474	2		T275	2		T526	3
all_values[14]	3707	1			T474	1		T275	2		T827	10
all_values[15]	3797	1			T474	2		T275	1		T458	1
all_values[16]	3742	1			T474	1		T275	3		T827	8
all_values[17]	3760	1			T474	5		T275	1		T526	2
all_values[18]	3725	1			T526	3		T827	11		T561	5
all_values[19]	3794	1			T474	2		T275	3		T526	2
all_values[20]	3766	1			T474	4		T275	2		T458	1
all_values[21]	3807	1			T474	2		T275	2		T526	3
all_values[22]	3704	1			T474	5		T275	1		T526	1
all_values[23]	3799	1			T474	1		T526	3		T458	1
all_values[24]	3746	1			T474	7		T275	2		T526	1
all_values[25]	3803	1			T275	2		T526	3		T458	1
all_values[26]	3615	1			T474	1		T458	2		T827	10
all_values[27]	3794	1			T474	2		T526	1		T458	1
all_values[28]	3752	1			T474	2		T275	2		T526	2
all_values[29]	3667	1			T474	2		T526	4		T458	1
all_values[30]	3645	1			T474	1		T275	2		T526	1
all_values[31]	3688	1			T474	2		T275	1		T526	3
all_values[32]	3799	1			T474	4		T275	4		T526	1
all_values[33]	3789	1			T474	1		T526	4		T458	1
all_values[34]	3765	1			T474	2		T275	3		T526	1
all_values[35]	3777	1			T474	3		T275	1		T526	1
all_values[36]	3701	1			T474	1		T275	1		T526	1
all_values[37]	3636	1			T474	2		T275	1		T526	1
all_values[38]	3684	1			T474	5		T275	4		T526	3
all_values[39]	3795	1			T474	4		T526	3		T827	15
all_values[40]	3541	1			T474	1		T275	2		T526	3
all_values[41]	3709	1			T474	3		T275	3		T526	1
all_values[42]	3743	1			T474	1		T275	1		T458	1
all_values[43]	3733	1			T474	1		T275	1		T526	1
all_values[44]	3795	1			T474	2		T275	1		T458	1
all_values[45]	3643	1			T474	1		T275	2		T526	1
all_values[46]	3717	1			T474	7		T275	4		T526	1
all_values[47]	3756	1			T474	3		T526	1		T827	9
all_values[48]	3735	1			T474	5		T526	1		T458	1
all_values[49]	3801	1			T474	2		T275	2		T526	1
all_values[50]	3744	1			T474	1		T275	3		T526	1
all_values[51]	3625	1			T474	3		T275	1		T526	1
all_values[52]	3812	1			T474	1		T275	1		T526	1
all_values[53]	3691	1			T474	3		T526	1		T458	1
all_values[54]	3674	1			T474	4		T275	1		T526	1
all_values[55]	3631	1			T474	4		T275	2		T458	1
all_values[56]	3854	1			T474	1		T275	3		T827	9
all_values[57]	3677	1			T474	4		T275	1		T526	1
all_values[58]	3628	1			T474	2		T458	1		T827	12
all_values[59]	3742	1			T474	3		T275	2		T458	1
all_values[60]	3649	1			T275	4		T526	1		T458	1
all_values[61]	3684	1			T474	1		T275	1		T526	1
all_values[62]	3707	1			T474	2		T275	2		T458	1
all_values[63]	3639	1			T474	1		T275	1		T526	2