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 LINE       12261
 EXPRESSION (mio_pad_attr_2_we & mio_pad_attr_regwen_2_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T29,T45,T46

 LINE       12430
 EXPRESSION (mio_pad_attr_3_we & mio_pad_attr_regwen_3_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T499,T500,T501

 LINE       12599
 EXPRESSION (mio_pad_attr_4_we & mio_pad_attr_regwen_4_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T502,T503,T492

 LINE       12768
 EXPRESSION (mio_pad_attr_5_we & mio_pad_attr_regwen_5_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T445,T490,T504

 LINE       12937
 EXPRESSION (mio_pad_attr_6_we & mio_pad_attr_regwen_6_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T501,T505,T506

 LINE       13106
 EXPRESSION (mio_pad_attr_7_we & mio_pad_attr_regwen_7_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T13,T49,T50

 LINE       13275
 EXPRESSION (mio_pad_attr_8_we & mio_pad_attr_regwen_8_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T461,T497,T507

 LINE       13444
 EXPRESSION (mio_pad_attr_9_we & mio_pad_attr_regwen_9_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T29,T45,T46

 LINE       13613
 EXPRESSION (mio_pad_attr_10_we & mio_pad_attr_regwen_10_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T29,T10,T11

 LINE       13782
 EXPRESSION (mio_pad_attr_11_we & mio_pad_attr_regwen_11_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T494,T508,T506

 LINE       13951
 EXPRESSION (mio_pad_attr_12_we & mio_pad_attr_regwen_12_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T29,T10,T11

 LINE       14120
 EXPRESSION (mio_pad_attr_13_we & mio_pad_attr_regwen_13_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T29,T12,T45

 LINE       14289
 EXPRESSION (mio_pad_attr_14_we & mio_pad_attr_regwen_14_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T29,T12,T45

 LINE       14458
 EXPRESSION (mio_pad_attr_15_we & mio_pad_attr_regwen_15_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T29,T12,T45

 LINE       14627
 EXPRESSION (mio_pad_attr_16_we & mio_pad_attr_regwen_16_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T509,T510,T511

 LINE       14796
 EXPRESSION (mio_pad_attr_17_we & mio_pad_attr_regwen_17_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T512,T513,T514

 LINE       14965
 EXPRESSION (mio_pad_attr_18_we & mio_pad_attr_regwen_18_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T495,T487,T506

 LINE       15134
 EXPRESSION (mio_pad_attr_19_we & mio_pad_attr_regwen_19_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T503,T515,T516

 LINE       15303
 EXPRESSION (mio_pad_attr_20_we & mio_pad_attr_regwen_20_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T93,T488,T517

 LINE       15472
 EXPRESSION (mio_pad_attr_21_we & mio_pad_attr_regwen_21_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T490,T495,T518

 LINE       15641
 EXPRESSION (mio_pad_attr_22_we & mio_pad_attr_regwen_22_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T54,T51,T52

 LINE       15810
 EXPRESSION (mio_pad_attr_23_we & mio_pad_attr_regwen_23_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T54,T51,T52

 LINE       15979
 EXPRESSION (mio_pad_attr_24_we & mio_pad_attr_regwen_24_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T54,T51,T52

 LINE       16148
 EXPRESSION (mio_pad_attr_25_we & mio_pad_attr_regwen_25_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       16317
 EXPRESSION (mio_pad_attr_26_we & mio_pad_attr_regwen_26_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T487,T519,T520

 LINE       16486
 EXPRESSION (mio_pad_attr_27_we & mio_pad_attr_regwen_27_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T482,T510,T506

 LINE       16655
 EXPRESSION (mio_pad_attr_28_we & mio_pad_attr_regwen_28_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T521,T522,T486

 LINE       16824
 EXPRESSION (mio_pad_attr_29_we & mio_pad_attr_regwen_29_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T492,T506,T523

 LINE       16993
 EXPRESSION (mio_pad_attr_30_we & mio_pad_attr_regwen_30_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T481,T524,T525

 LINE       17162
 EXPRESSION (mio_pad_attr_31_we & mio_pad_attr_regwen_31_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T526,T527,T486

 LINE       17331
 EXPRESSION (mio_pad_attr_32_we & mio_pad_attr_regwen_32_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T528,T529,T530

 LINE       17500
 EXPRESSION (mio_pad_attr_33_we & mio_pad_attr_regwen_33_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T509,T506,T529

 LINE       17669
 EXPRESSION (mio_pad_attr_34_we & mio_pad_attr_regwen_34_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T531,T532,T486

 LINE       17838
 EXPRESSION (mio_pad_attr_35_we & mio_pad_attr_regwen_35_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T495,T515,T487

 LINE       18007
 EXPRESSION (mio_pad_attr_36_we & mio_pad_attr_regwen_36_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T533,T534,T535

 LINE       18176
 EXPRESSION (mio_pad_attr_37_we & mio_pad_attr_regwen_37_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T274,T536,T488

 LINE       18345
 EXPRESSION (mio_pad_attr_38_we & mio_pad_attr_regwen_38_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T537,T515,T519

 LINE       18514
 EXPRESSION (mio_pad_attr_39_we & mio_pad_attr_regwen_39_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T519,T528,T538

 LINE       18683
 EXPRESSION (mio_pad_attr_40_we & mio_pad_attr_regwen_40_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T499,T539,T510

 LINE       18852
 EXPRESSION (mio_pad_attr_41_we & mio_pad_attr_regwen_41_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T540,T541,T542

 LINE       19021
 EXPRESSION (mio_pad_attr_42_we & mio_pad_attr_regwen_42_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T97,T532,T529

 LINE       19190
 EXPRESSION (mio_pad_attr_43_we & mio_pad_attr_regwen_43_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T490,T543,T544

 LINE       19359
 EXPRESSION (mio_pad_attr_44_we & mio_pad_attr_regwen_44_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T545,T546,T547

 LINE       19528
 EXPRESSION (mio_pad_attr_45_we & mio_pad_attr_regwen_45_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T483,T513,T548

 LINE       19697
 EXPRESSION (mio_pad_attr_46_we & mio_pad_attr_regwen_46_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T506,T549,T541

 LINE       20330
 EXPRESSION (dio_pad_attr_0_we & dio_pad_attr_regwen_0_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       20499
 EXPRESSION (dio_pad_attr_1_we & dio_pad_attr_regwen_1_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       20668
 EXPRESSION (dio_pad_attr_2_we & dio_pad_attr_regwen_2_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T29,T10,T11

 LINE       20837
 EXPRESSION (dio_pad_attr_3_we & dio_pad_attr_regwen_3_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T29,T10,T11

 LINE       21006
 EXPRESSION (dio_pad_attr_4_we & dio_pad_attr_regwen_4_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T29,T10,T11

 LINE       21175
 EXPRESSION (dio_pad_attr_5_we & dio_pad_attr_regwen_5_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T29,T10,T11

 LINE       21344
 EXPRESSION (dio_pad_attr_6_we & dio_pad_attr_regwen_6_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T499,T497,T550

 LINE       21513
 EXPRESSION (dio_pad_attr_7_we & dio_pad_attr_regwen_7_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T500,T515,T543

 LINE       21682
 EXPRESSION (dio_pad_attr_8_we & dio_pad_attr_regwen_8_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T492,T551,T541

 LINE       21851
 EXPRESSION (dio_pad_attr_9_we & dio_pad_attr_regwen_9_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T552,T553,T544

 LINE       22020
 EXPRESSION (dio_pad_attr_10_we & dio_pad_attr_regwen_10_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T17,T47,T48

 LINE       22189
 EXPRESSION (dio_pad_attr_11_we & dio_pad_attr_regwen_11_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T17,T47,T48

 LINE       22358
 EXPRESSION (dio_pad_attr_12_we & dio_pad_attr_regwen_12_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T480,T530,T540

 LINE       22527
 EXPRESSION (dio_pad_attr_13_we & dio_pad_attr_regwen_13_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T510,T506,T554

 LINE       22696
 EXPRESSION (dio_pad_attr_14_we & dio_pad_attr_regwen_14_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T29,T45,T46

 LINE       22865
 EXPRESSION (dio_pad_attr_15_we & dio_pad_attr_regwen_15_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T29,T45,T46

 LINE       25669
 EXPRESSION (mio_pad_sleep_en_0_we & mio_pad_sleep_regwen_0_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T407,T419,T477
1	1	Covered	T2,T27,T70

 LINE       25701
 EXPRESSION (mio_pad_sleep_en_1_we & mio_pad_sleep_regwen_1_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T163,T164,T433
1	1	Covered	T2,T27,T70

 LINE       25733
 EXPRESSION (mio_pad_sleep_en_2_we & mio_pad_sleep_regwen_2_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T406,T167,T168
1	1	Covered	T2,T27,T70

 LINE       25765
 EXPRESSION (mio_pad_sleep_en_3_we & mio_pad_sleep_regwen_3_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T406,T168,T169
1	1	Covered	T2,T27,T70

 LINE       25797
 EXPRESSION (mio_pad_sleep_en_4_we & mio_pad_sleep_regwen_4_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T164,T169,T432
1	1	Covered	T2,T27,T70

 LINE       25829
 EXPRESSION (mio_pad_sleep_en_5_we & mio_pad_sleep_regwen_5_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T407,T168,T419
1	1	Covered	T2,T27,T70

 LINE       25861
 EXPRESSION (mio_pad_sleep_en_6_we & mio_pad_sleep_regwen_6_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T164,T407,T432
1	1	Covered	T2,T27,T70

 LINE       25893
 EXPRESSION (mio_pad_sleep_en_7_we & mio_pad_sleep_regwen_7_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T163,T164,T433
1	1	Covered	T2,T5,T27

 LINE       25925
 EXPRESSION (mio_pad_sleep_en_8_we & mio_pad_sleep_regwen_8_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T168,T434
1	1	Covered	T2,T39,T20

 LINE       25957
 EXPRESSION (mio_pad_sleep_en_9_we & mio_pad_sleep_regwen_9_qs)
             ----------1----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T164,T167,T168
1	1	Covered	T2,T39,T20

 LINE       25989
 EXPRESSION (mio_pad_sleep_en_10_we & mio_pad_sleep_regwen_10_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T433,T419,T477
1	1	Covered	T2,T39,T20

 LINE       26021
 EXPRESSION (mio_pad_sleep_en_11_we & mio_pad_sleep_regwen_11_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T407,T168,T432
1	1	Covered	T2,T39,T20

 LINE       26053
 EXPRESSION (mio_pad_sleep_en_12_we & mio_pad_sleep_regwen_12_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T164,T169
1	1	Covered	T2,T39,T20

 LINE       26085
 EXPRESSION (mio_pad_sleep_en_13_we & mio_pad_sleep_regwen_13_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T168,T432,T419
1	1	Covered	T2,T39,T20

 LINE       26117
 EXPRESSION (mio_pad_sleep_en_14_we & mio_pad_sleep_regwen_14_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T407,T433,T420
1	1	Covered	T2,T39,T20

 LINE       26149
 EXPRESSION (mio_pad_sleep_en_15_we & mio_pad_sleep_regwen_15_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T406,T168,T169
1	1	Covered	T2,T39,T20

 LINE       26181
 EXPRESSION (mio_pad_sleep_en_16_we & mio_pad_sleep_regwen_16_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T164,T406
1	1	Covered	T2,T39,T20

 LINE       26213
 EXPRESSION (mio_pad_sleep_en_17_we & mio_pad_sleep_regwen_17_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T163,T406,T167
1	1	Covered	T2,T39,T20

 LINE       26245
 EXPRESSION (mio_pad_sleep_en_18_we & mio_pad_sleep_regwen_18_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T406,T407
1	1	Covered	T2,T39,T20

 LINE       26277
 EXPRESSION (mio_pad_sleep_en_19_we & mio_pad_sleep_regwen_19_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T163,T168
1	1	Covered	T2,T39,T20

 LINE       26309
 EXPRESSION (mio_pad_sleep_en_20_we & mio_pad_sleep_regwen_20_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T163,T406,T168
1	1	Covered	T2,T39,T20

 LINE       26341
 EXPRESSION (mio_pad_sleep_en_21_we & mio_pad_sleep_regwen_21_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T168,T433
1	1	Covered	T2,T39,T20

 LINE       26373
 EXPRESSION (mio_pad_sleep_en_22_we & mio_pad_sleep_regwen_22_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T406,T168,T419
1	1	Covered	T2,T39,T20

 LINE       26405
 EXPRESSION (mio_pad_sleep_en_23_we & mio_pad_sleep_regwen_23_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T407,T432,T433
1	1	Covered	T2,T39,T20

 LINE       26437
 EXPRESSION (mio_pad_sleep_en_24_we & mio_pad_sleep_regwen_24_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T163,T407,T169
1	1	Covered	T2,T39,T20

 LINE       26469
 EXPRESSION (mio_pad_sleep_en_25_we & mio_pad_sleep_regwen_25_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T164,T167
1	1	Covered	T2,T39,T20

 LINE       26501
 EXPRESSION (mio_pad_sleep_en_26_we & mio_pad_sleep_regwen_26_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T168,T169,T433
1	1	Covered	T2,T39,T20

 LINE       26533
 EXPRESSION (mio_pad_sleep_en_27_we & mio_pad_sleep_regwen_27_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T167,T432,T434
1	1	Covered	T2,T39,T20

 LINE       26565
 EXPRESSION (mio_pad_sleep_en_28_we & mio_pad_sleep_regwen_28_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T163,T164,T407
1	1	Covered	T2,T39,T20

 LINE       26597
 EXPRESSION (mio_pad_sleep_en_29_we & mio_pad_sleep_regwen_29_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T164,T406,T169
1	1	Covered	T2,T39,T20

 LINE       26629
 EXPRESSION (mio_pad_sleep_en_30_we & mio_pad_sleep_regwen_30_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T407,T167,T168
1	1	Covered	T2,T39,T20

 LINE       26661
 EXPRESSION (mio_pad_sleep_en_31_we & mio_pad_sleep_regwen_31_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T163,T168
1	1	Covered	T2,T39,T20

 LINE       26693
 EXPRESSION (mio_pad_sleep_en_32_we & mio_pad_sleep_regwen_32_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T163,T406,T407
1	1	Covered	T2,T39,T20

 LINE       26725
 EXPRESSION (mio_pad_sleep_en_33_we & mio_pad_sleep_regwen_33_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T167,T168
1	1	Covered	T2,T39,T20

 LINE       26757
 EXPRESSION (mio_pad_sleep_en_34_we & mio_pad_sleep_regwen_34_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T406,T169,T433
1	1	Covered	T2,T39,T20

 LINE       26789
 EXPRESSION (mio_pad_sleep_en_35_we & mio_pad_sleep_regwen_35_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T163,T164,T168
1	1	Covered	T2,T39,T20

 LINE       26821
 EXPRESSION (mio_pad_sleep_en_36_we & mio_pad_sleep_regwen_36_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T164,T407,T167
1	1	Covered	T2,T39,T20

 LINE       26853
 EXPRESSION (mio_pad_sleep_en_37_we & mio_pad_sleep_regwen_37_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T407,T433,T436
1	1	Covered	T2,T39,T20

 LINE       26885
 EXPRESSION (mio_pad_sleep_en_38_we & mio_pad_sleep_regwen_38_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T163,T434,T477
1	1	Covered	T2,T39,T20

 LINE       26917
 EXPRESSION (mio_pad_sleep_en_39_we & mio_pad_sleep_regwen_39_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T164,T406,T169
1	1	Covered	T2,T39,T20

 LINE       26949
 EXPRESSION (mio_pad_sleep_en_40_we & mio_pad_sleep_regwen_40_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T406,T168
1	1	Covered	T2,T39,T20

 LINE       26981
 EXPRESSION (mio_pad_sleep_en_41_we & mio_pad_sleep_regwen_41_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T164,T407,T168
1	1	Covered	T2,T39,T20

 LINE       27013
 EXPRESSION (mio_pad_sleep_en_42_we & mio_pad_sleep_regwen_42_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T164,T169,T413
1	1	Covered	T2,T39,T20

 LINE       27045
 EXPRESSION (mio_pad_sleep_en_43_we & mio_pad_sleep_regwen_43_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T163,T169,T420
1	1	Covered	T2,T39,T20

 LINE       27077
 EXPRESSION (mio_pad_sleep_en_44_we & mio_pad_sleep_regwen_44_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T432,T434,T436
1	1	Covered	T2,T39,T20

 LINE       27109
 EXPRESSION (mio_pad_sleep_en_45_we & mio_pad_sleep_regwen_45_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T406,T407,T433
1	1	Covered	T2,T39,T20

 LINE       27141
 EXPRESSION (mio_pad_sleep_en_46_we & mio_pad_sleep_regwen_46_qs)
             -----------1----------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T69,T164,T167
1	1	Covered	T2,T39,T20

 LINE       27173
 EXPRESSION (mio_pad_sleep_mode_0_we & mio_pad_sleep_regwen_0_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T407,T432,T433
1	1	Covered	T2,T27,T70

 LINE       27205
 EXPRESSION (mio_pad_sleep_mode_1_we & mio_pad_sleep_regwen_1_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T163,T164,T420
1	1	Covered	T2,T27,T70

 LINE       27237
 EXPRESSION (mio_pad_sleep_mode_2_we & mio_pad_sleep_regwen_2_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T169,T433,T413
1	1	Covered	T2,T27,T70

 LINE       27269
 EXPRESSION (mio_pad_sleep_mode_3_we & mio_pad_sleep_regwen_3_qs)
             -----------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T406,T168,T169
1	1	Covered	T2,T27,T70