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 LINE       1303
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T80,T81
1	0	1	Covered	T44,T80,T81
1	1	0	Covered	T93,T435,T577
1	1	1	Covered	T470,T67,T471

 LINE       1308
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T80,T81
1	0	1	Covered	T81,T295,T296
1	1	0	Covered	T537,T458,T559
1	1	1	Covered	T69,T93,T474

 LINE       1317
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T69,T93,T474
1	1	0	Not Covered
1	1	1	Covered	T2,T5,T6

 LINE       1318
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T69,T93,T474
1	1	0	Covered	T655,T656,T657
1	1	1	Covered	T2,T5,T6

 LINE       1319
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T5,T6
1	0	1	Covered	T69,T537,T415
1	1	0	Covered	T658
1	1	1	Covered	T2,T3,T4