Go
back
71 if (offset < NumSrc) begin : gen_assign
72 185/186 ==> assign vld_tree[Pa] = valid_i[offset];
Tests: T127 T329 T336 | T127 T329 T336 | T127 T329 T337 | T127 T329 T337 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T127 T329 T336 | T66 T128 T129 | T66 T128 T129 | T66 T128 T129 | T66 T128 T129 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T66 T128 T129 | T59 T329 T60 | T59 T329 T60 | T59 T329 T60 | T59 T329 T60 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T59 T329 T60 | T40 T329 T61 | T40 T329 T61 | T40 T329 T61 | T40 T329 T61 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T40 T329 T61 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T10 T124 T222 | T124 T181 T182 | T124 T181 T182 | T124 T181 T182 | T124 T181 T182 | T13 T124 T49 | T124 T181 T182 | T124 T181 T182 | T55 T340 T134 | T55 T340 T134 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T55 T56 T340 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T30 T340 T135 | T30 T340 T135 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T30 T340 T57 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T31 T340 T58 | T31 T340 T58 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T31 T340 T58 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T124 T181 T130 | T6 T124 T131 | T124 T181 T182 | T124 T181 T182 | T124 T181 T182 | T81 T236 T117 | T44 T80 T183 | T340 T295 T341 | T270 T340 T343 | T124 T181 T182 | T124 T181 T182 | T124 T181 T182 | T124 T181 T182 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T5 T27 T100 | T63 T329 T230 | T136 T340 T137 | T297 T260 T358 | T221 T260 T359 | T170 T124 T344 | T124 T181 T182 | T7 T143 T333 | T7 T143 T333 | T143 T333 T340 | T143 T333 T340 | T7 T143 T333 | T340 T341 T342 | T115 T334 T340 | T340 T341 T342 | T340 T341 T342 | T124 T181 T182 | T124 T181 T182 | T124 T181 T182 | T116 T124 T172 | T124 T181 T182 | T340 T341 T342 | T340 T345 T346 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T345 T346 | T340 T341 T342 | T340 T345 T346 | T340 T341 T342
73 assign idx_tree[Pa] = offset;
74 186/186 assign max_tree[Pa] = values_i[offset];
Tests: T277 T278 T279 | T127 T277 T124 | T127 T277 T124 | T127 T277 T124 | T127 T277 T124 | T127 T277 T124 | T127 T277 T124 | T127 T277 T124 | T127 T277 T124 | T127 T277 T124 | T66 T128 T129 | T66 T128 T129 | T66 T128 T129 | T66 T128 T129 | T66 T128 T129 | T66 T128 T129 | T66 T128 T129 | T66 T128 T129 | T66 T128 T129 | T59 T277 T124 | T59 T277 T124 | T59 T277 T124 | T59 T277 T124 | T59 T277 T124 | T59 T277 T124 | T59 T277 T124 | T59 T277 T124 | T59 T277 T124 | T40 T277 T124 | T40 T277 T124 | T40 T277 T124 | T40 T277 T124 | T40 T277 T124 | T40 T277 T124 | T40 T277 T124 | T40 T277 T124 | T40 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T13 T28 T10 | T13 T277 T124 | T13 T277 T124 | T13 T10 T11 | T13 T10 T11 | T13 T277 T124 | T277 T124 T329 | T277 T124 T329 | T55 T277 T124 | T55 T277 T124 | T277 T124 T329 | T55 T277 T124 | T55 T277 T124 | T55 T277 T124 | T55 T277 T124 | T55 T277 T124 | T277 T124 T329 | T55 T56 T277 | T56 T277 T124 | T277 T124 T329 | T56 T277 T124 | T56 T277 T124 | T56 T277 T124 | T30 T277 T124 | T30 T277 T124 | T277 T124 T329 | T30 T277 T124 | T30 T277 T124 | T30 T277 T124 | T30 T277 T124 | T30 T277 T124 | T277 T124 T329 | T30 T277 T124 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T31 T277 T124 | T31 T277 T124 | T277 T124 T329 | T31 T277 T124 | T31 T277 T124 | T31 T277 T124 | T31 T277 T124 | T31 T277 T124 | T277 T124 T329 | T31 T277 T124 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T6 T277 T124 | T6 T277 T124 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T44 T80 T81 | T44 T80 T81 | T44 T80 T81 | T44 T80 T81 | T10 T11 T277 | T10 T11 T277 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T2 T5 T27 | T63 T277 T124 | T136 T277 T124 | T44 T80 T81 | T221 T44 T80 | T170 T277 T124 | T277 T124 T329 | T7 T143 T333 | T7 T143 T333 | T7 T143 T333 | T7 T143 T333 | T7 T143 T333 | T277 T124 T329 | T115 T334 T277 | T115 T334 T277 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T116 T277 T124 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329
75 end else begin : gen_tie_off
76 assign vld_tree[Pa] = '0;
77 assign idx_tree[Pa] = '0;
78 assign max_tree[Pa] = '0;
79 end
80 // This creates the node assignments.
81 end else begin : gen_nodes
82 logic sel; // Local helper variable
83 // In case only one of the parents is valid, forward that one
84 // In case both parents are valid, forward the one with higher value
85 185/185(70 unreachable) assign sel = (~vld_tree[C0] & vld_tree[C1]) |
Tests: T5 T6 T7 | T6 T66 T55 | T66 T28 T127 | T6 T55 T30 | T5 T7 T221 | T66 T127 T59 | T28 T40 T277 | T55 T30 T13 | T6 T30 T31 | T5 T221 T27 | T7 T143 T333 | T66 T127 T128 | T66 T59 T128 | T28 T40 T277 | T28 T277 T124 | T55 T13 T28 | T55 T30 T56 | T30 T31 T277 | T6 T31 T81 | T44 T80 T81 | T5 T221 T27 | T7 T143 T333 | T277 T124 T329 | T127 T277 T124 | T66 T127 T128 | T66 T59 T128 | T59 T40 T277 | T28 T40 T277 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T10 T277 | T55 T13 T10 | T55 T56 T277 | T30 T277 T124 | T30 T277 T124 | T31 T277 T124 | T31 T277 T124 | T6 T81 T236 | T10 T44 T11 | T277 T124 T329 | T277 T124 T329 | T5 T221 T27 | T7 T143 T333 | T116 T277 T124 | T277 T124 T329 | T127 T277 T124 | T127 T277 T124 | T66 T127 T128 | T66 T128 T129 | T66 T59 T128 | T59 T277 T124 | T59 T277 T124 | T40 T277 T124 | T40 T277 T124 | T28 T40 T277 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T13 T28 T10 | T13 T10 T11 | T55 T277 T124 | T55 T277 T124 | T55 T56 T277 | T56 T277 T124 | T30 T277 T124 | T30 T277 T124 | T30 T277 T124 | T31 T277 T124 | T31 T277 T124 | T31 T277 T124 | T31 T277 T124 | T6 T277 T124 | T81 T236 T117 | T44 T80 T81 | T10 T11 T277 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T5 T27 T136 | T221 T44 T80 | T7 T143 T333 | T7 T143 T333 | T277 T124 T329 | T116 T277 T124 | T277 T124 T329 | T277 T124 T329 | T127 T277 T124 | T127 T277 T124 | T127 T277 T124 | T127 T277 T124 | T127 T277 T124 | T66 T128 T129 | T66 T128 T129 | T66 T128 T129 | T66 T128 T129 | T66 T59 T128 | T59 T277 T124 | T59 T277 T124 | T59 T277 T124 | T59 T277 T124 | T40 T277 T124 | T40 T277 T124 | T40 T277 T124 | T40 T277 T124 | T28 T40 T277 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T13 T28 T10 | T13 T277 T124 | T13 T10 T11 | T13 T277 T124 | T55 T277 T124 | T55 T277 T124 | T55 T277 T124 | T55 T277 T124 | T55 T277 T124 | T55 T56 T277 | T56 T277 T124 | T56 T277 T124 | T30 T277 T124 | T30 T277 T124 | T30 T277 T124 | T30 T277 T124 | T30 T277 T124 | T277 T124 T329 | T277 T124 T329 | T31 T277 T124 | T31 T277 T124 | T31 T277 T124 | T31 T277 T124 | T31 T277 T124 | T31 T277 T124 | T277 T124 T329 | T277 T124 T329 | T6 T277 T124 | T277 T124 T329 | T44 T80 T81 | T44 T80 T81 | T10 T44 T11 | T10 T11 T277 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T2 T5 T27 | T136 T63 T277 | T221 T44 T80 | T170 T277 T124 | T7 T143 T333 | T7 T143 T333 | T7 T143 T333 | T115 T334 T277 | T277 T124 T329 | T277 T124 T329 | T116 T277 T124 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329
86 (vld_tree[C0] & vld_tree[C1] & logic'(max_tree[C1] > max_tree[C0]));
87 // Forwarding muxes
88 // Note: these ternaries have triggered a synthesis bug in Vivado versions older
89 // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
90 188/188(67 unreachable) assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
Tests: T5 T6 T7 | T6 T66 T55 | T5 T7 T221 | T66 T28 T127 | T6 T55 T30 | T5 T7 T221 | T66 T127 T59 | T28 T40 T329 | T55 T30 T13 | T6 T30 T31 | T5 T221 T27 | T7 T143 T333 | T66 T127 T128 | T66 T59 T128 | T28 T40 T329 | T28 T340 T42 | T55 T13 T28 | T55 T30 T56 | T30 T31 T340 | T6 T31 T81 | T44 T80 T183 | T5 T221 T27 | T7 T143 T333 | T340 T345 T346 | T127 T329 T337 | T66 T127 T128 | T66 T59 T128 | T59 T40 T329 | T28 T40 T329 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T10 T124 | T55 T13 T124 | T55 T56 T340 | T30 T340 T135 | T30 T340 T57 | T31 T340 T58 | T31 T340 T58 | T6 T81 T236 | T44 T80 T183 | T329 T338 T339 | T329 T338 T339 | T5 T221 T27 | T7 T143 T333 | T116 T124 T340 | T340 T345 T346 | T340 T345 T346 | T127 T329 T337 | T127 T329 T337 | T66 T127 T128 | T66 T128 T129 | T66 T59 T128 | T59 T329 T60 | T59 T329 T60 | T40 T329 T61 | T329 T338 T339 | T28 T40 T329 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T10 T124 | T13 T124 T49 | T55 T124 T340 | T340 T341 T342 | T55 T56 T340 | T340 T341 T342 | T30 T340 T135 | T340 T341 T342 | T30 T340 T57 | T31 T340 T58 | T31 T340 T58 | T340 T341 T342 | T31 T340 T58 | T6 T124 T340 | T81 T236 T117 | T44 T80 T183 | T124 T329 T181 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T5 T27 T136 | T221 T297 T260 | T7 T143 T333 | T7 T143 T333 | T124 T340 T181 | T116 T124 T340 | T340 T341 T342 | T340 T345 T346 | T340 T345 T346 | T127 T329 T336 | T127 T329 T337 | T127 T329 T337 | T329 T338 T339 | T127 T329 T336 | T66 T128 T129 | T66 T128 T129 | T329 T338 T339 | T329 T338 T339 | T66 T59 T128 | T59 T329 T60 | T59 T329 T60 | T329 T338 T339 | T59 T329 T60 | T40 T329 T61 | T40 T329 T61 | T329 T338 T339 | T329 T338 T339 | T28 T40 T329 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T10 T124 | T124 T181 T182 | T124 T181 T182 | T13 T124 T49 | T55 T124 T340 | T55 T340 T134 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T55 T56 T340 | T340 T341 T342 | T340 T341 T342 | T30 T340 T135 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T30 T340 T57 | T340 T341 T342 | T340 T341 T342 | T31 T340 T58 | T31 T340 T58 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T31 T340 T58 | T340 T341 T342 | T340 T341 T342 | T6 T124 T131 | T124 T181 T182 | T81 T236 T117 | T44 T80 T183 | T124 T270 T340 | T124 T181 T182 | T124 T329 T181 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T5 T27 T100 | T136 T63 T329 | T221 T297 T260 | T170 T124 T344 | T7 T143 T333 | T143 T333 T340 | T7 T143 T333 | T115 T334 T340 | T124 T340 T181 | T124 T181 T182 | T116 T124 T172 | T340 T345 T346 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T345 T346 | T340 T345 T346
91 188/255 ==> assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
Tests: T5 T6 T7 | T6 T66 T55 | T5 T7 T221 | T66 T28 T127 | T6 T55 T30 | T5 T7 T221 | T66 T127 T59 | T28 T40 T329 | T55 T30 T13 | T6 T30 T31 | T5 T221 T27 | T7 T143 T333 | T66 T127 T128 | T66 T59 T128 | T28 T40 T329 | T28 T340 T42 | T55 T13 T28 | T55 T30 T56 | T30 T31 T340 | T6 T31 T81 | T124 T270 T329 | T5 T221 T27 | T7 T143 T333 | T340 T345 T346 | T127 T329 T337 | T66 T127 T128 | T66 T59 T128 | T59 T40 T329 | T28 T40 T329 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T10 T124 | T55 T13 T124 | T55 T56 T340 | T30 T340 T135 | T30 T340 T57 | T31 T340 T58 | T31 T340 T58 | T6 T81 T236 | T124 T270 T329 | T329 T338 T339 | T329 T338 T339 | T5 T221 T27 | T7 T143 T333 | T116 T124 T340 | T340 T345 T346 | T340 T341 T342 | T127 T329 T337 | T329 T338 T339 | T66 T127 T128 | T66 T128 T129 | T66 T59 T128 | T59 T329 T60 | T59 T329 T60 | T40 T329 T61 | T329 T338 T339 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T10 T124 T222 | T13 T124 T49 | T55 T340 T134 | T340 T341 T342 | T55 T56 T340 | T340 T341 T342 | T30 T340 T135 | T340 T341 T342 | T30 T340 T57 | T31 T340 T58 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T6 T124 T340 | T81 T236 T117 | T124 T270 T340 | T124 T329 T181 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T5 T27 T136 | T221 T260 T359 | T7 T143 T333 | T115 T334 T340 | T124 T181 T182 | T124 T340 T345 | T340 T341 T342 | T340 T345 T346 | T340 T341 T342 | T127 T329 T336 | T127 T329 T337 | T329 T338 T339 | T329 T338 T339 | T127 T329 T336 | T66 T128 T129 | T66 T128 T129 | T329 T338 T339 | T329 T338 T339 | T59 T329 T60 | T59 T329 T60 | T329 T338 T339 | T329 T338 T339 | T59 T329 T60 | T40 T329 T61 | T40 T329 T61 | T329 T338 T339 | T329 T338 T339 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T28 T340 T42 | T10 T124 T222 | T124 T181 T182 | T124 T181 T182 | T124 T181 T182 | T55 T340 T134 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T30 T340 T135 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T30 T340 T57 | T340 T341 T342 | T340 T341 T342 | T31 T340 T58 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T6 T124 T131 | T124 T181 T182 | T81 T236 T117 | T340 T295 T341 | T124 T181 T182 | T124 T181 T182 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T329 T338 T339 | T5 T27 T100 | T136 T340 T137 | T221 T260 T359 | T124 T181 T182 | T7 T143 T333 | T143 T333 T340 | T340 T341 T342 | T340 T341 T342 | T124 T181 T182 | T124 T181 T182 | T124 T181 T182 | T340 T345 T346 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342 | T340 T341 T342
92 188/255 ==> assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
Tests: T5 T6 T7 | T6 T66 T55 | T5 T7 T221 | T66 T28 T127 | T6 T55 T30 | T5 T7 T221 | T66 T127 T59 | T28 T40 T277 | T55 T30 T13 | T6 T30 T31 | T5 T221 T27 | T7 T143 T333 | T66 T127 T128 | T66 T59 T128 | T28 T40 T277 | T28 T277 T124 | T55 T13 T28 | T55 T30 T56 | T30 T31 T277 | T6 T31 T81 | T44 T80 T81 | T5 T221 T27 | T7 T143 T333 | T277 T124 T329 | T127 T277 T124 | T66 T127 T128 | T66 T59 T128 | T59 T40 T277 | T28 T40 T277 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T10 T277 | T55 T13 T10 | T55 T56 T277 | T30 T277 T124 | T30 T277 T124 | T31 T277 T124 | T31 T277 T124 | T6 T81 T236 | T10 T44 T11 | T277 T124 T329 | T277 T124 T329 | T5 T221 T27 | T7 T143 T333 | T116 T277 T124 | T277 T124 T329 | T277 T124 T329 | T127 T277 T124 | T127 T277 T124 | T66 T127 T128 | T66 T128 T129 | T66 T59 T128 | T59 T277 T124 | T59 T277 T124 | T40 T277 T124 | T40 T277 T124 | T28 T40 T277 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T13 T28 T10 | T13 T10 T11 | T55 T277 T124 | T55 T277 T124 | T55 T56 T277 | T56 T277 T124 | T30 T277 T124 | T30 T277 T124 | T30 T277 T124 | T31 T277 T124 | T31 T277 T124 | T31 T277 T124 | T31 T277 T124 | T6 T277 T124 | T81 T236 T117 | T44 T80 T81 | T10 T11 T277 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T5 T27 T136 | T221 T44 T80 | T7 T143 T333 | T7 T143 T333 | T277 T124 T329 | T116 T277 T124 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T127 T277 T124 | T127 T277 T124 | T127 T277 T124 | T127 T277 T124 | T127 T277 T124 | T66 T128 T129 | T66 T128 T129 | T66 T128 T129 | T66 T128 T129 | T66 T59 T128 | T59 T277 T124 | T59 T277 T124 | T59 T277 T124 | T59 T277 T124 | T40 T277 T124 | T40 T277 T124 | T40 T277 T124 | T40 T277 T124 | T28 T40 T277 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T28 T277 T124 | T13 T28 T10 | T13 T277 T124 | T13 T10 T11 | T13 T277 T124 | T55 T277 T124 | T55 T277 T124 | T55 T277 T124 | T55 T277 T124 | T55 T277 T124 | T55 T56 T277 | T56 T277 T124 | T56 T277 T124 | T30 T277 T124 | T30 T277 T124 | T30 T277 T124 | T30 T277 T124 | T30 T277 T124 | T277 T124 T329 | T277 T124 T329 | T31 T277 T124 | T31 T277 T124 | T31 T277 T124 | T31 T277 T124 | T31 T277 T124 | T31 T277 T124 | T277 T124 T329 | T277 T124 T329 | T6 T277 T124 | T277 T124 T329 | T44 T80 T81 | T44 T80 T81 | T10 T44 T11 | T10 T11 T277 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T2 T5 T27 | T136 T63 T277 | T221 T44 T80 | T170 T277 T124 | T7 T143 T333 | T7 T143 T333 | T7 T143 T333 | T115 T334 T277 | T277 T124 T329 | T277 T124 T329 | T116 T277 T124 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329 | T277 T124 T329
93 end
94 end : gen_level
95 end : gen_tree
96
97
98 // The results can be found at the tree root
99 1/1 assign max_valid_o = vld_tree[0];
Tests: T5 T6 T7
100 1/1 assign max_idx_o = idx_tree[0];
Tests: T5 T6 T7
101 1/1 assign max_value_o = max_tree[0];
Tests: T5 T6 T7
102
103 ////////////////
104 // Assertions //
105 ////////////////
106
107 `ifdef INC_ASSERT
108 //VCS coverage off
109 // pragma coverage off
110
111 // Helper functions for assertions below.
112 function automatic logic [Width-1:0] max_value (input logic [NumSrc-1:0][Width-1:0] values_i,
113 input logic [NumSrc-1:0] valid_i);
114 unreachable logic [Width-1:0] value = '0;
115 unreachable for (int k = 0; k < NumSrc; k++) begin
116 unreachable if (valid_i[k] && values_i[k] > value) begin
117 unreachable value = values_i[k];
118 end
==> MISSING_ELSE
119 end
120 unreachable return value;
121 endfunction : max_value
122
123 function automatic logic [SrcWidth-1:0] max_idx (input logic [NumSrc-1:0][Width-1:0] values_i,
124 input logic [NumSrc-1:0] valid_i);
125 unreachable logic [Width-1:0] value = '0;
126 unreachable logic [SrcWidth-1:0] idx = '0;
127 unreachable for (int k = NumSrc-1; k >= 0; k--) begin
128 unreachable if (valid_i[k] && values_i[k] >= value) begin
129 unreachable value = values_i[k];
130 unreachable idx = k;
131 end
==> MISSING_ELSE
132 end
133 unreachable return idx;
134 endfunction : max_idx
135
136 logic [Width-1:0] max_value_exp;
137 logic [SrcWidth-1:0] max_idx_exp;
138 unreachable assign max_value_exp = max_value(values_i, valid_i);
139 unreachable assign max_idx_exp = max_idx(values_i, valid_i);