Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3626908	1			T96	127		T97	96		T98	1208
values[2]	722433	1			T96	57		T97	50		T98	332
values[3]	102160	1			T98	1		T465	1		T307	2
values[4]	55024	1			T466	6		T439	77		T679	22
values[5]	36896	1			T466	6		T439	106		T679	18
values[6]	27502	1			T466	5		T439	89		T679	17
values[7]	21984	1			T439	68		T679	26		T432	20
values[8]	19079	1			T439	82		T679	20		T432	37
values[9]	17171	1			T439	94		T679	12		T432	35
values[10]	15728	1			T439	80		T679	19		T432	37
values[11]	14396	1			T439	89		T679	16		T432	28
values[12]	13378	1			T439	86		T679	21		T432	28
values[13]	12592	1			T439	94		T679	26		T432	13
values[14]	11811	1			T439	94		T679	41		T432	12
values[15]	11509	1			T439	92		T679	43		T432	1
values[16]	10788	1			T439	44		T679	32		T432	1
values[17]	10320	1			T439	40		T679	14		T432	2
values[18]	9999	1			T439	42		T679	19		T432	1
values[19]	9525	1			T439	54		T679	41		T432	1
values[20]	9230	1			T439	70		T679	21		T432	3
values[21]	9184	1			T439	99		T679	21		T432	2
values[22]	8744	1			T439	99		T679	12		T432	3
values[23]	8790	1			T439	107		T679	15		T432	4
values[24]	8444	1			T439	106		T679	10		T432	4
values[25]	7851	1			T439	77		T679	8		T432	1
values[26]	7247	1			T439	48		T679	11		T432	1
values[27]	7015	1			T439	48		T679	14		T432	1
values[28]	6648	1			T439	51		T679	13		T432	1
values[29]	6308	1			T439	57		T679	24		T432	1
values[30]	5856	1			T439	32		T679	22		T432	2
values[31]	5313	1			T439	40		T679	16		T432	3
values[32]	5059	1			T439	23		T679	15		T432	1
values[33]	4822	1			T439	41		T679	8		T432	4
values[34]	4501	1			T439	33		T679	8		T432	1
values[35]	4258	1			T439	32		T679	7		T432	1
values[36]	4150	1			T439	43		T679	15		T432	2
values[37]	3866	1			T439	33		T679	13		T432	1
values[38]	3684	1			T439	28		T679	5		T432	2
values[39]	3566	1			T439	8		T679	4		T432	3
values[40]	3337	1			T439	11		T679	2		T432	5
values[41]	3275	1			T439	16		T679	3		T432	7
values[42]	3255	1			T439	11		T432	6		T788	25
values[43]	3285	1			T439	6		T432	5		T788	24
values[44]	3136	1			T439	5		T432	6		T788	30
values[45]	3011	1			T439	5		T432	1		T788	24
values[46]	2950	1			T439	13		T432	3		T788	17
values[47]	2938	1			T439	5		T432	3		T788	24
values[48]	2959	1			T439	5		T432	2		T788	20
values[49]	2822	1			T439	4		T432	3		T788	15
values[50]	2851	1			T439	8		T432	4		T788	15
values[51]	2779	1			T439	8		T432	2		T788	15
values[52]	2780	1			T439	7		T432	1		T788	17
values[53]	2719	1			T439	5		T432	1		T788	16
values[54]	2687	1			T439	2		T432	1		T788	17
values[55]	2602	1			T439	2		T432	1		T788	12
values[56]	2570	1			T439	1		T432	1		T788	14
values[57]	2610	1			T439	4		T432	1		T788	16
values[58]	2490	1			T432	1		T788	15		T637	2
values[59]	2406	1			T432	1		T788	13		T637	5
values[60]	2400	1			T432	2		T788	18		T637	1
values[61]	2609	1			T432	3		T788	17		T637	3
values[62]	3929	1			T432	15		T788	27		T637	4
values[63]	10681	1			T432	42		T788	104		T637	25
values[64]	234920	1			T432	95		T788	264		T637	74

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4647371	1			T96	90		T97	113		T98	1238
values[2]	798868	1			T96	20		T97	19		T98	300
values[3]	83641	1			T96	5		T98	11		T169	2
values[4]	14535	1			T308	1		T464	1		T439	4
values[5]	5393	1			T308	1		T546	3		T788	45
values[6]	3189	1			T546	1		T788	35		T637	1
values[7]	2505	1			T788	26		T637	3		T448	1
values[8]	2029	1			T788	33		T637	2		T639	2
values[9]	1916	1			T788	33		T637	4		T639	1
values[10]	1799	1			T788	24		T637	1		T639	4
values[11]	1560	1			T788	35		T637	2		T639	1
values[12]	1320	1			T788	11		T637	1		T639	1
values[13]	1272	1			T788	14		T637	1		T639	2
values[14]	1221	1			T788	15		T637	2		T639	3
values[15]	1127	1			T788	14		T637	1		T639	5
values[16]	1076	1			T788	11		T637	3		T639	5
values[17]	949	1			T788	3		T637	1		T639	1
values[18]	865	1			T637	2		T639	1		T450	2
values[19]	839	1			T637	2		T639	1		T450	3
values[20]	823	1			T637	1		T639	1		T450	5
values[21]	816	1			T637	2		T639	1		T450	1
values[22]	813	1			T637	4		T639	2		T450	2
values[23]	764	1			T637	1		T639	2		T450	6
values[24]	711	1			T637	1		T639	2		T450	1
values[25]	674	1			T637	1		T639	3		T450	1
values[26]	645	1			T637	1		T639	2		T450	1
values[27]	606	1			T637	2		T639	2		T450	1
values[28]	599	1			T637	1		T639	2		T450	2
values[29]	622	1			T637	1		T639	1		T450	1
values[30]	574	1			T637	3		T639	3		T450	1
values[31]	583	1			T637	3		T639	3		T609	2
values[32]	613	1			T637	8		T639	1		T609	2
values[33]	561	1			T637	8		T639	6		T609	1
values[34]	511	1			T637	7		T639	1		T609	1
values[35]	512	1			T637	4		T639	1		T609	1
values[36]	505	1			T637	2		T639	4		T609	2
values[37]	465	1			T637	1		T639	4		T609	6
values[38]	443	1			T637	1		T639	3		T609	7
values[39]	446	1			T637	2		T639	1		T609	2
values[40]	408	1			T637	1		T639	1		T609	2
values[41]	434	1			T637	1		T639	1		T609	2
values[42]	462	1			T637	1		T639	1		T609	1
values[43]	429	1			T637	1		T639	1		T609	3
values[44]	429	1			T637	1		T639	2		T609	2
values[45]	435	1			T637	1		T639	1		T609	1
values[46]	424	1			T637	2		T639	2		T609	1
values[47]	433	1			T637	3		T639	1		T609	1
values[48]	386	1			T637	1		T639	3		T609	2
values[49]	415	1			T637	3		T639	3		T609	1
values[50]	373	1			T637	2		T639	4		T609	1
values[51]	373	1			T637	1		T639	1		T609	1
values[52]	390	1			T637	2		T639	1		T609	2
values[53]	377	1			T637	2		T639	1		T609	3
values[54]	396	1			T637	2		T639	1		T609	1
values[55]	380	1			T637	2		T639	2		T609	1
values[56]	368	1			T637	1		T639	2		T609	1
values[57]	398	1			T637	1		T639	2		T609	2
values[58]	376	1			T637	2		T639	2		T609	3
values[59]	385	1			T637	3		T639	1		T609	1
values[60]	339	1			T637	1		T639	2		T609	1
values[61]	394	1			T637	1		T639	4		T609	2
values[62]	644	1			T637	4		T639	1		T609	12
values[63]	2578	1			T637	23		T639	3		T609	51
values[64]	27740	1			T637	67		T639	143		T609	109

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	518933	1			T96	1		T97	1		T98	10
values[2]	2617479	1			T96	88		T97	84		T98	1147
values[3]	1160335	1			T96	40		T97	26		T98	279
values[4]	139844	1			T98	2		T169	1		T307	12
values[5]	71388	1			T308	1		T466	43		T555	1
values[6]	46289	1			T466	20		T439	79		T679	20
values[7]	34510	1			T466	12		T439	89		T679	29
values[8]	27425	1			T466	20		T439	109		T679	29
values[9]	23195	1			T466	9		T439	77		T679	29
values[10]	20636	1			T466	8		T439	63		T679	31
values[11]	18392	1			T466	12		T439	81		T679	18
values[12]	16994	1			T466	4		T439	99		T679	20
values[13]	15720	1			T466	3		T439	85		T679	22
values[14]	14644	1			T439	107		T679	25		T432	16
values[15]	13739	1			T439	97		T679	14		T432	6
values[16]	13132	1			T439	79		T679	6		T432	5
values[17]	12754	1			T439	54		T679	7		T432	9
values[18]	12274	1			T439	73		T679	20		T432	11
values[19]	11421	1			T439	77		T679	13		T432	8
values[20]	10885	1			T439	57		T679	9		T432	3
values[21]	10508	1			T439	51		T679	10		T432	1
values[22]	9834	1			T439	48		T679	14		T432	7
values[23]	9270	1			T439	69		T679	8		T432	1
values[24]	8899	1			T439	61		T679	11		T432	1
values[25]	8579	1			T439	103		T679	7		T432	5
values[26]	8263	1			T439	99		T679	13		T432	1
values[27]	7961	1			T439	81		T679	17		T432	2
values[28]	7521	1			T439	68		T679	14		T432	3
values[29]	6897	1			T439	64		T679	16		T432	5
values[30]	6635	1			T439	52		T679	28		T432	1
values[31]	6305	1			T439	47		T679	27		T432	1
values[32]	5763	1			T439	63		T679	17		T432	3
values[33]	5508	1			T439	64		T679	23		T432	1
values[34]	4999	1			T439	44		T679	13		T432	1
values[35]	4737	1			T439	27		T679	7		T432	2
values[36]	4436	1			T439	7		T679	4		T432	3
values[37]	4095	1			T439	6		T679	6		T432	8
values[38]	3821	1			T439	9		T679	5		T432	4
values[39]	3687	1			T439	7		T679	14		T432	1
values[40]	3524	1			T439	13		T679	10		T432	2
values[41]	3494	1			T439	8		T679	3		T432	3
values[42]	3392	1			T439	7		T679	4		T432	1
values[43]	3366	1			T439	10		T679	4		T432	1
values[44]	3319	1			T439	5		T679	1		T432	1
values[45]	3296	1			T439	9		T679	1		T432	2
values[46]	3229	1			T439	6		T679	1		T432	4
values[47]	3305	1			T439	4		T679	1		T432	1
values[48]	3160	1			T439	2		T679	2		T432	3
values[49]	3148	1			T439	10		T679	3		T432	1
values[50]	3069	1			T439	2		T679	1		T432	1
values[51]	2955	1			T439	3		T679	1		T432	2
values[52]	2922	1			T439	1		T679	2		T432	6
values[53]	2918	1			T439	3		T432	1		T788	27
values[54]	2857	1			T439	3		T432	1		T788	32
values[55]	2825	1			T439	10		T432	3		T788	22
values[56]	2745	1			T439	7		T432	3		T788	10
values[57]	2725	1			T439	5		T432	3		T788	17
values[58]	2696	1			T439	4		T432	1		T788	14
values[59]	2734	1			T439	1		T432	2		T788	11
values[60]	2672	1			T439	3		T432	2		T788	7
values[61]	2663	1			T439	1		T432	1		T788	14
values[62]	3507	1			T432	5		T788	23		T637	2
values[63]	9113	1			T432	43		T788	72		T637	25
values[64]	228311	1			T432	88		T788	191		T637	83