Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1843233	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

35134196

1

T1

350

T2

6701

T3

5234

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	25199222	1			T1	175		T2	2493		T3	1823
values[0x0]	10310412	1			T1	175		T2	4208		T3	3411
values[0x1]	1467795	1			T1	3		T2	263		T3	187

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	552771	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

36424658

1

T1

353

T2

6964

T3

5421

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17417996	1			T1	177		T2	3482		T3	2711
valid_sources[0x01]	17417423	1			T1	176		T2	3482		T3	2710
valid_sources[0x02]	38356	1			T883	1		T409	11		T410	15
valid_sources[0x03]	34192	1			T102	39		T883	11		T409	37
valid_sources[0x04]	34110	1			T883	10		T409	17		T410	9
valid_sources[0x05]	34641	1			T101	2		T883	3		T409	19
valid_sources[0x06]	33977	1			T101	4		T240	39		T71	4
valid_sources[0x07]	33966	1			T101	1		T883	14		T409	19
valid_sources[0x08]	34444	1			T101	2		T409	14		T410	17
valid_sources[0x09]	33920	1			T883	11		T409	26		T410	15
valid_sources[0x0a]	35087	1			T883	2		T409	20		T410	10
valid_sources[0x0b]	34333	1			T101	2		T883	3		T409	20
valid_sources[0x0c]	34365	1			T883	10		T409	27		T410	11
valid_sources[0x0d]	34471	1			T883	11		T409	18		T410	15
valid_sources[0x0e]	34255	1			T101	3		T409	15		T410	14
valid_sources[0x0f]	34729	1			T101	1		T883	12		T409	22
valid_sources[0x10]	35181	1			T71	7		T883	3		T409	21
valid_sources[0x11]	33930	1			T883	5		T409	35		T410	13
valid_sources[0x12]	34314	1			T883	6		T409	23		T410	12
valid_sources[0x13]	33268	1			T101	1		T409	16		T410	15
valid_sources[0x14]	34333	1			T101	2		T883	9		T409	20
valid_sources[0x15]	34010	1			T101	1		T883	2		T409	15
valid_sources[0x16]	33724	1			T883	1		T409	21		T410	22
valid_sources[0x17]	33979	1			T883	2		T409	26		T410	13
valid_sources[0x18]	34218	1			T883	1		T409	41		T410	16
valid_sources[0x19]	34095	1			T883	6		T409	19		T410	12
valid_sources[0x1a]	33702	1			T883	1		T409	29		T410	9
valid_sources[0x1b]	34356	1			T883	3		T409	20		T410	20
valid_sources[0x1c]	34370	1			T101	1		T71	11		T409	26
valid_sources[0x1d]	34821	1			T883	4		T409	33		T410	10
valid_sources[0x1e]	34996	1			T883	12		T409	21		T410	20
valid_sources[0x1f]	34678	1			T101	1		T883	1		T409	18
valid_sources[0x20]	33786	1			T101	1		T409	24		T410	25

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24608176

1

T1

175

T2

2493

T3

1823

values[0x0]

all_enables

biggest_size

10257634

1

T1

175

T2

4208

T3

3411

values[0x1]

all_enables

biggest_size

268386

1

T38

18

T101

23

T102

25

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2687909	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

425382

1

T96

30

T97

19

T98

210

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1054982	1			T96	54		T97	45		T98	502
values[0x0]	1003381	1			T96	70		T97	47		T98	536
values[0x1]	1054928	1			T96	60		T97	54		T98	503

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2081673	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1031618

1

T96

66

T97

41

T98

516

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	48141	1			T96	3		T97	3		T98	31
valid_sources[0x01]	48708	1			T96	1		T98	31		T103	18
valid_sources[0x02]	48443	1			T96	4		T98	4		T103	16
valid_sources[0x03]	49481	1			T97	4		T98	22		T103	15
valid_sources[0x04]	47625	1			T96	4		T98	44		T103	26
valid_sources[0x05]	48959	1			T96	5		T97	18		T98	23
valid_sources[0x06]	47828	1			T98	48		T103	24		T169	38
valid_sources[0x07]	48351	1			T96	4		T97	9		T98	21
valid_sources[0x08]	47993	1			T98	14		T103	34		T169	39
valid_sources[0x09]	49305	1			T97	1		T98	13		T103	42
valid_sources[0x0a]	47704	1			T96	3		T97	5		T169	34
valid_sources[0x0b]	48412	1			T96	4		T97	1		T98	48
valid_sources[0x0c]	49490	1			T96	5		T98	11		T169	22
valid_sources[0x0d]	47620	1			T96	3		T97	2		T98	31
valid_sources[0x0e]	47857	1			T98	16		T169	31		T276	2
valid_sources[0x0f]	49584	1			T96	2		T98	32		T103	23
valid_sources[0x10]	49302	1			T96	3		T98	14		T103	25
valid_sources[0x11]	48696	1			T96	5		T98	13		T103	18
valid_sources[0x12]	48674	1			T96	5		T97	25		T98	62
valid_sources[0x13]	49191	1			T96	4		T98	4		T103	8
valid_sources[0x14]	48552	1			T98	45		T103	68		T169	28
valid_sources[0x15]	49001	1			T96	2		T98	22		T169	36
valid_sources[0x16]	47793	1			T96	1		T98	37		T169	33
valid_sources[0x17]	50283	1			T96	7		T98	53		T103	15
valid_sources[0x18]	48862	1			T97	2		T98	33		T169	40
valid_sources[0x19]	48504	1			T96	6		T98	18		T103	7
valid_sources[0x1a]	48780	1			T96	3		T98	22		T103	13
valid_sources[0x1b]	47981	1			T96	3		T98	23		T103	6
valid_sources[0x1c]	48864	1			T96	1		T98	21		T103	32
valid_sources[0x1d]	48202	1			T96	1		T98	60		T169	47
valid_sources[0x1e]	49723	1			T96	3		T98	14		T169	38
valid_sources[0x1f]	48099	1			T97	8		T98	6		T169	35
valid_sources[0x20]	49208	1			T96	1		T97	3		T98	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44989

1

T97

2

T98

17

T103

12

values[0x0]

all_enables

biggest_size

335387

1

T96

27

T97

17

T98

171

values[0x1]

all_enables

biggest_size

45006

1

T96

3

T98

22

T103

9

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2882507	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

469454

1

T96

14

T97

22

T98

240

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1148215	1			T96	34		T97	40		T98	525
values[0x0]	1055481	1			T96	37		T97	49		T98	509
values[0x1]	1148265	1			T96	44		T97	43		T98	515

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2210306	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1141655

1

T96

42

T97

44

T98

521

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51428	1			T97	2		T98	7		T169	30
valid_sources[0x01]	52291	1			T96	8		T97	3		T98	35
valid_sources[0x02]	52834	1			T96	3		T97	1		T98	11
valid_sources[0x03]	52250	1			T96	5		T97	2		T98	36
valid_sources[0x04]	51373	1			T96	4		T97	3		T98	17
valid_sources[0x05]	52851	1			T97	1		T98	26		T103	9
valid_sources[0x06]	53211	1			T98	34		T103	28		T169	33
valid_sources[0x07]	52368	1			T97	1		T98	31		T103	14
valid_sources[0x08]	51913	1			T96	11		T97	2		T98	33
valid_sources[0x09]	51952	1			T97	7		T98	18		T103	32
valid_sources[0x0a]	51908	1			T97	2		T98	54		T169	37
valid_sources[0x0b]	52241	1			T96	2		T97	2		T98	8
valid_sources[0x0c]	51784	1			T96	2		T97	5		T98	12
valid_sources[0x0d]	52689	1			T96	6		T97	6		T98	18
valid_sources[0x0e]	52161	1			T98	22		T169	36		T276	1
valid_sources[0x0f]	51922	1			T96	6		T97	3		T98	10
valid_sources[0x10]	53295	1			T96	2		T98	15		T103	29
valid_sources[0x11]	52330	1			T97	2		T98	37		T103	28
valid_sources[0x12]	51893	1			T97	2		T98	17		T103	6
valid_sources[0x13]	52559	1			T98	11		T103	8		T169	29
valid_sources[0x14]	52039	1			T96	1		T97	1		T98	11
valid_sources[0x15]	53239	1			T96	7		T97	1		T98	21
valid_sources[0x16]	52040	1			T96	1		T97	3		T98	16
valid_sources[0x17]	52996	1			T97	2		T98	43		T103	10
valid_sources[0x18]	53724	1			T97	1		T98	16		T169	32
valid_sources[0x19]	51762	1			T97	4		T98	2		T103	14
valid_sources[0x1a]	52870	1			T97	2		T98	54		T103	7
valid_sources[0x1b]	53226	1			T98	28		T103	19		T169	22
valid_sources[0x1c]	53600	1			T96	20		T98	11		T103	32
valid_sources[0x1d]	51173	1			T97	3		T98	12		T169	36
valid_sources[0x1e]	52832	1			T97	2		T98	27		T169	37
valid_sources[0x1f]	50535	1			T97	2		T98	8		T169	33
valid_sources[0x20]	52718	1			T96	8		T97	5		T98	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49492

1

T96

1

T98

23

T103

4

values[0x0]

all_enables

biggest_size

370689

1

T96

13

T97

21

T98

189

values[0x1]

all_enables

biggest_size

49273

1

T97

1

T98

28

T103

16

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2715024	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

428504

1

T96

12

T97

16

T98

212

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1064657	1			T96	44		T97	39		T98	479
values[0x0]	1011465	1			T96	45		T97	37		T98	491
values[0x1]	1067406	1			T96	40		T97	35		T98	468

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2100089	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1043439

1

T96

31

T97

37

T98

465

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	49548	1			T96	12		T98	23		T169	55
valid_sources[0x01]	49532	1			T97	5		T98	41		T103	43
valid_sources[0x02]	48428	1			T97	8		T98	24		T103	20
valid_sources[0x03]	49805	1			T96	2		T97	4		T98	5
valid_sources[0x04]	49133	1			T98	1		T103	28		T169	6
valid_sources[0x05]	48887	1			T96	3		T97	1		T98	9
valid_sources[0x06]	49233	1			T98	35		T103	22		T169	49
valid_sources[0x07]	48776	1			T98	15		T103	12		T169	61
valid_sources[0x08]	48019	1			T97	3		T98	25		T103	22
valid_sources[0x09]	49439	1			T98	6		T103	28		T169	40
valid_sources[0x0a]	49249	1			T98	20		T169	45		T465	91
valid_sources[0x0b]	48181	1			T98	27		T169	47		T276	1
valid_sources[0x0c]	48669	1			T97	1		T98	22		T169	14
valid_sources[0x0d]	49349	1			T98	6		T103	9		T169	15
valid_sources[0x0e]	48179	1			T98	36		T169	26		T276	1
valid_sources[0x0f]	49940	1			T96	8		T97	1		T98	28
valid_sources[0x10]	49380	1			T97	2		T98	6		T103	27
valid_sources[0x11]	49370	1			T97	5		T98	33		T103	18
valid_sources[0x12]	48916	1			T98	23		T103	7		T169	48
valid_sources[0x13]	48094	1			T98	56		T103	6		T169	34
valid_sources[0x14]	49219	1			T97	2		T98	39		T103	62
valid_sources[0x15]	48902	1			T98	1		T169	31		T276	1
valid_sources[0x16]	48443	1			T98	38		T169	23		T465	46
valid_sources[0x17]	50799	1			T96	1		T98	3		T103	11
valid_sources[0x18]	49332	1			T96	2		T97	5		T98	20
valid_sources[0x19]	49497	1			T96	8		T97	2		T98	27
valid_sources[0x1a]	48675	1			T98	45		T103	5		T169	17
valid_sources[0x1b]	48757	1			T96	2		T98	15		T103	13
valid_sources[0x1c]	49608	1			T96	2		T98	21		T103	27
valid_sources[0x1d]	49766	1			T96	4		T98	33		T169	22
valid_sources[0x1e]	49190	1			T98	11		T169	20		T465	28
valid_sources[0x1f]	47666	1			T96	2		T97	6		T98	7
valid_sources[0x20]	49872	1			T97	4		T98	29		T103	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45419

1

T96

1

T97

1

T98

21

values[0x0]

all_enables

biggest_size

337893

1

T96

10

T97

13

T98

165

values[0x1]

all_enables

biggest_size

45192

1

T96

1

T97

2

T98

26