Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	495815317	63540112	0	0
DataKnown_AKnownEnable	495815317	495709674	0	0
DepthKnown_A	495815317	495709674	0	0
RvalidKnown_A	495815317	495709674	0	0
WreadyKnown_A	495815317	495709674	0	0
gen_passthru_fifo.paramCheckPass	1016	1016	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495815317	63540112	0	0
T1	42250	3485	0	0
T2	88852	9647	0	0
T3	72976	8662	0	0
T4	73392	10133	0	0
T5	85968	10985	0	0
T6	110425	14666	0	0
T7	107344	12370	0	0
T9	80162	9550	0	0
T25	101485	13292	0	0
T107	62251	5912	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	495815317	495709674	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495815317	495709674	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495815317	495709674	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495815317	495709674	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1016	1016	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T25	1	1	0	0
T107	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         0/1     ==>      assign wready_o = rready_i;
49         0/1     ==>      assign full_o = rready_i;
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	495815317	45742155	0	0
DataKnown_AKnownEnable	495815317	495709674	0	0
DepthKnown_A	495815317	495709674	0	0
RvalidKnown_A	495815317	495709674	0	0
WreadyKnown_A	495815317	495709674	0	0
gen_passthru_fifo.paramCheckPass	1016	1016	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495815317	45742155	0	0
T1	42250	1880	0	0
T2	88852	6955	0	0
T3	72976	6123	0	0
T4	73392	6469	0	0
T5	85968	8019	0	0
T6	110425	10424	0	0
T7	107344	9907	0	0
T9	80162	6807	0	0
T25	101485	9559	0	0
T107	62251	4237	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	495815317	495709674	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495815317	495709674	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495815317	495709674	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495815317	495709674	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1016	1016	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T25	1	1	0	0
T107	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	495815317	42763526	0	0
DataKnown_AKnownEnable	495815317	495709674	0	0
DepthKnown_A	495815317	495709674	0	0
RvalidKnown_A	495815317	495709674	0	0
WreadyKnown_A	495815317	495709674	0	0
gen_passthru_fifo.paramCheckPass	1016	1016	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495815317	42763526	0	0
T1	42250	461	0	0
T2	88852	7422	0	0
T3	72976	5596	0	0
T4	73392	4110	0	0
T5	85968	5755	0	0
T6	110425	7027	0	0
T7	107344	6374	0	0
T9	80162	4894	0	0
T25	101485	6798	0	0
T107	62251	3459	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	495815317	495709674	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495815317	495709674	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495815317	495709674	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495815317	495709674	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1016	1016	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T25	1	1	0	0
T107	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T38 T101 T102 
49         1/1              assign full_o = rready_i;
           Tests:       T38 T101 T102 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	495815317	34868728	0	0
DataKnown_AKnownEnable	495815317	495709674	0	0
DepthKnown_A	495815317	495709674	0	0
RvalidKnown_A	495815317	495709674	0	0
WreadyKnown_A	495815317	495709674	0	0
gen_passthru_fifo.paramCheckPass	1016	1016	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495815317	34868728	0	0
T1	42250	353	0	0
T2	88852	6964	0	0
T3	72976	5421	0	0
T4	73392	3937	0	0
T5	85968	5566	0	0
T6	110425	6777	0	0
T7	107344	6236	0	0
T9	80162	4725	0	0
T25	101485	6555	0	0
T107	62251	3346	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	495815317	495709674	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495815317	495709674	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495815317	495709674	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	495815317	495709674	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1016	1016	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T25	1	1	0	0
T107	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	576051747	91415	0	0
DataKnown_AKnownEnable	576051747	575930338	0	0
DepthKnown_A	576051747	575930338	0	0
RvalidKnown_A	576051747	575930338	0	0
WreadyKnown_A	576051747	575930338	0	0
gen_passthru_fifo.paramCheckPass	2925	2925	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	91415	0	0
T1	42250	8	0	0
T2	88852	208	0	0
T3	72976	24	0	0
T4	73392	24	0	0
T5	85968	27	0	0
T6	110425	25	0	0
T7	107344	13	0	0
T9	80162	18	0	0
T25	101485	29	0	0
T107	62251	13	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T25	1	1	0	0
T107	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	576051747	92290	0	0
DataKnown_AKnownEnable	576051747	575930338	0	0
DepthKnown_A	576051747	575930338	0	0
RvalidKnown_A	576051747	575930338	0	0
WreadyKnown_A	576051747	575930338	0	0
gen_passthru_fifo.paramCheckPass	2925	2925	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	92290	0	0
T1	42250	8	0	0
T2	88852	208	0	0
T3	72976	24	0	0
T4	73392	24	0	0
T5	85968	27	0	0
T6	110425	25	0	0
T7	107344	13	0	0
T9	80162	18	0	0
T25	101485	29	0	0
T107	62251	13	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T25	1	1	0	0
T107	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	576051747	50507	0	0
DataKnown_AKnownEnable	576051747	575930338	0	0
DepthKnown_A	576051747	575930338	0	0
RvalidKnown_A	576051747	575930338	0	0
WreadyKnown_A	576051747	575930338	0	0
gen_passthru_fifo.paramCheckPass	2925	2925	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	50507	0	0
T1	42250	8	0	0
T2	88852	205	0	0
T3	72976	23	0	0
T4	73392	21	0	0
T5	85968	24	0	0
T6	110425	22	0	0
T7	107344	12	0	0
T9	80162	15	0	0
T25	101485	26	0	0
T107	62251	12	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T25	1	1	0	0
T107	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	576051747	50507	0	0
DataKnown_AKnownEnable	576051747	575930338	0	0
DepthKnown_A	576051747	575930338	0	0
RvalidKnown_A	576051747	575930338	0	0
WreadyKnown_A	576051747	575930338	0	0
gen_passthru_fifo.paramCheckPass	2925	2925	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	50507	0	0
T1	42250	8	0	0
T2	88852	205	0	0
T3	72976	23	0	0
T4	73392	21	0	0
T5	85968	24	0	0
T6	110425	22	0	0
T7	107344	12	0	0
T9	80162	15	0	0
T25	101485	26	0	0
T107	62251	12	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T25	1	1	0	0
T107	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T2 T3 T4 
49         1/1              assign full_o = rready_i;
           Tests:       T2 T3 T4 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	576051747	40908	0	0
DataKnown_AKnownEnable	576051747	575930338	0	0
DepthKnown_A	576051747	575930338	0	0
RvalidKnown_A	576051747	575930338	0	0
WreadyKnown_A	576051747	575930338	0	0
gen_passthru_fifo.paramCheckPass	2925	2925	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	40908	0	0
T2	88852	3	0	0
T3	72976	1	0	0
T4	73392	3	0	0
T5	85968	3	0	0
T6	110425	3	0	0
T7	107344	1	0	0
T9	80162	3	0	0
T25	101485	3	0	0
T107	62251	1	0	0
T124	108667	3	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T25	1	1	0	0
T107	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T2 T3 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T2 T3 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	576051747	41783	0	0
DataKnown_AKnownEnable	576051747	575930338	0	0
DepthKnown_A	576051747	575930338	0	0
RvalidKnown_A	576051747	575930338	0	0
WreadyKnown_A	576051747	575930338	0	0
gen_passthru_fifo.paramCheckPass	2925	2925	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	41783	0	0
T2	88852	3	0	0
T3	72976	1	0	0
T4	73392	3	0	0
T5	85968	3	0	0
T6	110425	3	0	0
T7	107344	1	0	0
T9	80162	3	0	0
T25	101485	3	0	0
T107	62251	1	0	0
T124	108667	3	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	576051747	575930338	0	0
T1	42250	42192	0	0
T2	88852	88794	0	0
T3	72976	72914	0	0
T4	73392	73341	0	0
T5	85968	85910	0	0
T6	110425	110363	0	0
T7	107344	107282	0	0
T9	80162	80100	0	0
T25	101485	101434	0	0
T107	62251	62193	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2925	2925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T25	1	1	0	0
T107	1	1	0	0