Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T45,T39,T29	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T134,T133,T68	Yes	T134,T133,T68	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T134,T133,T68	Yes	T134,T133,T68	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T99,*T38,*T100	Yes	T99,T38,T100	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T38,T101,T102	Yes	T38,T101,T102	INPUT
tl_i.a_valid	Yes	Yes	T134,T133,T68	Yes	T134,T133,T68	INPUT
tl_o.a_ready	Yes	Yes	T134,T133,T68	Yes	T134,T133,T68	OUTPUT
tl_o.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T134,T133,T68	Yes	T134,T133,T68	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T134,T133,T68	Yes	T134,T133,T68	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T134,T133,T68	Yes	T134,T133,T68	OUTPUT
tl_o.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T310,*T311,*T452	Yes	T310,T311,T452	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T134,*T133,*T68	Yes	T134,T133,T68	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T134,T133,T68	Yes	T134,T133,T68	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T80,T104,T199	Yes	T80,T104,T199	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T80,T104,T199	Yes	T80,T104,T199	OUTPUT
cio_rx_i	Yes	Yes	T2,T45,T39	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T134,T133,T68	Yes	T134,T133,T68	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T134,T133,T68	Yes	T134,T133,T68	OUTPUT
intr_tx_empty_o	Yes	Yes	T134,T133,T68	Yes	T134,T133,T68	OUTPUT
intr_rx_watermark_o	Yes	Yes	T134,T133,T68	Yes	T134,T133,T68	OUTPUT
intr_tx_done_o	Yes	Yes	T134,T133,T68	Yes	T134,T133,T68	OUTPUT
intr_rx_overflow_o	Yes	Yes	T134,T133,T68	Yes	T134,T133,T68	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T252,T259,T260	Yes	T252,T259,T260	OUTPUT
intr_rx_break_err_o	Yes	Yes	T252,T259,T260	Yes	T252,T259,T260	OUTPUT
intr_rx_timeout_o	Yes	Yes	T252,T259,T260	Yes	T252,T259,T260	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T252,T259,T260	Yes	T252,T259,T260	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T45,T39,T29	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T133,T279,T252	Yes	T133,T279,T252	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T133,T279,T252	Yes	T133,T279,T252	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T99,*T38,*T100	Yes	T99,T38,T100	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T38,T101,T102	Yes	T38,T101,T102	INPUT
tl_i.a_valid	Yes	Yes	T133,T80,T279	Yes	T133,T80,T279	INPUT
tl_o.a_ready	Yes	Yes	T133,T80,T199	Yes	T133,T80,T199	OUTPUT
tl_o.d_error	Yes	Yes	T98,T103,T169	Yes	T98,T103,T169	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T133,T252,T256	Yes	T133,T252,T256	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T133,T199,T252	Yes	T133,T80,T199	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T133,T199,T252	Yes	T133,T80,T199	OUTPUT
tl_o.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T310,*T311,*T452	Yes	T310,T311,T452	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T133,*T252,*T256	Yes	T133,T252,T256	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T133,T80,T199	Yes	T133,T80,T199	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T80,T104,T199	Yes	T80,T104,T199	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T104,T105,T106	Yes	T104,T105,T313	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T104,T105,T313	Yes	T104,T105,T106	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T80,T104,T199	Yes	T80,T104,T199	OUTPUT
cio_rx_i	Yes	Yes	T2,T45,T39	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T133,T58,T55	Yes	T133,T58,T55	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T133,T252,T256	Yes	T133,T252,T256	OUTPUT
intr_tx_empty_o	Yes	Yes	T133,T252,T257	Yes	T133,T252,T257	OUTPUT
intr_rx_watermark_o	Yes	Yes	T133,T252,T257	Yes	T133,T252,T257	OUTPUT
intr_tx_done_o	Yes	Yes	T133,T252,T258	Yes	T133,T252,T258	OUTPUT
intr_rx_overflow_o	Yes	Yes	T133,T252,T258	Yes	T133,T252,T258	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T252,T259,T260	Yes	T252,T259,T260	OUTPUT
intr_rx_break_err_o	Yes	Yes	T252,T259,T260	Yes	T252,T259,T260	OUTPUT
intr_rx_timeout_o	Yes	Yes	T252,T259,T260	Yes	T252,T259,T260	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T252,T259,T260	Yes	T252,T259,T260	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T45,T39,T29	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T134,T135,T252	Yes	T134,T135,T252	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T134,T135,T252	Yes	T134,T135,T252	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T99,*T38,*T100	Yes	T99,T38,T100	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T38,T101,T102	Yes	T38,T101,T102	INPUT
tl_i.a_valid	Yes	Yes	T134,T80,T135	Yes	T134,T80,T135	INPUT
tl_o.a_ready	Yes	Yes	T134,T80,T135	Yes	T134,T80,T135	OUTPUT
tl_o.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T134,T135,T252	Yes	T134,T135,T252	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T134,T135,T199	Yes	T134,T80,T135	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T134,T135,T199	Yes	T134,T80,T135	OUTPUT
tl_o.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T98,*T103,*T169	Yes	T96,T97,T98	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T134,*T135,*T252	Yes	T134,T135,T252	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T134,T80,T135	Yes	T134,T80,T135	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T80,T104,T199	Yes	T80,T104,T199	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T80,T104,T199	Yes	T80,T104,T199	OUTPUT
cio_rx_i	Yes	Yes	T134,T135,T136	Yes	T2,T9,T134	INPUT
cio_tx_o	Yes	Yes	T134,T135,T136	Yes	T134,T135,T136	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T134,T135,T252	Yes	T134,T135,T252	OUTPUT
intr_tx_empty_o	Yes	Yes	T134,T135,T252	Yes	T134,T135,T252	OUTPUT
intr_rx_watermark_o	Yes	Yes	T134,T135,T252	Yes	T134,T135,T252	OUTPUT
intr_tx_done_o	Yes	Yes	T134,T135,T252	Yes	T134,T135,T252	OUTPUT
intr_rx_overflow_o	Yes	Yes	T134,T135,T252	Yes	T134,T135,T252	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T252,T259,T260	Yes	T252,T259,T260	OUTPUT
intr_rx_break_err_o	Yes	Yes	T252,T259,T260	Yes	T252,T259,T260	OUTPUT
intr_rx_timeout_o	Yes	Yes	T252,T259,T260	Yes	T252,T259,T260	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T252,T259,T260	Yes	T252,T259,T260	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T45,T39,T29	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T68,T252,T37	Yes	T68,T252,T37	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T68,T252,T37	Yes	T68,T252,T37	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T99,*T38,*T100	Yes	T99,T38,T100	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T38,T101,T102	Yes	T38,T101,T102	INPUT
tl_i.a_valid	Yes	Yes	T68,T80,T199	Yes	T68,T80,T199	INPUT
tl_o.a_ready	Yes	Yes	T68,T80,T199	Yes	T68,T80,T199	OUTPUT
tl_o.d_error	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T68,T252,T37	Yes	T68,T252,T37	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T68,T199,T252	Yes	T68,T80,T199	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T68,T199,T252	Yes	T68,T80,T199	OUTPUT
tl_o.d_sink	Yes	Yes	T97,T98,T103	Yes	T97,T98,T103	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T96,*T98,*T103	Yes	T96,T97,T98	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T68,*T252,*T37	Yes	T68,T252,T37	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T68,T80,T199	Yes	T68,T80,T199	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T80,T104,T199	Yes	T80,T104,T199	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T80,T104,T199	Yes	T80,T104,T199	OUTPUT
cio_rx_i	Yes	Yes	T68,T69,T137	Yes	T68,T69,T137	INPUT
cio_tx_o	Yes	Yes	T68,T69,T137	Yes	T68,T69,T137	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T68,T252,T69	Yes	T68,T252,T69	OUTPUT
intr_tx_empty_o	Yes	Yes	T68,T252,T69	Yes	T68,T252,T69	OUTPUT
intr_rx_watermark_o	Yes	Yes	T68,T252,T69	Yes	T68,T252,T69	OUTPUT
intr_tx_done_o	Yes	Yes	T68,T252,T69	Yes	T68,T252,T69	OUTPUT
intr_rx_overflow_o	Yes	Yes	T68,T252,T69	Yes	T68,T252,T69	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T252,T259,T260	Yes	T252,T259,T260	OUTPUT
intr_rx_break_err_o	Yes	Yes	T252,T259,T260	Yes	T252,T259,T260	OUTPUT
intr_rx_timeout_o	Yes	Yes	T252,T259,T260	Yes	T252,T259,T260	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T252,T259,T260	Yes	T252,T259,T260	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T45,T39,T29	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T26,T70,T252	Yes	T26,T70,T252	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T26,T70,T252	Yes	T26,T70,T252	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T99,*T38,*T100	Yes	T99,T38,T100	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T38,T101,T102	Yes	T38,T101,T102	INPUT
tl_i.a_valid	Yes	Yes	T26,T70,T80	Yes	T26,T70,T80	INPUT
tl_o.a_ready	Yes	Yes	T26,T70,T80	Yes	T26,T70,T80	OUTPUT
tl_o.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T26,T70,T252	Yes	T26,T70,T252	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T26,T70,T199	Yes	T26,T70,T80	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T26,T70,T199	Yes	T26,T70,T80	OUTPUT
tl_o.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T98,*T103,*T169	Yes	T96,T97,T98	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T26,*T70,*T252	Yes	T26,T70,T252	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T26,T70,T80	Yes	T26,T70,T80	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T80,T104,T199	Yes	T80,T104,T199	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T104,T105,T106	Yes	T104,T105,T106	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T80,T104,T199	Yes	T80,T104,T199	OUTPUT
cio_rx_i	Yes	Yes	T26,T70,T138	Yes	T26,T70,T138	INPUT
cio_tx_o	Yes	Yes	T26,T70,T138	Yes	T26,T70,T138	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T26,T70,T252	Yes	T26,T70,T252	OUTPUT
intr_tx_empty_o	Yes	Yes	T26,T70,T252	Yes	T26,T70,T252	OUTPUT
intr_rx_watermark_o	Yes	Yes	T26,T70,T252	Yes	T26,T70,T252	OUTPUT
intr_tx_done_o	Yes	Yes	T26,T70,T252	Yes	T26,T70,T252	OUTPUT
intr_rx_overflow_o	Yes	Yes	T26,T70,T252	Yes	T26,T70,T252	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T252,T259,T260	Yes	T252,T259,T260	OUTPUT
intr_rx_break_err_o	Yes	Yes	T252,T259,T260	Yes	T252,T259,T260	OUTPUT
intr_rx_timeout_o	Yes	Yes	T252,T259,T260	Yes	T252,T259,T260	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T252,T259,T260	Yes	T252,T259,T260	OUTPUT

*Tests covering at least one bit in the range