Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T45,T39,T29	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T45,T39,T29	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T45,T39,T29	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T45,T39,T29	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T45,T39,T29	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T307,T308,T309	Yes	T96,T97,T98	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T97,T276,T307	Yes	T97,T276,T307	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T246,T220,T247	Yes	T246,T220,T247	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T87,T246,T220	Yes	T87,T246,T220	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T38,T101,T102	Yes	T38,T101,T102	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T101,T240,T276	Yes	T101,T240,T276	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T101,T240,T96	Yes	T101,T240,T96	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T45,T87,T248	Yes	T45,T87,T248	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T45,T39,T46	Yes	T1,T3,T5	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T34,T99,T88	Yes	T34,T99,T88	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T45,T39,T46	Yes	T1,T3,T5	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T45,T39,T46	Yes	T1,T3,T5	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T34,T99,T88	Yes	T34,T99,T88	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T45,T39,T46	Yes	T1,T3,T5	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T34,T99,T88	Yes	T34,T99,T88	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T45,T39,T29	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T34,T99,T88	Yes	T34,T99,T88	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T34,T88,T38	Yes	T34,T88,T38	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T34,T99,T88	Yes	T34,T99,T88	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T34,*T99,*T88	Yes	T34,T99,T88	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T34,T99,T88	Yes	T34,T99,T88	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T45,T39,T29	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T307,T308,T309	Yes	T96,T97,T98	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T98,T103,T169	Yes	T96,T98,T103	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T98,*T103,*T169	Yes	T98,T103,T169	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T45,T39,T29	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T99,T310,T311	Yes	T99,T310,T311	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T99,T310,T311	Yes	T99,T310,T311	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T99,T310,T311	Yes	T99,T310,T311	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T99,T310,T311	Yes	T99,T310,T311	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T99,T310,T311	Yes	T99,T310,T311	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T99,*T310,*T311	Yes	T99,T310,T311	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T99,T310,T311	Yes	T99,T310,T311	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T3,T5	Yes	T45,T39,T46	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T99,T310,T311	Yes	T99,T310,T311	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T99,T310,T311	Yes	T99,T310,T311	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T3,T5	Yes	T45,T39,T46	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T99,*T310,*T311	Yes	T99,T310,T311	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T5	Yes	T45,T39,T46	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T99,T310,T311	Yes	T99,T310,T311	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T214,T32	Yes	T1,T214,T32	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T214,T421,T37	Yes	T214,T421,T37	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T45,T39,T29	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T80,T422,T325	Yes	T80,T422,T325	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T80,T422,T325	Yes	T80,T422,T325	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T80,T422,T325	Yes	T80,T422,T325	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T80,T422,T325	Yes	T80,T422,T325	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T80,T422,T325	Yes	T80,T422,T325	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T97,T103,T169	Yes	T97,T103,T169	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T422,T325,T423	Yes	T422,T325,T423	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T96,T97,T98	Yes	T80,T81,T82	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T422,T325,T423	Yes	T80,T422,T325	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T97,T98,T103	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T98,T103,T169	Yes	T96,T97,T98	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T97,T98,T103	Yes	T96,T97,T98	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T325,*T424,*T425	Yes	T422,T325,T423	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T80,T422,T325	Yes	T80,T422,T325	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T99,*T38,*T100	Yes	T99,T38,T100	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T38,T101,T102	Yes	T38,T101,T102	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T86,T87,T336	Yes	T86,T87,T336	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T99,*T38,*T100	Yes	T99,T38,T100	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T10,T236,T238	Yes	T10,T236,T238	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T97,*T98,*T103	Yes	T96,T97,T98	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T9,*T10,*T11	Yes	T9,T10,T11	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T337,T80,T131	Yes	T337,T80,T131	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T337,T80,T131	Yes	T337,T80,T131	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T337,T80,T131	Yes	T337,T80,T131	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T337,T80,T131	Yes	T337,T80,T131	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T337,T80,T131	Yes	T337,T80,T131	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T337,T80,T131	Yes	T337,T80,T131	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T98,T103,T169	Yes	T98,T103,T169	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T337,T80,T131	Yes	T337,T80,T131	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T337,T80,T131	Yes	T337,T80,T131	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T98,T103,T169	Yes	T98,T103,T169	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T337,T131,T37	Yes	T337,T131,T37	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T337,T131,T256	Yes	T337,T80,T131	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T337,T131,T37	Yes	T337,T131,T37	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T98,*T103,*T169	Yes	T96,T97,T98	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T96,T98,T103	Yes	T98,T103,T169	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T337,*T131,*T256	Yes	T337,T131,T256	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T337,T80,T131	Yes	T337,T80,T131	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T7,T31,T8	Yes	T7,T31,T8	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T7,T8,T16	Yes	T7,T8,T16	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T7,T31,T8	Yes	T7,T31,T8	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T7,T31,T8	Yes	T7,T31,T8	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T7,T8,T16	Yes	T7,T8,T16	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T7,T31,T8	Yes	T7,T31,T8	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T7,T31,T8	Yes	T7,T31,T8	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T7,T31,T8	Yes	T7,T31,T8	INPUT
tl_usbdev_i.d_error	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T7,T8,T16	Yes	T7,T31,T8	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T7,T31,T8	Yes	T7,T8,T16	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T7,T31,T8	Yes	T7,T8,T16	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T96,*T98,*T103	Yes	T96,T97,T98	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T7,*T8,*T16	Yes	T7,T8,T16	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T7,T31,T8	Yes	T7,T31,T8	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T45,T39,T29	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T4,T124,T45	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T45,T39,T29	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T97,T98,T103	Yes	T97,T98,T103	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T307,T308,T309	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T98,T103	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T96,T97,T98	Yes	T96,T98,T103	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T96,T98,T103	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T98,T103,T169	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T96,*T98,*T103	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T45,T39,T29	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_hmac_o.d_ready	Yes	Yes	T45,T39,T29	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T80,T659,T660	Yes	T80,T659,T660	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T80,T659,T660	Yes	T80,T659,T660	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T80,T659,T660	Yes	T80,T659,T660	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T80,T659,T660	Yes	T80,T659,T660	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T80,T659,T660	Yes	T80,T659,T660	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T659,T660,T254	Yes	T659,T660,T254	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T80,T659,T660	Yes	T80,T659,T660	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T80,T659,T660	Yes	T80,T659,T660	INPUT
tl_hmac_i.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T659,T660,T254	Yes	T659,T660,T254	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T659,T660,T254	Yes	T659,T660,T254	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T80,T659,T660	Yes	T659,T660,T254	INPUT
tl_hmac_i.d_sink	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T98,*T103,*T169	Yes	T96,T97,T98	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T80,*T659,*T660	Yes	T659,T660,T254	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T80,T659,T660	Yes	T80,T659,T660	INPUT
tl_kmac_o.d_ready	Yes	Yes	T45,T39,T235	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T235,T80,T458	Yes	T235,T80,T458	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T39,T235,T275	Yes	T39,T235,T275	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T39,T235,T275	Yes	T39,T235,T275	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T235,T80,T458	Yes	T235,T80,T458	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T39,T235,T275	Yes	T39,T235,T275	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T71,*T96,*T97	Yes	T71,T96,T97	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T235,T458,T459	Yes	T235,T458,T459	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T39,T235,T275	Yes	T39,T235,T275	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T39,T235,T275	Yes	T39,T235,T275	INPUT
tl_kmac_i.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T39,T235,T275	Yes	T39,T235,T275	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T39,T235,T275	Yes	T39,T235,T275	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T39,T235,T275	Yes	T39,T235,T216	INPUT
tl_kmac_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T71,*T96,*T97	Yes	T71,T96,T97	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T39,*T235,*T275	Yes	T39,T235,T216	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T39,T235,T275	Yes	T39,T235,T275	INPUT
tl_aes_o.d_ready	Yes	Yes	T45,T39,T29	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T321,T322,T416	Yes	T321,T322,T416	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T321,T322,T416	Yes	T321,T322,T416	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T321,T322,T416	Yes	T321,T322,T416	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T321,T322,T416	Yes	T321,T322,T416	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T321,T322,T416	Yes	T321,T322,T416	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T101,*T96,*T97	Yes	T101,T96,T97	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T321,T322,T416	Yes	T321,T322,T416	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T321,T322,T416	Yes	T321,T322,T416	INPUT
tl_aes_i.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T321,T322,T416	Yes	T321,T322,T416	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T321,T322,T416	Yes	T321,T322,T416	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T321,T322,T416	Yes	T321,T322,T416	INPUT
tl_aes_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T101,*T97,*T98	Yes	T101,T96,T97	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T321,*T322,*T416	Yes	T321,T322,T416	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T321,T322,T416	Yes	T321,T322,T416	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T97,T98,T103	Yes	T97,T98,T103	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T97,T98,T103	Yes	T96,T97,T98	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T166,T167,T168	Yes	T166,T167,T168	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T39,T46	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T45,T39,T46	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T98,*T103,*T169	Yes	T96,T97,T98	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T97,T98,T103	Yes	T97,T98,T103	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T166,*T167,*T168	Yes	T166,T167,T168	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T416,T80,T166	Yes	T416,T80,T166	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T101,*T96,*T97	Yes	T101,T96,T97	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T97,T98,T103	Yes	T97,T98,T103	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T416,T166,T625	Yes	T416,T166,T625	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T39,T46	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T45,T39,T46	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T101,*T97,*T98	Yes	T101,T96,T97	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T416,*T166,*T625	Yes	T416,T166,T625	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T416,T80,T166	Yes	T416,T80,T166	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T416,T80,T166	Yes	T416,T80,T166	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T416,T166,T168	Yes	T416,T166,T168	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T39,T46	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T45,T39,T46	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T98,*T103,*T169	Yes	T96,T97,T98	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T98,T103	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T416,*T166,*T168	Yes	T416,T166,T168	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T45,T39,T29	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T80,T166,T168	Yes	T80,T166,T168	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T80,T166,T168	Yes	T80,T166,T168	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T80,T166,T168	Yes	T80,T166,T168	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T80,T166,T168	Yes	T80,T166,T168	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T80,T166,T168	Yes	T80,T166,T168	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T80,T166,T168	Yes	T80,T166,T168	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T80,T166,T168	Yes	T80,T166,T168	INPUT
tl_edn1_i.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T166,T168,T163	Yes	T166,T168,T163	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T168,T163,T304	Yes	T80,T166,T168	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T168,T163,T304	Yes	T80,T166,T168	INPUT
tl_edn1_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T96,*T98,*T103	Yes	T96,T97,T98	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T166,*T168,*T163	Yes	T166,T168,T163	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T80,T166,T168	Yes	T80,T166,T168	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T97,T98,T103	Yes	T97,T98,T103	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T97,T98,T103	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T98,*T103,*T169	Yes	T96,T97,T98	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T97,T98,T103	Yes	T97,T98,T103	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_otbn_o.d_ready	Yes	Yes	T45,T39,T29	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T80,T224,T168	Yes	T80,T224,T168	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T80,T224,T168	Yes	T80,T224,T168	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T80,T224,T168	Yes	T80,T224,T168	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T80,T224,T168	Yes	T80,T224,T168	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T80,T224,T168	Yes	T80,T224,T168	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T38,*T102,*T240	Yes	T38,T102,T240	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T80,T224,T168	Yes	T80,T224,T168	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T80,T224,T168	Yes	T80,T224,T168	INPUT
tl_otbn_i.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T224,T168,T163	Yes	T224,T168,T163	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T224,T168,T163	Yes	T224,T168,T163	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T80,T224,T168	Yes	T224,T168,T163	INPUT
tl_otbn_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T38,*T102,*T240	Yes	T38,T102,T240	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T80,*T224,*T168	Yes	T224,T168,T163	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T80,T224,T168	Yes	T80,T224,T168	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T45,T39,T29	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T39,T216,T80	Yes	T39,T216,T80	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T39,T275,T216	Yes	T39,T275,T216	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T39,T275,T216	Yes	T39,T275,T216	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T39,T216,T80	Yes	T39,T216,T80	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T39,T275,T216	Yes	T39,T275,T216	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T39,T275,T216	Yes	T39,T275,T216	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T39,T275,T216	Yes	T39,T275,T216	INPUT
tl_keymgr_i.d_error	Yes	Yes	T98,T169,T276	Yes	T97,T98,T169	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T39,T216,T206	Yes	T39,T216,T206	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T39,T216,T206	Yes	T39,T216,T80	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T39,T216,T206	Yes	T39,T216,T80	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T98,*T103,*T169	Yes	T96,T97,T98	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T39,*T216,*T206	Yes	T39,T275,T216	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T39,T275,T216	Yes	T39,T275,T216	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T311,*T96,*T97	Yes	T311,T96,T97	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T97,T98,T103	Yes	T97,T98,T103	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T96,T98,T103	Yes	T96,T98,T103	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T311,T96,T97	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T45,T39,T29	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T80,T156,T217	Yes	T80,T156,T217	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T80,T156,T217	Yes	T80,T156,T217	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T80,T156,T217	Yes	T80,T156,T217	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T80,T156,T217	Yes	T80,T156,T217	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T80,T156,T217	Yes	T80,T156,T217	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T451,*T96,*T97	Yes	T451,T96,T97	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T80,T156,T217	Yes	T80,T156,T217	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T80,T156,T217	Yes	T80,T156,T217	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T220,T346,T347	Yes	T220,T346,T347	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T156,T217,T220	Yes	T80,T156,T217	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T156,T217,T220	Yes	T80,T156,T217	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T97,*T98,*T103	Yes	T451,T96,T97	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T156,*T217,*T220	Yes	T156,T217,T220	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T80,T156,T217	Yes	T80,T156,T217	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T45,T39,T29	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range