Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pwm_aon.u_reg.u_invert_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T6 T25 T76 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T6 T25 T76 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T6 T25 T76 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T6 T25 T76 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T6 T25 T76 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T6 T25 T76 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T6 T25 T76 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T6 T25 T76 
135        1/1                txn_bits_q <= '0;
           Tests:       T6 T25 T76 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T6 T25 T76 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T6 T25 T76 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T6 T25 T76 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T6,T25,T76

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T25,T76
1	1	Covered	T6,T25,T76

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T6,T25,T76
1	-	Covered	T6,T25,T76

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T6,T25,T76

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T25,T76
1	1	Covered	T6,T25,T76

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T25,T76
0	0	1	Covered	T6,T25,T76
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T25,T76
0	0	1	Covered	T6,T25,T76
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	144433419	122930	0	0
DstReqKnown_A	1673854	1450496	0	0
SrcAckBusyChk_A	144433419	306	0	0
SrcBusyKnown_A	144433419	143627870	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	122930	0	0
T6	37322	2142	0	0
T9	20410	0	0	0
T12	33850	0	0	0
T25	29026	712	0	0
T26	51721	0	0	0
T31	20612	0	0	0
T45	57350	0	0	0
T76	0	781	0	0
T83	0	960	0	0
T84	0	2075	0	0
T85	0	1847	0	0
T107	15625	0	0	0
T124	27106	0	0	0
T125	19208	0	0	0
T188	0	316	0	0
T189	0	697	0	0
T401	0	261	0	0
T426	0	270	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1673854	1450496	0	0
T1	285	111	0	0
T2	412	239	0	0
T3	378	204	0	0
T4	501	330	0	0
T5	360	186	0	0
T6	599	425	0	0
T7	447	273	0	0
T9	347	173	0	0
T25	509	338	0	0
T107	450	276	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	306	0	0
T6	37322	5	0	0
T9	20410	0	0	0
T12	33850	0	0	0
T25	29026	2	0	0
T26	51721	0	0	0
T31	20612	0	0	0
T45	57350	0	0	0
T76	0	2	0	0
T83	0	2	0	0
T84	0	5	0	0
T85	0	5	0	0
T107	15625	0	0	0
T124	27106	0	0	0
T125	19208	0	0	0
T188	0	1	0	0
T189	0	2	0	0
T401	0	1	0	0
T426	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	143627870	0	0
T1	11204	10507	0	0
T2	23341	22863	0	0
T3	18404	17881	0	0
T4	20300	19973	0	0
T5	21790	21001	0	0
T6	37322	36958	0	0
T7	26668	26130	0	0
T9	20410	19606	0	0
T25	29026	28597	0	0
T107	15625	15308	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T96 T97 T98 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T177 T179 T188 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T177 T179 T188 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T177 T179 T188 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T177 T179 T188 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T177 T179 T188 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T177 T179 T188 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T177 T179 T188 
135        1/1                txn_bits_q <= '0;
           Tests:       T177 T179 T188 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        0/1     ==>    assign src_qs_o = src_q;
156        0/1     ==>    assign dst_wd_o = src_q;
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T177 T179 T188 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T177,T179,T188

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T177,T179,T188
1	1	Covered	T177,T179,T188

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T177,T179,T188
1	-	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T177,T179,T188

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T177,T179,T188
1	1	Covered	T177,T179,T188

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T177,T179,T188
0	0	1	Covered	T177,T179,T188
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T177,T179,T188
0	0	1	Covered	T177,T179,T188
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	144433419	125591	0	0
DstReqKnown_A	1673854	1450496	0	0
SrcAckBusyChk_A	144433419	316	0	0
SrcBusyKnown_A	144433419	143627870	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	125591	0	0
T188	58214	286	0	0
T189	78753	692	0	0
T401	42537	252	0	0
T413	127034	705	0	0
T414	93359	878	0	0
T426	62299	261	0	0
T427	49042	458	0	0
T428	66344	475	0	0
T429	52741	382	0	0
T430	66679	441	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1673854	1450496	0	0
T1	285	111	0	0
T2	412	239	0	0
T3	378	204	0	0
T4	501	330	0	0
T5	360	186	0	0
T6	599	425	0	0
T7	447	273	0	0
T9	347	173	0	0
T25	509	338	0	0
T107	450	276	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	316	0	0
T188	58214	1	0	0
T189	78753	2	0	0
T401	42537	1	0	0
T413	127034	2	0	0
T414	93359	2	0	0
T426	62299	1	0	0
T427	49042	1	0	0
T428	66344	1	0	0
T429	52741	1	0	0
T430	66679	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	143627870	0	0
T1	11204	10507	0	0
T2	23341	22863	0	0
T3	18404	17881	0	0
T4	20300	19973	0	0
T5	21790	21001	0	0
T6	37322	36958	0	0
T7	26668	26130	0	0
T9	20410	19606	0	0
T25	29026	28597	0	0
T107	15625	15308	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T96 T97 T98 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T177 T179 T188 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T177 T179 T188 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T177 T179 T188 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T177 T179 T188 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T177 T179 T188 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T177 T179 T188 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T177 T179 T188 
135        1/1                txn_bits_q <= '0;
           Tests:       T177 T179 T188 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        0/1     ==>    assign src_qs_o = src_q;
156        0/1     ==>    assign dst_wd_o = src_q;
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T177 T179 T188 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T177,T179,T188

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T177,T179,T188
1	1	Covered	T177,T179,T188

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T177,T179,T188
1	-	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T177,T179,T188

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T177,T179,T188
1	1	Covered	T177,T179,T188

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T177,T179,T188
0	0	1	Covered	T177,T179,T188
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T177,T179,T188
0	0	1	Covered	T177,T179,T188
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	144433419	135051	0	0
DstReqKnown_A	1673854	1450496	0	0
SrcAckBusyChk_A	144433419	337	0	0
SrcBusyKnown_A	144433419	143627870	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	135051	0	0
T188	58214	346	0	0
T189	78753	641	0	0
T401	42537	299	0	0
T413	127034	781	0	0
T414	93359	819	0	0
T426	62299	344	0	0
T427	49042	473	0	0
T428	66344	438	0	0
T429	52741	371	0	0
T430	66679	459	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1673854	1450496	0	0
T1	285	111	0	0
T2	412	239	0	0
T3	378	204	0	0
T4	501	330	0	0
T5	360	186	0	0
T6	599	425	0	0
T7	447	273	0	0
T9	347	173	0	0
T25	509	338	0	0
T107	450	276	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	337	0	0
T188	58214	1	0	0
T189	78753	2	0	0
T401	42537	1	0	0
T413	127034	2	0	0
T414	93359	2	0	0
T426	62299	1	0	0
T427	49042	1	0	0
T428	66344	1	0	0
T429	52741	1	0	0
T430	66679	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	143627870	0	0
T1	11204	10507	0	0
T2	23341	22863	0	0
T3	18404	17881	0	0
T4	20300	19973	0	0
T5	21790	21001	0	0
T6	37322	36958	0	0
T7	26668	26130	0	0
T9	20410	19606	0	0
T25	29026	28597	0	0
T107	15625	15308	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T23 T96 T97 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T23 T177 T179 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T23 T177 T179 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T23 T177 T179 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T23 T177 T179 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T23 T177 T179 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T23 T177 T179 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T23 T177 T179 
135        1/1                txn_bits_q <= '0;
           Tests:       T23 T177 T179 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T23 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T23 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T23 T177 T179 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T23,T177,T432

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T177,T179
1	1	Covered	T23,T177,T179

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T23,T177,T179
1	-	Covered	T23

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T23,T177,T179

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T23,T177,T179
1	1	Covered	T23,T177,T179

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T23,T177,T179
0	0	1	Covered	T23,T177,T179
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T23,T177,T179
0	0	1	Covered	T23,T177,T179
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	144433419	116210	0	0
DstReqKnown_A	1673854	1450496	0	0
SrcAckBusyChk_A	144433419	293	0	0
SrcBusyKnown_A	144433419	143627870	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	116210	0	0
T23	23820	856	0	0
T47	25688	0	0	0
T138	51054	0	0	0
T140	21393	0	0	0
T188	0	306	0	0
T189	0	649	0	0
T401	0	345	0	0
T413	0	723	0	0
T414	0	857	0	0
T426	0	305	0	0
T427	0	448	0	0
T428	0	476	0	0
T429	0	477	0	0
T433	308867	0	0	0
T434	324117	0	0	0
T435	326818	0	0	0
T436	326348	0	0	0
T437	290224	0	0	0
T438	300660	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1673854	1450496	0	0
T1	285	111	0	0
T2	412	239	0	0
T3	378	204	0	0
T4	501	330	0	0
T5	360	186	0	0
T6	599	425	0	0
T7	447	273	0	0
T9	347	173	0	0
T25	509	338	0	0
T107	450	276	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	293	0	0
T23	23820	2	0	0
T47	25688	0	0	0
T138	51054	0	0	0
T140	21393	0	0	0
T188	0	1	0	0
T189	0	2	0	0
T401	0	1	0	0
T413	0	2	0	0
T414	0	2	0	0
T426	0	1	0	0
T427	0	1	0	0
T428	0	1	0	0
T429	0	1	0	0
T433	308867	0	0	0
T434	324117	0	0	0
T435	326818	0	0	0
T436	326348	0	0	0
T437	290224	0	0	0
T438	300660	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	143627870	0	0
T1	11204	10507	0	0
T2	23341	22863	0	0
T3	18404	17881	0	0
T4	20300	19973	0	0
T5	21790	21001	0	0
T6	37322	36958	0	0
T7	26668	26130	0	0
T9	20410	19606	0	0
T25	29026	28597	0	0
T107	15625	15308	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T96 T97 T98 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T177 T179 T188 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T177 T179 T188 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T177 T179 T188 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T177 T179 T188 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T177 T179 T188 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T177 T179 T188 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T177 T179 T188 
135        1/1                txn_bits_q <= '0;
           Tests:       T177 T179 T188 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        0/1     ==>    assign src_qs_o = src_q;
156        0/1     ==>    assign dst_wd_o = src_q;
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T177 T179 T188 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T439,T177,T432

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T177,T179,T188
1	1	Covered	T177,T179,T188

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T177,T179,T188
1	-	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T177,T179,T188

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T177,T179,T188
1	1	Covered	T177,T179,T188

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T177,T179,T188
0	0	1	Covered	T177,T179,T188
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T177,T179,T188
0	0	1	Covered	T177,T179,T188
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	144433419	117301	0	0
DstReqKnown_A	1673854	1450496	0	0
SrcAckBusyChk_A	144433419	293	0	0
SrcBusyKnown_A	144433419	143627870	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	117301	0	0
T188	58214	352	0	0
T189	78753	683	0	0
T401	42537	309	0	0
T413	127034	718	0	0
T414	93359	801	0	0
T426	62299	256	0	0
T427	49042	394	0	0
T428	66344	476	0	0
T429	52741	386	0	0
T430	66679	392	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1673854	1450496	0	0
T1	285	111	0	0
T2	412	239	0	0
T3	378	204	0	0
T4	501	330	0	0
T5	360	186	0	0
T6	599	425	0	0
T7	447	273	0	0
T9	347	173	0	0
T25	509	338	0	0
T107	450	276	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	293	0	0
T188	58214	1	0	0
T189	78753	2	0	0
T401	42537	1	0	0
T413	127034	2	0	0
T414	93359	2	0	0
T426	62299	1	0	0
T427	49042	1	0	0
T428	66344	1	0	0
T429	52741	1	0	0
T430	66679	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	143627870	0	0
T1	11204	10507	0	0
T2	23341	22863	0	0
T3	18404	17881	0	0
T4	20300	19973	0	0
T5	21790	21001	0	0
T6	37322	36958	0	0
T7	26668	26130	0	0
T9	20410	19606	0	0
T25	29026	28597	0	0
T107	15625	15308	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T77 T78 T79 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T77 T78 T79 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T77 T78 T79 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T77 T78 T79 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T77 T78 T79 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T77 T78 T79 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T77 T78 T79 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T77 T78 T79 
135        1/1                txn_bits_q <= '0;
           Tests:       T77 T78 T79 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T77 T78 T79 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T77 T78 T79 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T77 T78 T79 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T77,T78,T79

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T77,T78,T79
1	1	Covered	T77,T78,T79

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T77,T78,T79
1	-	Covered	T77,T78,T79

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T77,T78,T79

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T77,T78,T79
1	1	Covered	T77,T78,T79

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T77,T78,T79
0	0	1	Covered	T77,T78,T79
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T77,T78,T79
0	0	1	Covered	T77,T78,T79
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	144433419	128580	0	0
DstReqKnown_A	1673854	1450496	0	0
SrcAckBusyChk_A	144433419	324	0	0
SrcBusyKnown_A	144433419	143627870	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	128580	0	0
T14	278654	0	0	0
T32	24069	0	0	0
T33	20553	0	0	0
T77	46962	728	0	0
T78	0	1548	0	0
T79	0	648	0	0
T123	0	620	0	0
T128	0	1529	0	0
T129	0	1439	0	0
T136	266906	0	0	0
T188	0	276	0	0
T351	42531	0	0	0
T418	0	863	0	0
T431	0	648	0	0
T440	0	874	0	0
T441	67809	0	0	0
T442	57178	0	0	0
T443	10943	0	0	0
T444	134108	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1673854	1450496	0	0
T1	285	111	0	0
T2	412	239	0	0
T3	378	204	0	0
T4	501	330	0	0
T5	360	186	0	0
T6	599	425	0	0
T7	447	273	0	0
T9	347	173	0	0
T25	509	338	0	0
T107	450	276	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	324	0	0
T14	278654	0	0	0
T32	24069	0	0	0
T33	20553	0	0	0
T77	46962	2	0	0
T78	0	4	0	0
T79	0	2	0	0
T123	0	2	0	0
T128	0	4	0	0
T129	0	4	0	0
T136	266906	0	0	0
T188	0	1	0	0
T351	42531	0	0	0
T418	0	2	0	0
T431	0	2	0	0
T440	0	2	0	0
T441	67809	0	0	0
T442	57178	0	0	0
T443	10943	0	0	0
T444	134108	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	143627870	0	0
T1	11204	10507	0	0
T2	23341	22863	0	0
T3	18404	17881	0	0
T4	20300	19973	0	0
T5	21790	21001	0	0
T6	37322	36958	0	0
T7	26668	26130	0	0
T9	20410	19606	0	0
T25	29026	28597	0	0
T107	15625	15308	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	0	0.00
CONT_ASSIGN	156	1	0	0.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T96 T97 T98 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T177 T179 T188 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T177 T179 T188 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T177 T179 T188 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T177 T179 T188 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T177 T179 T188 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T177 T179 T188 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T177 T179 T188 
135        1/1                txn_bits_q <= '0;
           Tests:       T177 T179 T188 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        0/1     ==>    assign src_qs_o = src_q;
156        0/1     ==>    assign dst_wd_o = src_q;
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T177 T179 T188 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T177,T179,T188

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T177,T179,T188
1	1	Covered	T177,T179,T188

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T177,T179,T188
1	-	Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T177,T179,T188

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T177,T179,T188
1	1	Covered	T177,T179,T188

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T177,T179,T188
0	0	1	Covered	T177,T179,T188
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T177,T179,T188
0	0	1	Covered	T177,T179,T188
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	144433419	121306	0	0
DstReqKnown_A	1673854	1450496	0	0
SrcAckBusyChk_A	144433419	306	0	0
SrcBusyKnown_A	144433419	143627870	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	121306	0	0
T188	58214	288	0	0
T189	78753	678	0	0
T401	42537	316	0	0
T413	127034	788	0	0
T414	93359	810	0	0
T426	62299	249	0	0
T427	49042	387	0	0
T428	66344	477	0	0
T429	52741	455	0	0
T430	66679	472	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1673854	1450496	0	0
T1	285	111	0	0
T2	412	239	0	0
T3	378	204	0	0
T4	501	330	0	0
T5	360	186	0	0
T6	599	425	0	0
T7	447	273	0	0
T9	347	173	0	0
T25	509	338	0	0
T107	450	276	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	306	0	0
T188	58214	1	0	0
T189	78753	2	0	0
T401	42537	1	0	0
T413	127034	2	0	0
T414	93359	2	0	0
T426	62299	1	0	0
T427	49042	1	0	0
T428	66344	1	0	0
T429	52741	1	0	0
T430	66679	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	143627870	0	0
T1	11204	10507	0	0
T2	23341	22863	0	0
T3	18404	17881	0	0
T4	20300	19973	0	0
T5	21790	21001	0	0
T6	37322	36958	0	0
T7	26668	26130	0	0
T9	20410	19606	0	0
T25	29026	28597	0	0
T107	15625	15308	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T4 T24 T96 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T4 T24 T177 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T4 T24 T177 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T4 T24 T177 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T4 T24 T177 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T4 T24 T177 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T4 T24 T177 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T4 T24 T177 
135        1/1                txn_bits_q <= '0;
           Tests:       T4 T24 T177 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T4 T24 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T4 T24 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T4 T24 T177 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T4,T24,T445

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T24,T177
1	1	Covered	T4,T24,T177

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T4,T24,T177
1	-	Covered	T4,T24

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T4,T24,T177

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T24,T177
1	1	Covered	T4,T24,T177

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T24,T177
0	0	1	Covered	T4,T24,T177
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T24,T177
0	0	1	Covered	T4,T24,T177
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	144433419	127942	0	0
DstReqKnown_A	1673854	1450496	0	0
SrcAckBusyChk_A	144433419	317	0	0
SrcBusyKnown_A	144433419	143627870	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	127942	0	0
T4	20300	941	0	0
T5	21790	0	0	0
T6	37322	0	0	0
T7	26668	0	0	0
T9	20410	0	0	0
T24	0	1052	0	0
T25	29026	0	0	0
T31	20612	0	0	0
T107	15625	0	0	0
T124	27106	0	0	0
T125	19208	0	0	0
T188	0	331	0	0
T189	0	738	0	0
T401	0	304	0	0
T413	0	708	0	0
T414	0	869	0	0
T426	0	313	0	0
T427	0	457	0	0
T428	0	394	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1673854	1450496	0	0
T1	285	111	0	0
T2	412	239	0	0
T3	378	204	0	0
T4	501	330	0	0
T5	360	186	0	0
T6	599	425	0	0
T7	447	273	0	0
T9	347	173	0	0
T25	509	338	0	0
T107	450	276	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	317	0	0
T4	20300	2	0	0
T5	21790	0	0	0
T6	37322	0	0	0
T7	26668	0	0	0
T9	20410	0	0	0
T24	0	2	0	0
T25	29026	0	0	0
T31	20612	0	0	0
T107	15625	0	0	0
T124	27106	0	0	0
T125	19208	0	0	0
T188	0	1	0	0
T189	0	2	0	0
T401	0	1	0	0
T413	0	2	0	0
T414	0	2	0	0
T426	0	1	0	0
T427	0	1	0	0
T428	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	143627870	0	0
T1	11204	10507	0	0
T2	23341	22863	0	0
T3	18404	17881	0	0
T4	20300	19973	0	0
T5	21790	21001	0	0
T6	37322	36958	0	0
T7	26668	26130	0	0
T9	20410	19606	0	0
T25	29026	28597	0	0
T107	15625	15308	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T6 T25 T76 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T6 T25 T76 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T6 T25 T76 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T6 T25 T76 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T6 T25 T76 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T6 T25 T76 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T6 T25 T76 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T6 T25 T76 
135        1/1                txn_bits_q <= '0;
           Tests:       T6 T25 T76 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T6 T84 T85 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T6 T84 T85 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T6 T25 T76 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T6,T25,T76

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T25,T76
1	1	Covered	T6,T25,T76

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T6,T25,T76

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T25,T76
1	1	Covered	T6,T25,T76

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T25,T76
0	0	1	Covered	T6,T25,T76
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T25,T76
0	0	1	Covered	T6,T25,T76
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	144433419	135345	0	0
DstReqKnown_A	1673854	1450496	0	0
SrcAckBusyChk_A	144433419	339	0	0
SrcBusyKnown_A	144433419	143627870	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	135345	0	0
T6	37322	841	0	0
T9	20410	0	0	0
T12	33850	0	0	0
T25	29026	336	0	0
T26	51721	0	0	0
T31	20612	0	0	0
T45	57350	0	0	0
T76	0	406	0	0
T83	0	465	0	0
T84	0	778	0	0
T85	0	795	0	0
T107	15625	0	0	0
T124	27106	0	0	0
T125	19208	0	0	0
T188	0	301	0	0
T189	0	812	0	0
T401	0	309	0	0
T426	0	352	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1673854	1450496	0	0
T1	285	111	0	0
T2	412	239	0	0
T3	378	204	0	0
T4	501	330	0	0
T5	360	186	0	0
T6	599	425	0	0
T7	447	273	0	0
T9	347	173	0	0
T25	509	338	0	0
T107	450	276	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	339	0	0
T6	37322	2	0	0
T9	20410	0	0	0
T12	33850	0	0	0
T25	29026	1	0	0
T26	51721	0	0	0
T31	20612	0	0	0
T45	57350	0	0	0
T76	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0
T85	0	2	0	0
T107	15625	0	0	0
T124	27106	0	0	0
T125	19208	0	0	0
T188	0	1	0	0
T189	0	2	0	0
T401	0	1	0	0
T426	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	143627870	0	0
T1	11204	10507	0	0
T2	23341	22863	0	0
T3	18404	17881	0	0
T4	20300	19973	0	0
T5	21790	21001	0	0
T6	37322	36958	0	0
T7	26668	26130	0	0
T9	20410	19606	0	0
T25	29026	28597	0	0
T107	15625	15308	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T96 T97 T98 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T177 T179 T188 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T177 T179 T188 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T177 T179 T188 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T177 T179 T188 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T177 T179 T188 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T177 T179 T188 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T177 T179 T188 
135        1/1                txn_bits_q <= '0;
           Tests:       T177 T179 T188 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T177 T179 T188 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T177 T179 T188 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T177 T179 T188 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T439,T446,T177

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T177,T179,T188
1	1	Covered	T177,T179,T188

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T177,T179,T188

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T177,T179,T188
1	1	Covered	T177,T179,T188

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T177,T179,T188
0	0	1	Covered	T177,T179,T188
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T177,T179,T188
0	0	1	Covered	T177,T179,T188
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	144433419	128340	0	0
DstReqKnown_A	1673854	1450496	0	0
SrcAckBusyChk_A	144433419	321	0	0
SrcBusyKnown_A	144433419	143627870	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	128340	0	0
T188	58214	250	0	0
T189	78753	650	0	0
T401	42537	247	0	0
T413	127034	712	0	0
T414	93359	858	0	0
T426	62299	361	0	0
T427	49042	403	0	0
T428	66344	369	0	0
T429	52741	381	0	0
T430	66679	405	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1673854	1450496	0	0
T1	285	111	0	0
T2	412	239	0	0
T3	378	204	0	0
T4	501	330	0	0
T5	360	186	0	0
T6	599	425	0	0
T7	447	273	0	0
T9	347	173	0	0
T25	509	338	0	0
T107	450	276	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	321	0	0
T188	58214	1	0	0
T189	78753	2	0	0
T401	42537	1	0	0
T413	127034	2	0	0
T414	93359	2	0	0
T426	62299	1	0	0
T427	49042	1	0	0
T428	66344	1	0	0
T429	52741	1	0	0
T430	66679	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	143627870	0	0
T1	11204	10507	0	0
T2	23341	22863	0	0
T3	18404	17881	0	0
T4	20300	19973	0	0
T5	21790	21001	0	0
T6	37322	36958	0	0
T7	26668	26130	0	0
T9	20410	19606	0	0
T25	29026	28597	0	0
T107	15625	15308	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T96 T97 T98 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T177 T179 T188 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T177 T179 T188 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T177 T179 T188 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T177 T179 T188 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T177 T179 T188 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T177 T179 T188 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T177 T179 T188 
135        1/1                txn_bits_q <= '0;
           Tests:       T177 T179 T188 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T177 T179 T188 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T177 T179 T188 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T177 T179 T188 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T177,T179,T447

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T177,T179,T188
1	1	Covered	T177,T179,T188

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T177,T179,T188

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T177,T179,T188
1	1	Covered	T177,T179,T188

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T177,T179,T188
0	0	1	Covered	T177,T179,T188
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T177,T179,T188
0	0	1	Covered	T177,T179,T188
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	144433419	112983	0	0
DstReqKnown_A	1673854	1450496	0	0
SrcAckBusyChk_A	144433419	282	0	0
SrcBusyKnown_A	144433419	143627870	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	112983	0	0
T188	58214	352	0	0
T189	78753	658	0	0
T401	42537	322	0	0
T413	127034	659	0	0
T414	93359	831	0	0
T426	62299	326	0	0
T427	49042	408	0	0
T428	66344	404	0	0
T429	52741	425	0	0
T430	66679	451	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1673854	1450496	0	0
T1	285	111	0	0
T2	412	239	0	0
T3	378	204	0	0
T4	501	330	0	0
T5	360	186	0	0
T6	599	425	0	0
T7	447	273	0	0
T9	347	173	0	0
T25	509	338	0	0
T107	450	276	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	282	0	0
T188	58214	1	0	0
T189	78753	2	0	0
T401	42537	1	0	0
T413	127034	2	0	0
T414	93359	2	0	0
T426	62299	1	0	0
T427	49042	1	0	0
T428	66344	1	0	0
T429	52741	1	0	0
T430	66679	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	143627870	0	0
T1	11204	10507	0	0
T2	23341	22863	0	0
T3	18404	17881	0	0
T4	20300	19973	0	0
T5	21790	21001	0	0
T6	37322	36958	0	0
T7	26668	26130	0	0
T9	20410	19606	0	0
T25	29026	28597	0	0
T107	15625	15308	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T23 T96 T97 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T23 T177 T179 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T23 T177 T179 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T23 T177 T179 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T23 T177 T179 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T23 T177 T179 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T23 T177 T179 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T23 T177 T179 
135        1/1                txn_bits_q <= '0;
           Tests:       T23 T177 T179 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T23 T177 T179 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T23 T177 T179 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T23 T177 T179 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T23,T177,T179

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T177,T179
1	1	Covered	T23,T177,T179

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T23,T177,T179

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T23,T177,T179
1	1	Covered	T23,T177,T179

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T23,T177,T179
0	0	1	Covered	T23,T177,T179
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T23,T177,T179
0	0	1	Covered	T23,T177,T179
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	144433419	108177	0	0
DstReqKnown_A	1673854	1450496	0	0
SrcAckBusyChk_A	144433419	276	0	0
SrcBusyKnown_A	144433419	143627870	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	108177	0	0
T23	23820	313	0	0
T47	25688	0	0	0
T138	51054	0	0	0
T140	21393	0	0	0
T188	0	310	0	0
T189	0	678	0	0
T401	0	281	0	0
T413	0	711	0	0
T414	0	817	0	0
T426	0	248	0	0
T427	0	429	0	0
T428	0	396	0	0
T429	0	382	0	0
T433	308867	0	0	0
T434	324117	0	0	0
T435	326818	0	0	0
T436	326348	0	0	0
T437	290224	0	0	0
T438	300660	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1673854	1450496	0	0
T1	285	111	0	0
T2	412	239	0	0
T3	378	204	0	0
T4	501	330	0	0
T5	360	186	0	0
T6	599	425	0	0
T7	447	273	0	0
T9	347	173	0	0
T25	509	338	0	0
T107	450	276	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	276	0	0
T23	23820	1	0	0
T47	25688	0	0	0
T138	51054	0	0	0
T140	21393	0	0	0
T188	0	1	0	0
T189	0	2	0	0
T401	0	1	0	0
T413	0	2	0	0
T414	0	2	0	0
T426	0	1	0	0
T427	0	1	0	0
T428	0	1	0	0
T429	0	1	0	0
T433	308867	0	0	0
T434	324117	0	0	0
T435	326818	0	0	0
T436	326348	0	0	0
T437	290224	0	0	0
T438	300660	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	143627870	0	0
T1	11204	10507	0	0
T2	23341	22863	0	0
T3	18404	17881	0	0
T4	20300	19973	0	0
T5	21790	21001	0	0
T6	37322	36958	0	0
T7	26668	26130	0	0
T9	20410	19606	0	0
T25	29026	28597	0	0
T107	15625	15308	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T96 T97 T98 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T177 T179 T188 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T177 T179 T188 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T177 T179 T188 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T177 T179 T188 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T177 T179 T188 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T177 T179 T188 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T177 T179 T188 
135        1/1                txn_bits_q <= '0;
           Tests:       T177 T179 T188 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T177 T179 T188 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T177 T179 T188 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T177 T179 T188 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T96,T177,T179

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T177,T179,T188
1	1	Covered	T177,T179,T188

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T177,T179,T188

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T177,T179,T188
1	1	Covered	T177,T179,T188

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T177,T179,T188
0	0	1	Covered	T177,T179,T188
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T177,T179,T188
0	0	1	Covered	T177,T179,T188
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	144433419	117798	0	0
DstReqKnown_A	1673854	1450496	0	0
SrcAckBusyChk_A	144433419	294	0	0
SrcBusyKnown_A	144433419	143627870	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	117798	0	0
T188	58214	334	0	0
T189	78753	717	0	0
T401	42537	342	0	0
T413	127034	810	0	0
T414	93359	747	0	0
T426	62299	333	0	0
T427	49042	445	0	0
T428	66344	408	0	0
T429	52741	394	0	0
T430	66679	390	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1673854	1450496	0	0
T1	285	111	0	0
T2	412	239	0	0
T3	378	204	0	0
T4	501	330	0	0
T5	360	186	0	0
T6	599	425	0	0
T7	447	273	0	0
T9	347	173	0	0
T25	509	338	0	0
T107	450	276	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	294	0	0
T188	58214	1	0	0
T189	78753	2	0	0
T401	42537	1	0	0
T413	127034	2	0	0
T414	93359	2	0	0
T426	62299	1	0	0
T427	49042	1	0	0
T428	66344	1	0	0
T429	52741	1	0	0
T430	66679	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	143627870	0	0
T1	11204	10507	0	0
T2	23341	22863	0	0
T3	18404	17881	0	0
T4	20300	19973	0	0
T5	21790	21001	0	0
T6	37322	36958	0	0
T7	26668	26130	0	0
T9	20410	19606	0	0
T25	29026	28597	0	0
T107	15625	15308	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T77 T78 T79 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T77 T78 T79 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T77 T78 T79 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T77 T78 T79 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T77 T78 T79 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T77 T78 T79 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T77 T78 T79 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T77 T78 T79 
135        1/1                txn_bits_q <= '0;
           Tests:       T77 T78 T79 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T177 T179 T188 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T177 T179 T188 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T77 T78 T79 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T77,T78,T79

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T77,T78,T79
1	1	Covered	T77,T78,T79

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T77,T78,T79

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T77,T78,T79
1	1	Covered	T77,T78,T79

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T77,T78,T79
0	0	1	Covered	T77,T78,T79
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T77,T78,T79
0	0	1	Covered	T77,T78,T79
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	144433419	123806	0	0
DstReqKnown_A	1673854	1450496	0	0
SrcAckBusyChk_A	144433419	313	0	0
SrcBusyKnown_A	144433419	143627870	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	123806	0	0
T14	278654	0	0	0
T32	24069	0	0	0
T33	20553	0	0	0
T77	46962	473	0	0
T78	0	557	0	0
T79	0	272	0	0
T123	0	244	0	0
T128	0	778	0	0
T129	0	567	0	0
T136	266906	0	0	0
T188	0	277	0	0
T351	42531	0	0	0
T418	0	368	0	0
T431	0	273	0	0
T440	0	379	0	0
T441	67809	0	0	0
T442	57178	0	0	0
T443	10943	0	0	0
T444	134108	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1673854	1450496	0	0
T1	285	111	0	0
T2	412	239	0	0
T3	378	204	0	0
T4	501	330	0	0
T5	360	186	0	0
T6	599	425	0	0
T7	447	273	0	0
T9	347	173	0	0
T25	509	338	0	0
T107	450	276	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	313	0	0
T14	278654	0	0	0
T32	24069	0	0	0
T33	20553	0	0	0
T77	46962	1	0	0
T78	0	2	0	0
T79	0	1	0	0
T123	0	1	0	0
T128	0	2	0	0
T129	0	2	0	0
T136	266906	0	0	0
T188	0	1	0	0
T351	42531	0	0	0
T418	0	1	0	0
T431	0	1	0	0
T440	0	1	0	0
T441	67809	0	0	0
T442	57178	0	0	0
T443	10943	0	0	0
T444	134108	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	143627870	0	0
T1	11204	10507	0	0
T2	23341	22863	0	0
T3	18404	17881	0	0
T4	20300	19973	0	0
T5	21790	21001	0	0
T6	37322	36958	0	0
T7	26668	26130	0	0
T9	20410	19606	0	0
T25	29026	28597	0	0
T107	15625	15308	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T96 T97 T98 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T177 T179 T188 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T177 T179 T188 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T177 T179 T188 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T177 T179 T188 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T177 T179 T188 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T177 T179 T188 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T177 T179 T188 
135        1/1                txn_bits_q <= '0;
           Tests:       T177 T179 T188 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T177 T179 T188 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T177 T179 T188 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T177 T179 T188 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T439,T177,T179

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T177,T179,T188
1	1	Covered	T177,T179,T188

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T177,T179,T188

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T177,T179,T188
1	1	Covered	T177,T179,T188

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T177,T179,T188
0	0	1	Covered	T177,T179,T188
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T177,T179,T188
0	0	1	Covered	T177,T179,T188
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	144433419	110095	0	0
DstReqKnown_A	1673854	1450496	0	0
SrcAckBusyChk_A	144433419	276	0	0
SrcBusyKnown_A	144433419	143627870	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	110095	0	0
T188	58214	351	0	0
T189	78753	641	0	0
T401	42537	302	0	0
T413	127034	730	0	0
T414	93359	836	0	0
T426	62299	322	0	0
T427	49042	378	0	0
T428	66344	437	0	0
T429	52741	436	0	0
T430	66679	431	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1673854	1450496	0	0
T1	285	111	0	0
T2	412	239	0	0
T3	378	204	0	0
T4	501	330	0	0
T5	360	186	0	0
T6	599	425	0	0
T7	447	273	0	0
T9	347	173	0	0
T25	509	338	0	0
T107	450	276	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	276	0	0
T188	58214	1	0	0
T189	78753	2	0	0
T401	42537	1	0	0
T413	127034	2	0	0
T414	93359	2	0	0
T426	62299	1	0	0
T427	49042	1	0	0
T428	66344	1	0	0
T429	52741	1	0	0
T430	66679	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	143627870	0	0
T1	11204	10507	0	0
T2	23341	22863	0	0
T3	18404	17881	0	0
T4	20300	19973	0	0
T5	21790	21001	0	0
T6	37322	36958	0	0
T7	26668	26130	0	0
T9	20410	19606	0	0
T25	29026	28597	0	0
T107	15625	15308	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T4 T24 T96 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T4 T24 T177 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T4 T24 T177 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T4 T24 T177 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T4 T24 T177 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T4 T24 T177 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T4 T24 T177 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T4 T24 T177 
135        1/1                txn_bits_q <= '0;
           Tests:       T4 T24 T177 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T177 T179 T188 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T177 T179 T188 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T4 T24 T177 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T4,T24,T98

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T24,T177
1	1	Covered	T4,T24,T177

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T4,T24,T177

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T24,T177
1	1	Covered	T4,T24,T177

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T24,T177
0	0	1	Covered	T4,T24,T177
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T24,T177
0	0	1	Covered	T4,T24,T177
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	144433419	125765	0	0
DstReqKnown_A	1673854	1450496	0	0
SrcAckBusyChk_A	144433419	313	0	0
SrcBusyKnown_A	144433419	143627870	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	125765	0	0
T4	20300	276	0	0
T5	21790	0	0	0
T6	37322	0	0	0
T7	26668	0	0	0
T9	20410	0	0	0
T24	0	387	0	0
T25	29026	0	0	0
T31	20612	0	0	0
T107	15625	0	0	0
T124	27106	0	0	0
T125	19208	0	0	0
T188	0	278	0	0
T189	0	781	0	0
T401	0	294	0	0
T413	0	623	0	0
T414	0	814	0	0
T426	0	309	0	0
T427	0	446	0	0
T428	0	454	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1673854	1450496	0	0
T1	285	111	0	0
T2	412	239	0	0
T3	378	204	0	0
T4	501	330	0	0
T5	360	186	0	0
T6	599	425	0	0
T7	447	273	0	0
T9	347	173	0	0
T25	509	338	0	0
T107	450	276	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	313	0	0
T4	20300	1	0	0
T5	21790	0	0	0
T6	37322	0	0	0
T7	26668	0	0	0
T9	20410	0	0	0
T24	0	1	0	0
T25	29026	0	0	0
T31	20612	0	0	0
T107	15625	0	0	0
T124	27106	0	0	0
T125	19208	0	0	0
T188	0	1	0	0
T189	0	2	0	0
T401	0	1	0	0
T413	0	2	0	0
T414	0	2	0	0
T426	0	1	0	0
T427	0	1	0	0
T428	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	143627870	0	0
T1	11204	10507	0	0
T2	23341	22863	0	0
T3	18404	17881	0	0
T4	20300	19973	0	0
T5	21790	21001	0	0
T6	37322	36958	0	0
T7	26668	26130	0	0
T9	20410	19606	0	0
T25	29026	28597	0	0
T107	15625	15308	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T96 T97 T98 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T177 T179 T188 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T177 T179 T188 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T177 T179 T188 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T177 T179 T188 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T177 T179 T188 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T177 T179 T188 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T177 T179 T188 
135        1/1                txn_bits_q <= '0;
           Tests:       T177 T179 T188 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T177 T179 T188 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T177 T179 T188 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T177 T179 T188 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T169,T177,T179

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T177,T179,T188
1	1	Covered	T177,T179,T188

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T177,T179,T188

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T177,T179,T188
1	1	Covered	T177,T179,T188

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T177,T179,T188
0	0	1	Covered	T177,T179,T188
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T177,T179,T188
0	0	1	Covered	T177,T179,T188
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	144433419	107783	0	0
DstReqKnown_A	1673854	1450496	0	0
SrcAckBusyChk_A	144433419	273	0	0
SrcBusyKnown_A	144433419	143627870	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	107783	0	0
T188	58214	271	0	0
T189	78753	710	0	0
T401	42537	354	0	0
T413	127034	673	0	0
T414	93359	908	0	0
T426	62299	317	0	0
T427	49042	368	0	0
T428	66344	451	0	0
T429	52741	424	0	0
T430	66679	368	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1673854	1450496	0	0
T1	285	111	0	0
T2	412	239	0	0
T3	378	204	0	0
T4	501	330	0	0
T5	360	186	0	0
T6	599	425	0	0
T7	447	273	0	0
T9	347	173	0	0
T25	509	338	0	0
T107	450	276	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	273	0	0
T188	58214	1	0	0
T189	78753	2	0	0
T401	42537	1	0	0
T413	127034	2	0	0
T414	93359	2	0	0
T426	62299	1	0	0
T427	49042	1	0	0
T428	66344	1	0	0
T429	52741	1	0	0
T430	66679	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	143627870	0	0
T1	11204	10507	0	0
T2	23341	22863	0	0
T3	18404	17881	0	0
T4	20300	19973	0	0
T5	21790	21001	0	0
T6	37322	36958	0	0
T7	26668	26130	0	0
T9	20410	19606	0	0
T25	29026	28597	0	0
T107	15625	15308	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T91 T126 T127 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T91 T126 T127 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T91 T126 T127 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T91 T126 T127 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T91 T126 T127 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T91 T126 T127 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T91 T126 T127 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T91 T126 T127 
135        1/1                txn_bits_q <= '0;
           Tests:       T91 T126 T127 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T91 T126 T127 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T91 T126 T127 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T91 T126 T127 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T91,T126,T127

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T91,T126,T127
1	1	Covered	T91,T126,T127

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T91,T126,T127

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T91,T126,T127
1	1	Covered	T91,T126,T127

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T91,T126,T127
0	0	1	Covered	T91,T126,T127
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T91,T126,T127
0	0	1	Covered	T91,T126,T127
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	144433419	131047	0	0
DstReqKnown_A	1673854	1450496	0	0
SrcAckBusyChk_A	144433419	329	0	0
SrcBusyKnown_A	144433419	143627870	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	131047	0	0
T91	36302	291	0	0
T126	0	249	0	0
T127	0	255	0	0
T172	49268	0	0	0
T185	41201	0	0	0
T188	0	313	0	0
T189	0	741	0	0
T209	54528	0	0	0
T221	21035	0	0	0
T222	21661	0	0	0
T229	105638	0	0	0
T343	128703	0	0	0
T344	158520	0	0	0
T345	19789	0	0	0
T401	0	341	0	0
T413	0	724	0	0
T426	0	308	0	0
T427	0	399	0	0
T428	0	388	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1673854	1450496	0	0
T1	285	111	0	0
T2	412	239	0	0
T3	378	204	0	0
T4	501	330	0	0
T5	360	186	0	0
T6	599	425	0	0
T7	447	273	0	0
T9	347	173	0	0
T25	509	338	0	0
T107	450	276	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	329	0	0
T91	36302	1	0	0
T126	0	1	0	0
T127	0	1	0	0
T172	49268	0	0	0
T185	41201	0	0	0
T188	0	1	0	0
T189	0	2	0	0
T209	54528	0	0	0
T221	21035	0	0	0
T222	21661	0	0	0
T229	105638	0	0	0
T343	128703	0	0	0
T344	158520	0	0	0
T345	19789	0	0	0
T401	0	1	0	0
T413	0	2	0	0
T426	0	1	0	0
T427	0	1	0	0
T428	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144433419	143627870	0	0
T1	11204	10507	0	0
T2	23341	22863	0	0
T3	18404	17881	0	0
T4	20300	19973	0	0
T5	21790	21001	0	0
T6	37322	36958	0	0
T7	26668	26130	0	0
T9	20410	19606	0	0
T25	29026	28597	0	0
T107	15625	15308	0	0