Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3786122	1			T91	86		T92	89		T93	6
values[2]	741885	1			T91	52		T92	51		T93	9
values[3]	98241	1			T93	9		T97	2		T98	1
values[4]	51532	1			T93	6		T273	1		T468	3
values[5]	34332	1			T93	8		T538	90		T510	9
values[6]	25515	1			T93	13		T538	54		T510	18
values[7]	20501	1			T93	6		T538	47		T510	30
values[8]	17797	1			T93	2		T538	41		T510	18
values[9]	15502	1			T93	4		T538	31		T510	16
values[10]	14592	1			T93	3		T538	42		T510	25
values[11]	13393	1			T93	12		T538	26		T510	15
values[12]	12745	1			T93	9		T538	29		T510	3
values[13]	12097	1			T93	5		T538	19		T510	6
values[14]	11573	1			T93	7		T538	22		T510	11
values[15]	10950	1			T93	1		T538	17		T510	2
values[16]	10937	1			T93	2		T538	19		T510	3
values[17]	10688	1			T93	1		T538	31		T510	6
values[18]	10057	1			T93	2		T538	29		T510	8
values[19]	9672	1			T93	1		T538	17		T510	9
values[20]	9370	1			T93	2		T538	15		T510	6
values[21]	8912	1			T93	3		T538	19		T510	1
values[22]	8580	1			T93	1		T538	18		T834	3
values[23]	8493	1			T93	1		T538	14		T834	1
values[24]	8383	1			T93	2		T538	12		T834	2
values[25]	8060	1			T93	3		T538	8		T834	1
values[26]	7553	1			T93	2		T538	11		T834	2
values[27]	7317	1			T93	2		T538	7		T834	2
values[28]	6887	1			T93	1		T538	10		T834	1
values[29]	6232	1			T93	2		T538	14		T834	1
values[30]	6035	1			T93	9		T538	9		T834	1
values[31]	5546	1			T93	1		T538	8		T834	1
values[32]	5020	1			T93	1		T538	15		T834	1
values[33]	4724	1			T93	2		T538	9		T834	1
values[34]	4367	1			T93	1		T538	10		T834	1
values[35]	4028	1			T93	3		T538	8		T834	2
values[36]	3767	1			T93	3		T538	14		T834	1
values[37]	3665	1			T93	8		T538	6		T834	2
values[38]	3585	1			T93	3		T538	5		T834	1
values[39]	3407	1			T93	3		T538	5		T834	1
values[40]	3450	1			T93	9		T538	6		T834	4
values[41]	3213	1			T93	2		T538	6		T834	1
values[42]	3145	1			T538	18		T834	2		T866	3
values[43]	3090	1			T538	18		T834	2		T866	3
values[44]	2978	1			T538	6		T834	2		T866	3
values[45]	3006	1			T538	6		T834	1		T866	3
values[46]	2915	1			T538	6		T834	1		T866	3
values[47]	2811	1			T538	9		T834	1		T866	3
values[48]	2762	1			T538	8		T834	1		T866	3
values[49]	2729	1			T538	6		T834	1		T866	3
values[50]	2685	1			T538	10		T834	3		T866	3
values[51]	2676	1			T538	10		T834	1		T866	3
values[52]	2586	1			T538	8		T834	4		T866	3
values[53]	2576	1			T538	14		T834	8		T866	3
values[54]	2471	1			T538	7		T834	2		T866	3
values[55]	2446	1			T538	3		T834	1		T866	3
values[56]	2396	1			T538	4		T834	4		T866	3
values[57]	2306	1			T538	3		T834	1		T866	3
values[58]	2329	1			T538	9		T834	3		T866	3
values[59]	2344	1			T538	4		T834	2		T866	3
values[60]	2289	1			T538	4		T834	2		T866	3
values[61]	2510	1			T538	5		T834	4		T866	3
values[62]	3643	1			T538	5		T834	10		T866	3
values[63]	9185	1			T538	22		T834	21		T866	3
values[64]	233522	1			T538	124		T834	91		T866	513

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4794321	1			T91	132		T92	86		T93	168
values[2]	804977	1			T91	37		T92	14		T93	38
values[3]	82416	1			T93	1		T97	21		T98	4
values[4]	14979	1			T97	3		T98	1		T272	1
values[5]	5858	1			T273	1		T565	1		T651	2
values[6]	3602	1			T651	1		T866	1		T568	3
values[7]	2702	1			T651	1		T835	82		T682	7
values[8]	2321	1			T835	54		T682	7		T873	1
values[9]	1966	1			T835	49		T682	6		T836	2
values[10]	1707	1			T835	48		T682	17		T836	1
values[11]	1579	1			T835	55		T682	27		T836	1
values[12]	1427	1			T835	71		T682	34		T836	3
values[13]	1331	1			T835	50		T682	32		T836	2
values[14]	1237	1			T835	28		T682	30		T836	1
values[15]	1082	1			T835	19		T682	28		T836	2
values[16]	1033	1			T835	14		T682	15		T836	2
values[17]	1034	1			T835	6		T682	18		T836	1
values[18]	930	1			T835	5		T682	25		T836	1
values[19]	833	1			T835	8		T682	12		T836	1
values[20]	769	1			T835	2		T836	1		T850	1
values[21]	793	1			T835	6		T836	1		T850	1
values[22]	777	1			T835	10		T836	1		T850	1
values[23]	760	1			T835	8		T836	1		T850	1
values[24]	714	1			T835	6		T836	2		T850	1
values[25]	682	1			T835	2		T836	2		T850	1
values[26]	637	1			T835	8		T836	4		T850	1
values[27]	611	1			T835	14		T836	4		T850	1
values[28]	607	1			T835	16		T836	1		T850	1
values[29]	609	1			T835	6		T836	3		T850	1
values[30]	545	1			T835	4		T836	7		T850	1
values[31]	606	1			T835	2		T836	4		T850	1
values[32]	586	1			T836	1		T850	1		T500	1
values[33]	556	1			T836	1		T850	1		T500	1
values[34]	501	1			T836	2		T850	1		T500	1
values[35]	528	1			T836	2		T850	1		T500	4
values[36]	561	1			T836	3		T850	1		T500	1
values[37]	540	1			T836	1		T850	1		T500	1
values[38]	494	1			T836	1		T850	1		T500	1
values[39]	445	1			T836	3		T850	1		T500	2
values[40]	436	1			T836	2		T850	1		T500	1
values[41]	456	1			T836	1		T850	1		T500	1
values[42]	444	1			T836	2		T850	1		T500	2
values[43]	412	1			T836	3		T850	1		T500	6
values[44]	407	1			T836	1		T850	1		T500	1
values[45]	448	1			T836	2		T850	1		T500	1
values[46]	441	1			T836	2		T850	1		T500	1
values[47]	422	1			T836	1		T850	1		T500	2
values[48]	422	1			T836	1		T850	1		T500	1
values[49]	418	1			T836	1		T850	1		T500	4
values[50]	396	1			T836	1		T850	1		T500	4
values[51]	382	1			T836	1		T850	1		T500	2
values[52]	365	1			T836	2		T850	1		T500	4
values[53]	382	1			T836	3		T850	1		T500	3
values[54]	390	1			T836	2		T850	1		T500	2
values[55]	395	1			T836	2		T850	1		T500	3
values[56]	365	1			T836	2		T850	1		T500	2
values[57]	341	1			T836	1		T850	1		T500	4
values[58]	342	1			T836	2		T850	1		T500	1
values[59]	334	1			T836	1		T850	1		T500	3
values[60]	363	1			T836	1		T850	1		T500	1
values[61]	410	1			T836	4		T850	1		T500	1
values[62]	662	1			T836	7		T850	1		T500	1
values[63]	2212	1			T836	28		T850	2		T500	2
values[64]	25949	1			T836	104		T850	173		T500	163

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	560347	1			T91	2		T92	1		T93	1
values[2]	2705420	1			T91	99		T92	97		T93	5
values[3]	1191256	1			T91	30		T92	49		T93	9
values[4]	139852	1			T93	7		T97	11		T272	1
values[5]	68980	1			T93	6		T468	2		T565	5
values[6]	44422	1			T93	7		T538	148		T510	24
values[7]	32355	1			T93	10		T538	76		T510	14
values[8]	25715	1			T93	5		T538	70		T510	12
values[9]	21668	1			T93	2		T538	68		T510	18
values[10]	19136	1			T93	9		T538	51		T510	21
values[11]	17502	1			T93	12		T538	33		T510	17
values[12]	16071	1			T93	7		T538	16		T510	20
values[13]	15173	1			T93	2		T538	22		T510	33
values[14]	14450	1			T93	2		T538	21		T510	16
values[15]	13756	1			T93	13		T538	38		T510	15
values[16]	12919	1			T93	17		T538	19		T510	14
values[17]	12519	1			T93	5		T538	21		T510	17
values[18]	12033	1			T93	3		T538	32		T510	7
values[19]	11617	1			T93	5		T538	30		T510	9
values[20]	10992	1			T93	4		T538	26		T510	10
values[21]	10574	1			T93	8		T538	13		T510	12
values[22]	10220	1			T93	3		T538	28		T510	20
values[23]	9855	1			T93	7		T538	36		T510	9
values[24]	9499	1			T93	8		T538	30		T510	2
values[25]	8948	1			T538	30		T834	1		T866	3
values[26]	8753	1			T538	17		T834	1		T866	3
values[27]	8068	1			T538	20		T834	1		T866	3
values[28]	7670	1			T538	23		T834	1		T866	3
values[29]	7053	1			T538	17		T834	2		T866	3
values[30]	6823	1			T538	30		T834	3		T866	3
values[31]	6373	1			T538	19		T834	8		T866	3
values[32]	5848	1			T538	16		T834	6		T866	3
values[33]	5504	1			T538	19		T834	1		T866	3
values[34]	5052	1			T538	13		T834	5		T866	3
values[35]	4753	1			T538	9		T834	8		T866	3
values[36]	4494	1			T538	8		T834	7		T866	3
values[37]	4181	1			T538	7		T834	2		T866	3
values[38]	3994	1			T538	3		T834	3		T866	3
values[39]	3832	1			T538	2		T834	1		T866	3
values[40]	3731	1			T538	6		T834	1		T866	3
values[41]	3617	1			T538	3		T834	3		T866	3
values[42]	3465	1			T538	6		T834	1		T866	3
values[43]	3325	1			T538	9		T834	6		T866	3
values[44]	3288	1			T538	4		T834	2		T866	3
values[45]	3182	1			T538	3		T834	2		T866	3
values[46]	3208	1			T538	3		T834	10		T866	3
values[47]	3179	1			T538	4		T834	10		T866	3
values[48]	3062	1			T538	8		T834	6		T866	3
values[49]	3032	1			T538	5		T834	2		T866	3
values[50]	2997	1			T538	3		T834	2		T866	4
values[51]	2990	1			T538	4		T834	1		T866	3
values[52]	2902	1			T538	7		T834	1		T866	3
values[53]	2699	1			T538	6		T834	4		T866	3
values[54]	2751	1			T538	6		T834	3		T866	3
values[55]	2654	1			T538	9		T834	3		T866	3
values[56]	2648	1			T538	7		T834	1		T866	3
values[57]	2708	1			T538	2		T834	3		T866	3
values[58]	2691	1			T538	3		T834	3		T866	3
values[59]	2586	1			T538	4		T834	5		T866	3
values[60]	2580	1			T538	8		T834	5		T866	3
values[61]	2694	1			T538	7		T834	4		T866	3
values[62]	3536	1			T538	8		T834	2		T866	4
values[63]	8174	1			T538	22		T834	5		T866	4
values[64]	225942	1			T538	40		T834	17		T866	485