Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1693068	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36883381

1

T1

350

T2

3395

T3

5094

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	26335142	1			T1	175		T2	727		T3	1723
values[0x0]	10740228	1			T1	175		T2	2668		T3	3371
values[0x1]	1501079	1			T1	3		T2	80		T3	167

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	407895	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38168554

1

T1

353

T2

3475

T3

5261

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18408174	1			T1	177		T2	1738		T3	2631
valid_sources[0x01]	18408170	1			T1	176		T2	1737		T3	2630
valid_sources[0x02]	28785	1			T231	1		T414	1		T415	1
valid_sources[0x03]	28206	1			T414	8		T920	13		T169	135
valid_sources[0x04]	28124	1			T920	3		T169	187		T569	9
valid_sources[0x05]	27548	1			T231	1		T414	7		T920	6
valid_sources[0x06]	30882	1			T40	2		T70	4		T231	1
valid_sources[0x07]	28147	1			T40	8		T231	1		T414	8
valid_sources[0x08]	27452	1			T231	1		T414	1		T415	2
valid_sources[0x09]	28608	1			T40	2		T414	3		T415	2
valid_sources[0x0a]	29052	1			T414	10		T920	13		T169	153
valid_sources[0x0b]	27836	1			T414	2		T415	1		T920	16
valid_sources[0x0c]	28094	1			T70	5		T414	9		T920	13
valid_sources[0x0d]	27674	1			T231	3		T414	3		T920	17
valid_sources[0x0e]	27915	1			T231	2		T414	2		T920	3
valid_sources[0x0f]	29026	1			T231	1		T414	8		T920	17
valid_sources[0x10]	28625	1			T231	1		T414	7		T415	1
valid_sources[0x11]	27565	1			T231	1		T414	4		T415	3
valid_sources[0x12]	28274	1			T230	39		T231	1		T414	6
valid_sources[0x13]	27737	1			T231	2		T414	5		T920	9
valid_sources[0x14]	28176	1			T414	6		T920	8		T169	167
valid_sources[0x15]	27740	1			T231	3		T414	3		T920	15
valid_sources[0x16]	28391	1			T414	8		T920	17		T169	192
valid_sources[0x17]	27880	1			T231	1		T414	6		T415	1
valid_sources[0x18]	28057	1			T95	39		T414	7		T415	2
valid_sources[0x19]	35760	1			T414	9		T920	12		T169	169
valid_sources[0x1a]	27939	1			T414	6		T415	1		T920	8
valid_sources[0x1b]	31836	1			T40	1		T70	1		T231	1
valid_sources[0x1c]	28056	1			T70	5		T414	8		T920	13
valid_sources[0x1d]	28594	1			T231	1		T414	12		T415	456
valid_sources[0x1e]	28147	1			T231	1		T414	7		T920	5
valid_sources[0x1f]	27618	1			T70	7		T231	1		T414	6
valid_sources[0x20]	27855	1			T70	2		T414	6		T920	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25928110

1

T1

175

T2

727

T3

1723

values[0x0]

all_enables

biggest_size

10689092

1

T1

175

T2

2668

T3

3371

values[0x1]

all_enables

biggest_size

266179

1

T40

16

T95

22

T96

24

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2947630	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

466484

1

T91

22

T92

21

T93

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1154890	1			T91	43		T92	49		T93	66
values[0x0]	1102795	1			T91	45		T92	50		T93	50
values[0x1]	1156429	1			T91	50		T92	41		T93	54

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2282414	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1131700

1

T91

48

T92

46

T93

53

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53478	1			T91	1		T93	2		T97	20
valid_sources[0x01]	52169	1			T91	5		T92	1		T93	4
valid_sources[0x02]	53240	1			T92	12		T93	1		T97	12
valid_sources[0x03]	53431	1			T91	6		T97	2		T98	10
valid_sources[0x04]	54850	1			T91	8		T93	4		T97	3
valid_sources[0x05]	53455	1			T91	2		T92	2		T93	1
valid_sources[0x06]	53655	1			T91	1		T92	4		T93	5
valid_sources[0x07]	54214	1			T91	2		T93	1		T97	5
valid_sources[0x08]	52944	1			T91	4		T93	4		T97	20
valid_sources[0x09]	52739	1			T91	5		T93	2		T97	1
valid_sources[0x0a]	52514	1			T91	6		T92	4		T93	2
valid_sources[0x0b]	52587	1			T91	1		T92	6		T93	3
valid_sources[0x0c]	53774	1			T91	5		T93	1		T97	15
valid_sources[0x0d]	51670	1			T91	1		T92	1		T93	4
valid_sources[0x0e]	54197	1			T92	1		T93	2		T97	2
valid_sources[0x0f]	53401	1			T93	2		T97	8		T98	13
valid_sources[0x10]	52813	1			T91	6		T92	11		T93	5
valid_sources[0x11]	52270	1			T92	2		T93	3		T97	2
valid_sources[0x12]	53438	1			T93	6		T97	13		T98	11
valid_sources[0x13]	53872	1			T93	4		T97	6		T98	17
valid_sources[0x14]	53537	1			T91	3		T93	4		T97	6
valid_sources[0x15]	52746	1			T97	5		T98	8		T467	14
valid_sources[0x16]	53761	1			T91	2		T92	3		T97	15
valid_sources[0x17]	52942	1			T91	2		T93	1		T97	7
valid_sources[0x18]	53485	1			T92	6		T93	5		T97	10
valid_sources[0x19]	53252	1			T92	7		T93	2		T97	6
valid_sources[0x1a]	53415	1			T91	1		T93	3		T97	4
valid_sources[0x1b]	52896	1			T91	2		T92	3		T93	1
valid_sources[0x1c]	53747	1			T91	2		T92	1		T93	3
valid_sources[0x1d]	53301	1			T91	1		T92	1		T93	3
valid_sources[0x1e]	52928	1			T91	1		T93	2		T97	16
valid_sources[0x1f]	53824	1			T91	4		T93	2		T97	6
valid_sources[0x20]	53048	1			T91	2		T93	4		T97	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49377

1

T91

3

T92

2

T93

3

values[0x0]

all_enables

biggest_size

368703

1

T91

19

T92

19

T93

17

values[0x1]

all_enables

biggest_size

48404

1

T93

1

T97

7

T98

11

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3150224	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

512090

1

T91

13

T92

9

T93

28

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1252722	1			T91	71		T92	29		T93	62
values[0x0]	1155352	1			T91	39		T92	31		T93	57
values[0x1]	1254240	1			T91	59		T92	40		T93	88

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2418321	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1243993

1

T91

49

T92

31

T93

64

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	57492	1			T91	2		T92	3		T97	4
valid_sources[0x01]	56551	1			T91	5		T97	12		T98	23
valid_sources[0x02]	56554	1			T91	6		T92	4		T97	4
valid_sources[0x03]	57826	1			T91	1		T92	3		T97	8
valid_sources[0x04]	58261	1			T91	4		T92	2		T93	1
valid_sources[0x05]	56296	1			T91	5		T93	2		T97	7
valid_sources[0x06]	56846	1			T91	2		T97	8		T98	22
valid_sources[0x07]	57536	1			T91	2		T97	3		T98	25
valid_sources[0x08]	58176	1			T97	3		T98	9		T467	15
valid_sources[0x09]	57287	1			T91	3		T92	2		T93	1
valid_sources[0x0a]	57475	1			T91	2		T92	1		T97	5
valid_sources[0x0b]	57081	1			T91	4		T97	6		T98	3
valid_sources[0x0c]	58572	1			T97	6		T98	13		T162	10
valid_sources[0x0d]	56650	1			T91	7		T93	6		T97	12
valid_sources[0x0e]	56909	1			T91	1		T92	3		T97	4
valid_sources[0x0f]	58925	1			T97	5		T274	3		T273	2
valid_sources[0x10]	55532	1			T91	3		T92	2		T97	3
valid_sources[0x11]	57085	1			T91	8		T92	1		T97	10
valid_sources[0x12]	58788	1			T91	4		T97	5		T98	14
valid_sources[0x13]	57116	1			T91	1		T97	3		T98	8
valid_sources[0x14]	56890	1			T91	7		T93	15		T97	9
valid_sources[0x15]	56694	1			T91	5		T93	10		T97	6
valid_sources[0x16]	57365	1			T91	4		T92	3		T97	6
valid_sources[0x17]	56407	1			T91	5		T97	6		T467	15
valid_sources[0x18]	57543	1			T91	3		T92	1		T97	1
valid_sources[0x19]	57125	1			T91	3		T97	8		T98	8
valid_sources[0x1a]	57249	1			T91	2		T97	4		T98	4
valid_sources[0x1b]	57309	1			T91	3		T97	3		T98	16
valid_sources[0x1c]	57189	1			T91	1		T92	4		T97	6
valid_sources[0x1d]	56991	1			T91	2		T93	65		T97	6
valid_sources[0x1e]	56871	1			T93	13		T97	5		T273	3
valid_sources[0x1f]	56805	1			T91	1		T97	5		T98	10
valid_sources[0x20]	56259	1			T91	1		T97	6		T98	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

53908

1

T91

4

T93

4

T97

6

values[0x0]

all_enables

biggest_size

404474

1

T91

9

T92

9

T93

21

values[0x1]

all_enables

biggest_size

53708

1

T93

3

T97

6

T98

14

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2967445	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

470479

1

T91

19

T92

16

T93

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1163247	1			T91	43		T92	48		T93	57
values[0x0]	1111515	1			T91	43		T92	45		T93	59
values[0x1]	1163162	1			T91	45		T92	54		T93	41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2297063	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1140861

1

T91

42

T92

37

T93

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54458	1			T91	2		T93	3		T97	10
valid_sources[0x01]	53706	1			T91	1		T93	1		T97	10
valid_sources[0x02]	53588	1			T92	18		T93	3		T97	9
valid_sources[0x03]	53538	1			T92	2		T93	4		T97	5
valid_sources[0x04]	54084	1			T91	4		T93	3		T97	5
valid_sources[0x05]	53549	1			T91	1		T93	2		T97	5
valid_sources[0x06]	54181	1			T91	7		T93	4		T97	5
valid_sources[0x07]	54882	1			T91	2		T93	2		T97	10
valid_sources[0x08]	54311	1			T91	1		T93	3		T97	8
valid_sources[0x09]	52627	1			T91	2		T92	4		T93	1
valid_sources[0x0a]	53262	1			T91	1		T93	1		T97	7
valid_sources[0x0b]	53078	1			T91	2		T92	3		T93	3
valid_sources[0x0c]	54543	1			T91	5		T93	3		T97	10
valid_sources[0x0d]	53245	1			T93	2		T97	6		T98	24
valid_sources[0x0e]	54038	1			T91	2		T92	10		T93	1
valid_sources[0x0f]	53716	1			T91	2		T93	2		T97	11
valid_sources[0x10]	53572	1			T91	3		T93	2		T97	8
valid_sources[0x11]	53272	1			T91	2		T93	4		T97	11
valid_sources[0x12]	53564	1			T91	2		T92	35		T97	8
valid_sources[0x13]	53694	1			T92	4		T93	4		T97	7
valid_sources[0x14]	52990	1			T91	2		T93	2		T97	4
valid_sources[0x15]	53160	1			T91	3		T93	2		T97	8
valid_sources[0x16]	54587	1			T91	1		T92	4		T93	2
valid_sources[0x17]	52669	1			T91	1		T93	2		T97	9
valid_sources[0x18]	53508	1			T91	3		T92	1		T93	2
valid_sources[0x19]	53475	1			T93	5		T97	6		T98	15
valid_sources[0x1a]	54689	1			T93	1		T97	7		T98	12
valid_sources[0x1b]	53884	1			T91	2		T93	1		T97	2
valid_sources[0x1c]	53561	1			T93	1		T97	11		T98	17
valid_sources[0x1d]	53224	1			T91	4		T93	5		T97	5
valid_sources[0x1e]	53698	1			T91	2		T93	3		T97	7
valid_sources[0x1f]	53579	1			T91	1		T93	3		T97	10
valid_sources[0x20]	53648	1			T91	1		T93	1		T97	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49212

1

T91

1

T92

1

T97

10

values[0x0]

all_enables

biggest_size

372207

1

T91

18

T92

13

T93

15

values[0x1]

all_enables

biggest_size

49060

1

T92

2

T93

3

T97

8