Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	520052953	64958322	0	0
DataKnown_AKnownEnable	520052953	519948669	0	0
DepthKnown_A	520052953	519948669	0	0
RvalidKnown_A	520052953	519948669	0	0
WreadyKnown_A	520052953	519948669	0	0
gen_passthru_fifo.paramCheckPass	1015	1015	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520052953	64958322	0	0
T1	42219	3485	0	0
T2	65997	7006	0	0
T3	71291	8442	0	0
T4	93260	10464	0	0
T5	96811	57233	0	0
T6	127653	16873	0	0
T8	92025	9850	0	0
T25	193688	23450	0	0
T102	66235	6440	0	0
T103	83457	8689	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	520052953	519948669	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520052953	519948669	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520052953	519948669	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520052953	519948669	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1015	1015	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T25	1	1	0	0
T102	1	1	0	0
T103	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         0/1     ==>      assign wready_o = rready_i;
49         0/1     ==>      assign full_o = rready_i;
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	520052953	47218640	0	0
DataKnown_AKnownEnable	520052953	519948669	0	0
DepthKnown_A	520052953	519948669	0	0
RvalidKnown_A	520052953	519948669	0	0
WreadyKnown_A	520052953	519948669	0	0
gen_passthru_fifo.paramCheckPass	1015	1015	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520052953	47218640	0	0
T1	42219	1880	0	0
T2	65997	4882	0	0
T3	71291	5903	0	0
T4	93260	8043	0	0
T5	96811	28216	0	0
T6	127653	11396	0	0
T8	92025	7323	0	0
T25	193688	18414	0	0
T102	66235	4765	0	0
T103	83457	7019	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	520052953	519948669	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520052953	519948669	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520052953	519948669	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520052953	519948669	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1015	1015	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T25	1	1	0	0
T102	1	1	0	0
T103	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	520052953	44769687	0	0
DataKnown_AKnownEnable	520052953	519948669	0	0
DepthKnown_A	520052953	519948669	0	0
RvalidKnown_A	520052953	519948669	0	0
WreadyKnown_A	520052953	519948669	0	0
gen_passthru_fifo.paramCheckPass	1015	1015	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520052953	44769687	0	0
T1	42219	461	0	0
T2	65997	3601	0	0
T3	71291	5436	0	0
T4	93260	5034	0	0
T5	96811	6657	0	0
T6	127653	8935	0	0
T8	92025	7737	0	0
T25	193688	13227	0	0
T102	66235	3843	0	0
T103	83457	5484	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	520052953	519948669	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520052953	519948669	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520052953	519948669	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520052953	519948669	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1015	1015	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T25	1	1	0	0
T102	1	1	0	0
T103	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T40 T95 T96 
49         1/1              assign full_o = rready_i;
           Tests:       T40 T95 T96 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	520052953	36826989	0	0
DataKnown_AKnownEnable	520052953	519948669	0	0
DepthKnown_A	520052953	519948669	0	0
RvalidKnown_A	520052953	519948669	0	0
WreadyKnown_A	520052953	519948669	0	0
gen_passthru_fifo.paramCheckPass	1015	1015	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520052953	36826989	0	0
T1	42219	353	0	0
T2	65997	3475	0	0
T3	71291	5261	0	0
T4	93260	4900	0	0
T5	96811	6036	0	0
T6	127653	8470	0	0
T8	92025	7283	0	0
T25	193688	12962	0	0
T102	66235	3730	0	0
T103	83457	5370	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	520052953	519948669	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520052953	519948669	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520052953	519948669	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520052953	519948669	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1015	1015	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T25	1	1	0	0
T102	1	1	0	0
T103	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	587217096	86984	0	0
DataKnown_AKnownEnable	587217096	587096521	0	0
DepthKnown_A	587217096	587096521	0	0
RvalidKnown_A	587217096	587096521	0	0
WreadyKnown_A	587217096	587096521	0	0
gen_passthru_fifo.paramCheckPass	2923	2923	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	86984	0	0
T1	42219	8	0	0
T2	65997	13	0	0
T3	71291	24	0	0
T4	93260	13	0	0
T5	96811	34	0	0
T6	127653	59	0	0
T8	92025	208	0	0
T25	193688	35	0	0
T102	66235	13	0	0
T103	83457	13	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2923	2923	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T25	1	1	0	0
T102	1	1	0	0
T103	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	587217096	90055	0	0
DataKnown_AKnownEnable	587217096	587096521	0	0
DepthKnown_A	587217096	587096521	0	0
RvalidKnown_A	587217096	587096521	0	0
WreadyKnown_A	587217096	587096521	0	0
gen_passthru_fifo.paramCheckPass	2923	2923	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	90055	0	0
T1	42219	8	0	0
T2	65997	13	0	0
T3	71291	24	0	0
T4	93260	13	0	0
T5	96811	34	0	0
T6	127653	59	0	0
T8	92025	208	0	0
T25	193688	35	0	0
T102	66235	13	0	0
T103	83457	13	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2923	2923	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T25	1	1	0	0
T102	1	1	0	0
T103	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	587217096	50521	0	0
DataKnown_AKnownEnable	587217096	587096521	0	0
DepthKnown_A	587217096	587096521	0	0
RvalidKnown_A	587217096	587096521	0	0
WreadyKnown_A	587217096	587096521	0	0
gen_passthru_fifo.paramCheckPass	2923	2923	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	50521	0	0
T1	42219	8	0	0
T2	65997	12	0	0
T3	71291	23	0	0
T4	93260	12	0	0
T5	96811	31	0	0
T6	127653	56	0	0
T8	92025	205	0	0
T25	193688	31	0	0
T102	66235	12	0	0
T103	83457	12	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2923	2923	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T25	1	1	0	0
T102	1	1	0	0
T103	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	587217096	50521	0	0
DataKnown_AKnownEnable	587217096	587096521	0	0
DepthKnown_A	587217096	587096521	0	0
RvalidKnown_A	587217096	587096521	0	0
WreadyKnown_A	587217096	587096521	0	0
gen_passthru_fifo.paramCheckPass	2923	2923	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	50521	0	0
T1	42219	8	0	0
T2	65997	12	0	0
T3	71291	23	0	0
T4	93260	12	0	0
T5	96811	31	0	0
T6	127653	56	0	0
T8	92025	205	0	0
T25	193688	31	0	0
T102	66235	12	0	0
T103	83457	12	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2923	2923	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T25	1	1	0	0
T102	1	1	0	0
T103	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T2 T3 T4 
49         1/1              assign full_o = rready_i;
           Tests:       T2 T3 T4 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	587217096	36463	0	0
DataKnown_AKnownEnable	587217096	587096521	0	0
DepthKnown_A	587217096	587096521	0	0
RvalidKnown_A	587217096	587096521	0	0
WreadyKnown_A	587217096	587096521	0	0
gen_passthru_fifo.paramCheckPass	2923	2923	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	36463	0	0
T2	65997	1	0	0
T3	71291	1	0	0
T4	93260	1	0	0
T5	96811	3	0	0
T6	127653	3	0	0
T7	104030	3	0	0
T8	92025	3	0	0
T25	193688	4	0	0
T102	66235	1	0	0
T103	83457	1	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2923	2923	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T25	1	1	0	0
T102	1	1	0	0
T103	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T2 T3 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T2 T3 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	587217096	39534	0	0
DataKnown_AKnownEnable	587217096	587096521	0	0
DepthKnown_A	587217096	587096521	0	0
RvalidKnown_A	587217096	587096521	0	0
WreadyKnown_A	587217096	587096521	0	0
gen_passthru_fifo.paramCheckPass	2923	2923	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	39534	0	0
T2	65997	1	0	0
T3	71291	1	0	0
T4	93260	1	0	0
T5	96811	3	0	0
T6	127653	3	0	0
T7	104030	3	0	0
T8	92025	3	0	0
T25	193688	4	0	0
T102	66235	1	0	0
T103	83457	1	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	587217096	587096521	0	0
T1	42219	42164	0	0
T2	65997	65946	0	0
T3	71291	71240	0	0
T4	93260	93202	0	0
T5	96811	96756	0	0
T6	127653	127591	0	0
T8	92025	91974	0	0
T25	193688	193583	0	0
T102	66235	66180	0	0
T103	83457	83395	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2923	2923	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T25	1	1	0	0
T102	1	1	0	0
T103	1	1	0	0