Module Definition
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Module : tlul_adapter_host
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.09 91.11 75.79 89.44 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex 87.26 90.91 69.23 88.89 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex 90.91 91.30 82.35 90.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.26 90.91 69.23 88.89 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.90 90.48 72.22 88.89 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.74 96.47 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cmd_intg_gen 94.12 88.24 100.00
u_rsp_chk 93.33 100.00 80.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.91 91.30 82.35 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.79 95.35 81.82 90.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.74 96.47 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cmd_intg_gen 100.00 100.00 100.00
u_rsp_chk 93.33 100.00 80.00 100.00

Line Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Line Coverage for Module self-instances :
SCORELINE
90.91 91.30
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

Line No.TotalCoveredPercent
TOTAL232191.30
ALWAYS7033100.00
ALWAYS7855100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
ALWAYS1324375.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN149100.00
CONT_ASSIGN15311100.00
ALWAYS16800
ALWAYS17800


69                          always_ff @(posedge clk_i or negedge rst_ni) begin
70         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
71         1/1                  source_q <= '0;
           Tests:       T1 T2 T3 
72                            end else begin
73         1/1                  source_q <= source_d;
           Tests:       T1 T2 T3 
74                            end
75                          end
76                      
77                          always_comb begin
78         1/1                source_d = source_q;
           Tests:       T1 T2 T3 
79                      
80         1/1                if (req_i && gnt_o) begin
           Tests:       T1 T2 T3 
81         1/1                  if (source_q == MaxSource[ReqNumW-1:0]) begin
           Tests:       T1 T2 T3 
82         1/1                    source_d = '0;
           Tests:       T1 T2 T3 
83                              end else  begin
84         1/1                    source_d = source_q + ReqNumOne;
           Tests:       T1 T2 T3 
85                              end
86                            end
                        MISSING_ELSE
87                          end
88                      
89         1/1              assign tl_source = top_pkg::TL_AIW'(source_q);
           Tests:       T1 T2 T3 
90                        end
91                      
92                        // For TL-UL Get opcode all active bytes must have their mask bit set, so all reads get all tl_be
93                        // bits set. For writes the supplied be_i is used as the mask.
94         1/1            assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign tl_out = '{
           Tests:       T1 T2 T3 
97                          a_valid:   req_i,
98                          a_opcode:  (~we_i) ? Get           :
99                                     (&be_i) ? PutFullData   :
100                                              PutPartialData,
101                         a_param:   3'h0,
102                         a_size:    top_pkg::TL_SZW'(WordSize),
103                         a_mask:    tl_be,
104                         a_source:  tl_source,
105                         a_address: {addr_i[31:WordSize], {WordSize{1'b0}}},
106                         a_data:    wdata_i,
107                         a_user:    '{default: '0, data_intg: wdata_intg_i, instr_type: instr_type_i},
108                         d_ready:   1'b1
109                       };
110                     
111                       tlul_cmd_intg_gen #(.EnableDataIntgGen (EnableDataIntgGen)) u_cmd_intg_gen (
112                         .tl_i(tl_out),
113                         .tl_o(tl_o)
114                       );
115                     
116        1/1            assign gnt_o        = tl_i.a_ready;
           Tests:       T1 T2 T3 
117                     
118        1/1            assign valid_o      = tl_i.d_valid;
           Tests:       T1 T2 T3 
119        1/1            assign rdata_o      = tl_i.d_data;
           Tests:       T1 T2 T3 
120        1/1            assign rdata_intg_o = tl_i.d_user.data_intg;
           Tests:       T1 T2 T3 
121                     
122                       logic intg_err;
123                       tlul_rsp_intg_chk #(
124                         .EnableRspDataIntgCheck(EnableRspDataIntgCheck)
125                       ) u_rsp_chk (
126                         .tl_i,
127                         .err_o(intg_err)
128                       );
129                     
130                       logic intg_err_q;
131                       always_ff @(posedge clk_i or negedge rst_ni) begin
132        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
133        1/1                intg_err_q <= '0;
           Tests:       T1 T2 T3 
134        1/1              end else if (intg_err) begin
           Tests:       T1 T2 T3 
135        0/1     ==>        intg_err_q <= 1'b1;
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // err_o is transactional.  This allows the host to continue
140                       // debug without receiving an endless stream of errors.
141        1/1            assign err_o   = tl_i.d_error | intg_err;
           Tests:       T1 T2 T3 
142                     
143                       // intg_err_o is permanent once detected, and should be used
144                       // to trigger alerts
145        1/1            assign intg_err_o = intg_err_q | intg_err;
           Tests:       T1 T2 T3 
146                     
147                       // Addresses are assumed to be word-aligned, and the bottom bits are ignored
148                       logic unused_addr_bottom_bits;
149        0/1     ==>    assign unused_addr_bottom_bits = ^addr_i[WordSize-1:0];
150                     
151                       // Explicitly ignore unused fields of tl_i
152                       logic unused_tl_i_fields;
153        1/1            assign unused_tl_i_fields = ^{tl_i.d_opcode, tl_i.d_param,
           Tests:       T1 T2 T3 
154                                                     tl_i.d_size, tl_i.d_source, tl_i.d_sink,
155                                                     tl_i.d_user};
156                     
157                     `ifdef INC_ASSERT
158                       //VCS coverage off
159                       // pragma coverage off
160                       localparam int OutstandingReqCntW =
161                         (MAX_REQS == 2 ** $clog2(MAX_REQS)) ? $clog2(MAX_REQS) + 1 : $clog2(MAX_REQS);
162                       localparam logic [OutstandingReqCntW-1:0] OutstandingReqCntOne = OutstandingReqCntW'(1'b1);
163                     
164                       logic [OutstandingReqCntW-1:0] outstanding_reqs_q;
165                       logic [OutstandingReqCntW-1:0] outstanding_reqs_d;
166                     
167                       always_comb begin
168        unreachable      outstanding_reqs_d = outstanding_reqs_q;
169                     
170        unreachable      if ((req_i && gnt_o) && !valid_o) begin
171        unreachable        outstanding_reqs_d = outstanding_reqs_q + OutstandingReqCntOne;
172        unreachable      end else if (!(req_i && gnt_o) && valid_o) begin
173        unreachable        outstanding_reqs_d = outstanding_reqs_q - OutstandingReqCntOne;
174                         end
                   ==>  MISSING_ELSE
175                       end
176                     
177                       always_ff @(posedge clk_i or negedge rst_ni) begin
178        unreachable      if (!rst_ni) begin
179        unreachable        outstanding_reqs_q <= '0;
180                         end else begin
181        unreachable        outstanding_reqs_q <= outstanding_reqs_d;
Line Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Line Coverage for Module self-instances :
SCORELINE
87.26 90.91
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

Line No.TotalCoveredPercent
TOTAL222090.91
ALWAYS7033100.00
ALWAYS7855100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9400
CONT_ASSIGN9611100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
ALWAYS1324375.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN149100.00
CONT_ASSIGN15311100.00
ALWAYS16800
ALWAYS17800


69                          always_ff @(posedge clk_i or negedge rst_ni) begin
70         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
71         1/1                  source_q <= '0;
           Tests:       T1 T2 T3 
72                            end else begin
73         1/1                  source_q <= source_d;
           Tests:       T1 T2 T3 
74                            end
75                          end
76                      
77                          always_comb begin
78         1/1                source_d = source_q;
           Tests:       T1 T2 T3 
79                      
80         1/1                if (req_i && gnt_o) begin
           Tests:       T1 T2 T3 
81         1/1                  if (source_q == MaxSource[ReqNumW-1:0]) begin
           Tests:       T1 T2 T3 
82         1/1                    source_d = '0;
           Tests:       T1 T2 T3 
83                              end else  begin
84         1/1                    source_d = source_q + ReqNumOne;
           Tests:       T1 T2 T3 
85                              end
86                            end
                        MISSING_ELSE
87                          end
88                      
89         1/1              assign tl_source = top_pkg::TL_AIW'(source_q);
           Tests:       T1 T2 T3 
90                        end
91                      
92                        // For TL-UL Get opcode all active bytes must have their mask bit set, so all reads get all tl_be
93                        // bits set. For writes the supplied be_i is used as the mask.
94         unreachable    assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
95                      
96         1/1            assign tl_out = '{
           Tests:       T1 T2 T3 
97                          a_valid:   req_i,
98                          a_opcode:  (~we_i) ? Get           :
99                                     (&be_i) ? PutFullData   :
100                                              PutPartialData,
101                         a_param:   3'h0,
102                         a_size:    top_pkg::TL_SZW'(WordSize),
103                         a_mask:    tl_be,
104                         a_source:  tl_source,
105                         a_address: {addr_i[31:WordSize], {WordSize{1'b0}}},
106                         a_data:    wdata_i,
107                         a_user:    '{default: '0, data_intg: wdata_intg_i, instr_type: instr_type_i},
108                         d_ready:   1'b1
109                       };
110                     
111                       tlul_cmd_intg_gen #(.EnableDataIntgGen (EnableDataIntgGen)) u_cmd_intg_gen (
112                         .tl_i(tl_out),
113                         .tl_o(tl_o)
114                       );
115                     
116        1/1            assign gnt_o        = tl_i.a_ready;
           Tests:       T1 T2 T3 
117                     
118        1/1            assign valid_o      = tl_i.d_valid;
           Tests:       T1 T2 T3 
119        1/1            assign rdata_o      = tl_i.d_data;
           Tests:       T1 T2 T3 
120        1/1            assign rdata_intg_o = tl_i.d_user.data_intg;
           Tests:       T1 T2 T3 
121                     
122                       logic intg_err;
123                       tlul_rsp_intg_chk #(
124                         .EnableRspDataIntgCheck(EnableRspDataIntgCheck)
125                       ) u_rsp_chk (
126                         .tl_i,
127                         .err_o(intg_err)
128                       );
129                     
130                       logic intg_err_q;
131                       always_ff @(posedge clk_i or negedge rst_ni) begin
132        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
133        1/1                intg_err_q <= '0;
           Tests:       T1 T2 T3 
134        1/1              end else if (intg_err) begin
           Tests:       T1 T2 T3 
135        0/1     ==>        intg_err_q <= 1'b1;
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // err_o is transactional.  This allows the host to continue
140                       // debug without receiving an endless stream of errors.
141        1/1            assign err_o   = tl_i.d_error | intg_err;
           Tests:       T1 T2 T3 
142                     
143                       // intg_err_o is permanent once detected, and should be used
144                       // to trigger alerts
145        1/1            assign intg_err_o = intg_err_q | intg_err;
           Tests:       T1 T2 T3 
146                     
147                       // Addresses are assumed to be word-aligned, and the bottom bits are ignored
148                       logic unused_addr_bottom_bits;
149        0/1     ==>    assign unused_addr_bottom_bits = ^addr_i[WordSize-1:0];
150                     
151                       // Explicitly ignore unused fields of tl_i
152                       logic unused_tl_i_fields;
153        1/1            assign unused_tl_i_fields = ^{tl_i.d_opcode, tl_i.d_param,
           Tests:       T1 T2 T3 
154                                                     tl_i.d_size, tl_i.d_source, tl_i.d_sink,
155                                                     tl_i.d_user};
156                     
157                     `ifdef INC_ASSERT
158                       //VCS coverage off
159                       // pragma coverage off
160                       localparam int OutstandingReqCntW =
161                         (MAX_REQS == 2 ** $clog2(MAX_REQS)) ? $clog2(MAX_REQS) + 1 : $clog2(MAX_REQS);
162                       localparam logic [OutstandingReqCntW-1:0] OutstandingReqCntOne = OutstandingReqCntW'(1'b1);
163                     
164                       logic [OutstandingReqCntW-1:0] outstanding_reqs_q;
165                       logic [OutstandingReqCntW-1:0] outstanding_reqs_d;
166                     
167                       always_comb begin
168        unreachable      outstanding_reqs_d = outstanding_reqs_q;
169                     
170        unreachable      if ((req_i && gnt_o) && !valid_o) begin
171        unreachable        outstanding_reqs_d = outstanding_reqs_q + OutstandingReqCntOne;
172        unreachable      end else if (!(req_i && gnt_o) && valid_o) begin
173        unreachable        outstanding_reqs_d = outstanding_reqs_q - OutstandingReqCntOne;
174                         end
                   ==>  MISSING_ELSE
175                       end
176                     
177                       always_ff @(posedge clk_i or negedge rst_ni) begin
178        unreachable      if (!rst_ni) begin
179        unreachable        outstanding_reqs_q <= '0;
180                         end else begin
181        unreachable        outstanding_reqs_q <= outstanding_reqs_d;
Cond Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Cond Coverage for Module self-instances :
SCORECOND
87.26 69.23
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

TotalCoveredPercent
Conditions13969.23
Logical13969.23
Non-Logical00
Event00

 LINE       80
 EXPRESSION (req_i && gnt_o)
             --1--    --2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       81
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0])
            --------------------------------------------1-------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       94
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3 

 LINE       96
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3 

 LINE       96
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----
-1-StatusTests
0Unreachable
1Unreachable 

 LINE       141
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT47,T211,T238 

 LINE       145
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered
Cond Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Cond Coverage for Module self-instances :
SCORECOND
90.91 82.35
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

TotalCoveredPercent
Conditions171482.35
Logical171482.35
Non-Logical00
Event00

 LINE       80
 EXPRESSION (req_i && gnt_o)
             --1--    --2--
-1--2-StatusTests
01CoveredT40,T95,T96
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       81
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       94
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       96
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       96
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       141
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT46,T47,T239 

 LINE       145
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered
Branch Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
90.91 90.00
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

Line No.TotalCoveredPercent
Branches 10 9 90.00
TERNARY 94 2 2 100.00
IF 132 3 2 66.67
IF 70 2 2 100.00
IF 80 3 3 100.00 



94           assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
                                  -1-  
                                  ==>  
                                  ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



132            if (!rst_ni) begin
               -1-  
133              intg_err_q <= '0;
                 ==>
134            end else if (intg_err) begin
                        -2-  
135              intg_err_q <= 1'b1;
                 ==>
136            end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3 



70               if (!rst_ni) begin
                 -1-  
71                 source_q <= '0;
                   ==>
72               end else begin
73                 source_q <= source_d;
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



80               if (req_i && gnt_o) begin
                 -1-  
81                 if (source_q == MaxSource[ReqNumW-1:0]) begin
                   -2-  
82                   source_d = '0;
                     ==>
83                 end else  begin
84                   source_d = source_q + ReqNumOne;
                     ==>
85                 end
86               end
                 MISSING_ELSE
                 ==>

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3

Branch Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Branch Coverage for Module self-instances :
SCOREBRANCH
87.26 88.89
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

Line No.TotalCoveredPercent
Branches 9 8 88.89
TERNARY 94 1 1 100.00
IF 132 3 2 66.67
IF 70 2 2 100.00
IF 80 3 3 100.00 



94           assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
                                  -1-  
                                  ==>  
                                  ==> (Unreachable)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable 



132            if (!rst_ni) begin
               -1-  
133              intg_err_q <= '0;
                 ==>
134            end else if (intg_err) begin
                        -2-  
135              intg_err_q <= 1'b1;
                 ==>
136            end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3 



70               if (!rst_ni) begin
                 -1-  
71                 source_q <= '0;
                   ==>
72               end else begin
73                 source_q <= source_d;
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



80               if (req_i && gnt_o) begin
                 -1-  
81                 if (source_q == MaxSource[ReqNumW-1:0]) begin
                   -2-  
82                   source_d = '0;
                     ==>
83                 end else  begin
84                   source_d = source_q + ReqNumOne;
                     ==>
85                 end
86               end
                 MISSING_ELSE
                 ==>

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3

Assert Coverage for Module : tlul_adapter_host
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DontExceeedMaxReqs 1040105906 109681284 0 0


DontExceeedMaxReqs
NameAttemptsReal SuccessesFailuresIncomplete
Total 1040105906 109681284 0 0
T1 84438 3946 0 0
T2 131994 10607 0 0
T3 142582 13878 0 0
T4 186520 15498 0 0
T5 193622 63890 0 0
T6 255306 25808 0 0
T8 184050 17587 0 0
T25 387376 36677 0 0
T102 132470 10283 0 0
T103 166914 14173 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
Line No.TotalCoveredPercent
TOTAL222090.91
ALWAYS7033100.00
ALWAYS7855100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9400
CONT_ASSIGN9611100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
ALWAYS1324375.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN149100.00
CONT_ASSIGN15311100.00
ALWAYS16800
ALWAYS17800


69                          always_ff @(posedge clk_i or negedge rst_ni) begin
70         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
71         1/1                  source_q <= '0;
           Tests:       T1 T2 T3 
72                            end else begin
73         1/1                  source_q <= source_d;
           Tests:       T1 T2 T3 
74                            end
75                          end
76                      
77                          always_comb begin
78         1/1                source_d = source_q;
           Tests:       T1 T2 T3 
79                      
80         1/1                if (req_i && gnt_o) begin
           Tests:       T1 T2 T3 
81         1/1                  if (source_q == MaxSource[ReqNumW-1:0]) begin
           Tests:       T1 T2 T3 
82         1/1                    source_d = '0;
           Tests:       T1 T2 T3 
83                              end else  begin
84         1/1                    source_d = source_q + ReqNumOne;
           Tests:       T1 T2 T3 
85                              end
86                            end
                        MISSING_ELSE
87                          end
88                      
89         1/1              assign tl_source = top_pkg::TL_AIW'(source_q);
           Tests:       T1 T2 T3 
90                        end
91                      
92                        // For TL-UL Get opcode all active bytes must have their mask bit set, so all reads get all tl_be
93                        // bits set. For writes the supplied be_i is used as the mask.
94         unreachable    assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
95                      
96         1/1            assign tl_out = '{
           Tests:       T1 T2 T3 
97                          a_valid:   req_i,
98                          a_opcode:  (~we_i) ? Get           :
99                                     (&be_i) ? PutFullData   :
100                                              PutPartialData,
101                         a_param:   3'h0,
102                         a_size:    top_pkg::TL_SZW'(WordSize),
103                         a_mask:    tl_be,
104                         a_source:  tl_source,
105                         a_address: {addr_i[31:WordSize], {WordSize{1'b0}}},
106                         a_data:    wdata_i,
107                         a_user:    '{default: '0, data_intg: wdata_intg_i, instr_type: instr_type_i},
108                         d_ready:   1'b1
109                       };
110                     
111                       tlul_cmd_intg_gen #(.EnableDataIntgGen (EnableDataIntgGen)) u_cmd_intg_gen (
112                         .tl_i(tl_out),
113                         .tl_o(tl_o)
114                       );
115                     
116        1/1            assign gnt_o        = tl_i.a_ready;
           Tests:       T1 T2 T3 
117                     
118        1/1            assign valid_o      = tl_i.d_valid;
           Tests:       T1 T2 T3 
119        1/1            assign rdata_o      = tl_i.d_data;
           Tests:       T1 T2 T3 
120        1/1            assign rdata_intg_o = tl_i.d_user.data_intg;
           Tests:       T1 T2 T3 
121                     
122                       logic intg_err;
123                       tlul_rsp_intg_chk #(
124                         .EnableRspDataIntgCheck(EnableRspDataIntgCheck)
125                       ) u_rsp_chk (
126                         .tl_i,
127                         .err_o(intg_err)
128                       );
129                     
130                       logic intg_err_q;
131                       always_ff @(posedge clk_i or negedge rst_ni) begin
132        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
133        1/1                intg_err_q <= '0;
           Tests:       T1 T2 T3 
134        1/1              end else if (intg_err) begin
           Tests:       T1 T2 T3 
135        0/1     ==>        intg_err_q <= 1'b1;
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // err_o is transactional.  This allows the host to continue
140                       // debug without receiving an endless stream of errors.
141        1/1            assign err_o   = tl_i.d_error | intg_err;
           Tests:       T1 T2 T3 
142                     
143                       // intg_err_o is permanent once detected, and should be used
144                       // to trigger alerts
145        1/1            assign intg_err_o = intg_err_q | intg_err;
           Tests:       T1 T2 T3 
146                     
147                       // Addresses are assumed to be word-aligned, and the bottom bits are ignored
148                       logic unused_addr_bottom_bits;
149        0/1     ==>    assign unused_addr_bottom_bits = ^addr_i[WordSize-1:0];
150                     
151                       // Explicitly ignore unused fields of tl_i
152                       logic unused_tl_i_fields;
153        1/1            assign unused_tl_i_fields = ^{tl_i.d_opcode, tl_i.d_param,
           Tests:       T1 T2 T3 
154                                                     tl_i.d_size, tl_i.d_source, tl_i.d_sink,
155                                                     tl_i.d_user};
156                     
157                     `ifdef INC_ASSERT
158                       //VCS coverage off
159                       // pragma coverage off
160                       localparam int OutstandingReqCntW =
161                         (MAX_REQS == 2 ** $clog2(MAX_REQS)) ? $clog2(MAX_REQS) + 1 : $clog2(MAX_REQS);
162                       localparam logic [OutstandingReqCntW-1:0] OutstandingReqCntOne = OutstandingReqCntW'(1'b1);
163                     
164                       logic [OutstandingReqCntW-1:0] outstanding_reqs_q;
165                       logic [OutstandingReqCntW-1:0] outstanding_reqs_d;
166                     
167                       always_comb begin
168        unreachable      outstanding_reqs_d = outstanding_reqs_q;
169                     
170        unreachable      if ((req_i && gnt_o) && !valid_o) begin
171        unreachable        outstanding_reqs_d = outstanding_reqs_q + OutstandingReqCntOne;
172        unreachable      end else if (!(req_i && gnt_o) && valid_o) begin
173        unreachable        outstanding_reqs_d = outstanding_reqs_q - OutstandingReqCntOne;
174                         end
                   ==>  MISSING_ELSE
175                       end
176                     
177                       always_ff @(posedge clk_i or negedge rst_ni) begin
178        unreachable      if (!rst_ni) begin
179        unreachable        outstanding_reqs_q <= '0;
180                         end else begin
181        unreachable        outstanding_reqs_q <= outstanding_reqs_d;
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
TotalCoveredPercent
Conditions13969.23
Logical13969.23
Non-Logical00
Event00

 LINE       80
 EXPRESSION (req_i && gnt_o)
             --1--    --2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       81
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0])
            --------------------------------------------1-------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       94
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3 

 LINE       96
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3 

 LINE       96
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----
-1-StatusTests
0Unreachable
1Unreachable 

 LINE       141
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT47,T211,T238 

 LINE       145
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
Line No.TotalCoveredPercent
Branches 9 8 88.89
TERNARY 94 1 1 100.00
IF 132 3 2 66.67
IF 70 2 2 100.00
IF 80 3 3 100.00 



94           assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
                                  -1-  
                                  ==>  
                                  ==> (Unreachable)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable 



132            if (!rst_ni) begin
               -1-  
133              intg_err_q <= '0;
                 ==>
134            end else if (intg_err) begin
                        -2-  
135              intg_err_q <= 1'b1;
                 ==>
136            end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3 



70               if (!rst_ni) begin
                 -1-  
71                 source_q <= '0;
                   ==>
72               end else begin
73                 source_q <= source_d;
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



80               if (req_i && gnt_o) begin
                 -1-  
81                 if (source_q == MaxSource[ReqNumW-1:0]) begin
                   -2-  
82                   source_d = '0;
                     ==>
83                 end else  begin
84                   source_d = source_q + ReqNumOne;
                     ==>
85                 end
86               end
                 MISSING_ELSE
                 ==>

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DontExceeedMaxReqs 520052953 64958322 0 0


DontExceeedMaxReqs
NameAttemptsReal SuccessesFailuresIncomplete
Total 520052953 64958322 0 0
T1 42219 3485 0 0
T2 65997 7006 0 0
T3 71291 8442 0 0
T4 93260 10464 0 0
T5 96811 57233 0 0
T6 127653 16873 0 0
T8 92025 9850 0 0
T25 193688 23450 0 0
T102 66235 6440 0 0
T103 83457 8689 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
Line No.TotalCoveredPercent
TOTAL232191.30
ALWAYS7033100.00
ALWAYS7855100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
ALWAYS1324375.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN149100.00
CONT_ASSIGN15311100.00
ALWAYS16800
ALWAYS17800


69                          always_ff @(posedge clk_i or negedge rst_ni) begin
70         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
71         1/1                  source_q <= '0;
           Tests:       T1 T2 T3 
72                            end else begin
73         1/1                  source_q <= source_d;
           Tests:       T1 T2 T3 
74                            end
75                          end
76                      
77                          always_comb begin
78         1/1                source_d = source_q;
           Tests:       T1 T2 T3 
79                      
80         1/1                if (req_i && gnt_o) begin
           Tests:       T1 T2 T3 
81         1/1                  if (source_q == MaxSource[ReqNumW-1:0]) begin
           Tests:       T1 T2 T3 
82         1/1                    source_d = '0;
           Tests:       T1 T2 T3 
83                              end else  begin
84         1/1                    source_d = source_q + ReqNumOne;
           Tests:       T1 T2 T3 
85                              end
86                            end
                        MISSING_ELSE
87                          end
88                      
89         1/1              assign tl_source = top_pkg::TL_AIW'(source_q);
           Tests:       T1 T2 T3 
90                        end
91                      
92                        // For TL-UL Get opcode all active bytes must have their mask bit set, so all reads get all tl_be
93                        // bits set. For writes the supplied be_i is used as the mask.
94         1/1            assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
           Tests:       T1 T2 T3 
95                      
96         1/1            assign tl_out = '{
           Tests:       T1 T2 T3 
97                          a_valid:   req_i,
98                          a_opcode:  (~we_i) ? Get           :
99                                     (&be_i) ? PutFullData   :
100                                              PutPartialData,
101                         a_param:   3'h0,
102                         a_size:    top_pkg::TL_SZW'(WordSize),
103                         a_mask:    tl_be,
104                         a_source:  tl_source,
105                         a_address: {addr_i[31:WordSize], {WordSize{1'b0}}},
106                         a_data:    wdata_i,
107                         a_user:    '{default: '0, data_intg: wdata_intg_i, instr_type: instr_type_i},
108                         d_ready:   1'b1
109                       };
110                     
111                       tlul_cmd_intg_gen #(.EnableDataIntgGen (EnableDataIntgGen)) u_cmd_intg_gen (
112                         .tl_i(tl_out),
113                         .tl_o(tl_o)
114                       );
115                     
116        1/1            assign gnt_o        = tl_i.a_ready;
           Tests:       T1 T2 T3 
117                     
118        1/1            assign valid_o      = tl_i.d_valid;
           Tests:       T1 T2 T3 
119        1/1            assign rdata_o      = tl_i.d_data;
           Tests:       T1 T2 T3 
120        1/1            assign rdata_intg_o = tl_i.d_user.data_intg;
           Tests:       T1 T2 T3 
121                     
122                       logic intg_err;
123                       tlul_rsp_intg_chk #(
124                         .EnableRspDataIntgCheck(EnableRspDataIntgCheck)
125                       ) u_rsp_chk (
126                         .tl_i,
127                         .err_o(intg_err)
128                       );
129                     
130                       logic intg_err_q;
131                       always_ff @(posedge clk_i or negedge rst_ni) begin
132        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
133        1/1                intg_err_q <= '0;
           Tests:       T1 T2 T3 
134        1/1              end else if (intg_err) begin
           Tests:       T1 T2 T3 
135        0/1     ==>        intg_err_q <= 1'b1;
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // err_o is transactional.  This allows the host to continue
140                       // debug without receiving an endless stream of errors.
141        1/1            assign err_o   = tl_i.d_error | intg_err;
           Tests:       T1 T2 T3 
142                     
143                       // intg_err_o is permanent once detected, and should be used
144                       // to trigger alerts
145        1/1            assign intg_err_o = intg_err_q | intg_err;
           Tests:       T1 T2 T3 
146                     
147                       // Addresses are assumed to be word-aligned, and the bottom bits are ignored
148                       logic unused_addr_bottom_bits;
149        0/1     ==>    assign unused_addr_bottom_bits = ^addr_i[WordSize-1:0];
150                     
151                       // Explicitly ignore unused fields of tl_i
152                       logic unused_tl_i_fields;
153        1/1            assign unused_tl_i_fields = ^{tl_i.d_opcode, tl_i.d_param,
           Tests:       T1 T2 T3 
154                                                     tl_i.d_size, tl_i.d_source, tl_i.d_sink,
155                                                     tl_i.d_user};
156                     
157                     `ifdef INC_ASSERT
158                       //VCS coverage off
159                       // pragma coverage off
160                       localparam int OutstandingReqCntW =
161                         (MAX_REQS == 2 ** $clog2(MAX_REQS)) ? $clog2(MAX_REQS) + 1 : $clog2(MAX_REQS);
162                       localparam logic [OutstandingReqCntW-1:0] OutstandingReqCntOne = OutstandingReqCntW'(1'b1);
163                     
164                       logic [OutstandingReqCntW-1:0] outstanding_reqs_q;
165                       logic [OutstandingReqCntW-1:0] outstanding_reqs_d;
166                     
167                       always_comb begin
168        unreachable      outstanding_reqs_d = outstanding_reqs_q;
169                     
170        unreachable      if ((req_i && gnt_o) && !valid_o) begin
171        unreachable        outstanding_reqs_d = outstanding_reqs_q + OutstandingReqCntOne;
172        unreachable      end else if (!(req_i && gnt_o) && valid_o) begin
173        unreachable        outstanding_reqs_d = outstanding_reqs_q - OutstandingReqCntOne;
174                         end
                   ==>  MISSING_ELSE
175                       end
176                     
177                       always_ff @(posedge clk_i or negedge rst_ni) begin
178        unreachable      if (!rst_ni) begin
179        unreachable        outstanding_reqs_q <= '0;
180                         end else begin
181        unreachable        outstanding_reqs_q <= outstanding_reqs_d;
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
TotalCoveredPercent
Conditions171482.35
Logical171482.35
Non-Logical00
Event00

 LINE       80
 EXPRESSION (req_i && gnt_o)
             --1--    --2--
-1--2-StatusTests
01CoveredT40,T95,T96
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       81
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       94
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       96
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       96
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       141
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT46,T47,T239 

 LINE       145
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
Line No.TotalCoveredPercent
Branches 10 9 90.00
TERNARY 94 2 2 100.00
IF 132 3 2 66.67
IF 70 2 2 100.00
IF 80 3 3 100.00 



94           assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
                                  -1-  
                                  ==>  
                                  ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



132            if (!rst_ni) begin
               -1-  
133              intg_err_q <= '0;
                 ==>
134            end else if (intg_err) begin
                        -2-  
135              intg_err_q <= 1'b1;
                 ==>
136            end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3 



70               if (!rst_ni) begin
                 -1-  
71                 source_q <= '0;
                   ==>
72               end else begin
73                 source_q <= source_d;
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



80               if (req_i && gnt_o) begin
                 -1-  
81                 if (source_q == MaxSource[ReqNumW-1:0]) begin
                   -2-  
82                   source_d = '0;
                     ==>
83                 end else  begin
84                   source_d = source_q + ReqNumOne;
                     ==>
85                 end
86               end
                 MISSING_ELSE
                 ==>

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DontExceeedMaxReqs 520052953 44722962 0 0


DontExceeedMaxReqs
NameAttemptsReal SuccessesFailuresIncomplete
Total 520052953 44722962 0 0
T1 42219 461 0 0
T2 65997 3601 0 0
T3 71291 5436 0 0
T4 93260 5034 0 0
T5 96811 6657 0 0
T6 127653 8935 0 0
T8 92025 7737 0 0
T25 193688 13227 0 0
T102 66235 3843 0 0
T103 83457 5484 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%