Unified Coverage Report :: Module

Line Coverage for Module : rv_plic_reg_top

	Line No.	Total	Covered	Percent
TOTAL		1560	1560	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	16579	1	1	100.00
CONT_ASSIGN	16593	1	1	100.00
CONT_ASSIGN	16627	1	1	100.00
CONT_ASSIGN	16641	1	1	100.00
ALWAYS	16647	203	203	100.00
CONT_ASSIGN	16852	1	1	100.00
ALWAYS	16856	1	1	100.00
CONT_ASSIGN	17062	1	1	100.00
CONT_ASSIGN	17064	1	1	100.00
CONT_ASSIGN	17065	1	1	100.00
CONT_ASSIGN	17067	1	1	100.00
CONT_ASSIGN	17068	1	1	100.00
CONT_ASSIGN	17070	1	1	100.00
CONT_ASSIGN	17071	1	1	100.00
CONT_ASSIGN	17073	1	1	100.00
CONT_ASSIGN	17074	1	1	100.00
CONT_ASSIGN	17076	1	1	100.00
CONT_ASSIGN	17077	1	1	100.00
CONT_ASSIGN	17079	1	1	100.00
CONT_ASSIGN	17080	1	1	100.00
CONT_ASSIGN	17082	1	1	100.00
CONT_ASSIGN	17083	1	1	100.00
CONT_ASSIGN	17085	1	1	100.00
CONT_ASSIGN	17086	1	1	100.00
CONT_ASSIGN	17088	1	1	100.00
CONT_ASSIGN	17089	1	1	100.00
CONT_ASSIGN	17091	1	1	100.00
CONT_ASSIGN	17092	1	1	100.00
CONT_ASSIGN	17094	1	1	100.00
CONT_ASSIGN	17095	1	1	100.00
CONT_ASSIGN	17097	1	1	100.00
CONT_ASSIGN	17098	1	1	100.00
CONT_ASSIGN	17100	1	1	100.00
CONT_ASSIGN	17101	1	1	100.00
CONT_ASSIGN	17103	1	1	100.00
CONT_ASSIGN	17104	1	1	100.00
CONT_ASSIGN	17106	1	1	100.00
CONT_ASSIGN	17107	1	1	100.00
CONT_ASSIGN	17109	1	1	100.00
CONT_ASSIGN	17110	1	1	100.00
CONT_ASSIGN	17112	1	1	100.00
CONT_ASSIGN	17113	1	1	100.00
CONT_ASSIGN	17115	1	1	100.00
CONT_ASSIGN	17116	1	1	100.00
CONT_ASSIGN	17118	1	1	100.00
CONT_ASSIGN	17119	1	1	100.00
CONT_ASSIGN	17121	1	1	100.00
CONT_ASSIGN	17122	1	1	100.00
CONT_ASSIGN	17124	1	1	100.00
CONT_ASSIGN	17125	1	1	100.00
CONT_ASSIGN	17127	1	1	100.00
CONT_ASSIGN	17128	1	1	100.00
CONT_ASSIGN	17130	1	1	100.00
CONT_ASSIGN	17131	1	1	100.00
CONT_ASSIGN	17133	1	1	100.00
CONT_ASSIGN	17134	1	1	100.00
CONT_ASSIGN	17136	1	1	100.00
CONT_ASSIGN	17137	1	1	100.00
CONT_ASSIGN	17139	1	1	100.00
CONT_ASSIGN	17140	1	1	100.00
CONT_ASSIGN	17142	1	1	100.00
CONT_ASSIGN	17143	1	1	100.00
CONT_ASSIGN	17145	1	1	100.00
CONT_ASSIGN	17146	1	1	100.00
CONT_ASSIGN	17148	1	1	100.00
CONT_ASSIGN	17149	1	1	100.00
CONT_ASSIGN	17151	1	1	100.00
CONT_ASSIGN	17152	1	1	100.00
CONT_ASSIGN	17154	1	1	100.00
CONT_ASSIGN	17155	1	1	100.00
CONT_ASSIGN	17157	1	1	100.00
CONT_ASSIGN	17158	1	1	100.00
CONT_ASSIGN	17160	1	1	100.00
CONT_ASSIGN	17161	1	1	100.00
CONT_ASSIGN	17163	1	1	100.00
CONT_ASSIGN	17164	1	1	100.00
CONT_ASSIGN	17166	1	1	100.00
CONT_ASSIGN	17167	1	1	100.00
CONT_ASSIGN	17169	1	1	100.00
CONT_ASSIGN	17170	1	1	100.00
CONT_ASSIGN	17172	1	1	100.00
CONT_ASSIGN	17173	1	1	100.00
CONT_ASSIGN	17175	1	1	100.00
CONT_ASSIGN	17176	1	1	100.00
CONT_ASSIGN	17178	1	1	100.00
CONT_ASSIGN	17179	1	1	100.00
CONT_ASSIGN	17181	1	1	100.00
CONT_ASSIGN	17182	1	1	100.00
CONT_ASSIGN	17184	1	1	100.00
CONT_ASSIGN	17185	1	1	100.00
CONT_ASSIGN	17187	1	1	100.00
CONT_ASSIGN	17188	1	1	100.00
CONT_ASSIGN	17190	1	1	100.00
CONT_ASSIGN	17191	1	1	100.00
CONT_ASSIGN	17193	1	1	100.00
CONT_ASSIGN	17194	1	1	100.00
CONT_ASSIGN	17196	1	1	100.00
CONT_ASSIGN	17197	1	1	100.00
CONT_ASSIGN	17199	1	1	100.00
CONT_ASSIGN	17200	1	1	100.00
CONT_ASSIGN	17202	1	1	100.00
CONT_ASSIGN	17203	1	1	100.00
CONT_ASSIGN	17205	1	1	100.00
CONT_ASSIGN	17206	1	1	100.00
CONT_ASSIGN	17208	1	1	100.00
CONT_ASSIGN	17209	1	1	100.00
CONT_ASSIGN	17211	1	1	100.00
CONT_ASSIGN	17212	1	1	100.00
CONT_ASSIGN	17214	1	1	100.00
CONT_ASSIGN	17215	1	1	100.00
CONT_ASSIGN	17217	1	1	100.00
CONT_ASSIGN	17218	1	1	100.00
CONT_ASSIGN	17220	1	1	100.00
CONT_ASSIGN	17221	1	1	100.00
CONT_ASSIGN	17223	1	1	100.00
CONT_ASSIGN	17224	1	1	100.00
CONT_ASSIGN	17226	1	1	100.00
CONT_ASSIGN	17227	1	1	100.00
CONT_ASSIGN	17229	1	1	100.00
CONT_ASSIGN	17230	1	1	100.00
CONT_ASSIGN	17232	1	1	100.00
CONT_ASSIGN	17233	1	1	100.00
CONT_ASSIGN	17235	1	1	100.00
CONT_ASSIGN	17236	1	1	100.00
CONT_ASSIGN	17238	1	1	100.00
CONT_ASSIGN	17239	1	1	100.00
CONT_ASSIGN	17241	1	1	100.00
CONT_ASSIGN	17242	1	1	100.00
CONT_ASSIGN	17244	1	1	100.00
CONT_ASSIGN	17245	1	1	100.00
CONT_ASSIGN	17247	1	1	100.00
CONT_ASSIGN	17248	1	1	100.00
CONT_ASSIGN	17250	1	1	100.00
CONT_ASSIGN	17251	1	1	100.00
CONT_ASSIGN	17253	1	1	100.00
CONT_ASSIGN	17254	1	1	100.00
CONT_ASSIGN	17256	1	1	100.00
CONT_ASSIGN	17257	1	1	100.00
CONT_ASSIGN	17259	1	1	100.00
CONT_ASSIGN	17260	1	1	100.00
CONT_ASSIGN	17262	1	1	100.00
CONT_ASSIGN	17263	1	1	100.00
CONT_ASSIGN	17265	1	1	100.00
CONT_ASSIGN	17266	1	1	100.00
CONT_ASSIGN	17268	1	1	100.00
CONT_ASSIGN	17269	1	1	100.00
CONT_ASSIGN	17271	1	1	100.00
CONT_ASSIGN	17272	1	1	100.00
CONT_ASSIGN	17274	1	1	100.00
CONT_ASSIGN	17275	1	1	100.00
CONT_ASSIGN	17277	1	1	100.00
CONT_ASSIGN	17278	1	1	100.00
CONT_ASSIGN	17280	1	1	100.00
CONT_ASSIGN	17281	1	1	100.00
CONT_ASSIGN	17283	1	1	100.00
CONT_ASSIGN	17284	1	1	100.00
CONT_ASSIGN	17286	1	1	100.00
CONT_ASSIGN	17287	1	1	100.00
CONT_ASSIGN	17289	1	1	100.00
CONT_ASSIGN	17290	1	1	100.00
CONT_ASSIGN	17292	1	1	100.00
CONT_ASSIGN	17293	1	1	100.00
CONT_ASSIGN	17295	1	1	100.00
CONT_ASSIGN	17296	1	1	100.00
CONT_ASSIGN	17298	1	1	100.00
CONT_ASSIGN	17299	1	1	100.00
CONT_ASSIGN	17301	1	1	100.00
CONT_ASSIGN	17302	1	1	100.00
CONT_ASSIGN	17304	1	1	100.00
CONT_ASSIGN	17305	1	1	100.00
CONT_ASSIGN	17307	1	1	100.00
CONT_ASSIGN	17308	1	1	100.00
CONT_ASSIGN	17310	1	1	100.00
CONT_ASSIGN	17311	1	1	100.00
CONT_ASSIGN	17313	1	1	100.00
CONT_ASSIGN	17314	1	1	100.00
CONT_ASSIGN	17316	1	1	100.00
CONT_ASSIGN	17317	1	1	100.00
CONT_ASSIGN	17319	1	1	100.00
CONT_ASSIGN	17320	1	1	100.00
CONT_ASSIGN	17322	1	1	100.00
CONT_ASSIGN	17323	1	1	100.00
CONT_ASSIGN	17325	1	1	100.00
CONT_ASSIGN	17326	1	1	100.00
CONT_ASSIGN	17328	1	1	100.00
CONT_ASSIGN	17329	1	1	100.00
CONT_ASSIGN	17331	1	1	100.00
CONT_ASSIGN	17332	1	1	100.00
CONT_ASSIGN	17334	1	1	100.00
CONT_ASSIGN	17335	1	1	100.00
CONT_ASSIGN	17337	1	1	100.00
CONT_ASSIGN	17338	1	1	100.00
CONT_ASSIGN	17340	1	1	100.00
CONT_ASSIGN	17341	1	1	100.00
CONT_ASSIGN	17343	1	1	100.00
CONT_ASSIGN	17344	1	1	100.00
CONT_ASSIGN	17346	1	1	100.00
CONT_ASSIGN	17347	1	1	100.00
CONT_ASSIGN	17349	1	1	100.00
CONT_ASSIGN	17350	1	1	100.00
CONT_ASSIGN	17352	1	1	100.00
CONT_ASSIGN	17353	1	1	100.00
CONT_ASSIGN	17355	1	1	100.00
CONT_ASSIGN	17356	1	1	100.00
CONT_ASSIGN	17358	1	1	100.00
CONT_ASSIGN	17359	1	1	100.00
CONT_ASSIGN	17361	1	1	100.00
CONT_ASSIGN	17362	1	1	100.00
CONT_ASSIGN	17364	1	1	100.00
CONT_ASSIGN	17365	1	1	100.00
CONT_ASSIGN	17367	1	1	100.00
CONT_ASSIGN	17368	1	1	100.00
CONT_ASSIGN	17370	1	1	100.00
CONT_ASSIGN	17371	1	1	100.00
CONT_ASSIGN	17373	1	1	100.00
CONT_ASSIGN	17374	1	1	100.00
CONT_ASSIGN	17376	1	1	100.00
CONT_ASSIGN	17377	1	1	100.00
CONT_ASSIGN	17379	1	1	100.00
CONT_ASSIGN	17380	1	1	100.00
CONT_ASSIGN	17382	1	1	100.00
CONT_ASSIGN	17383	1	1	100.00
CONT_ASSIGN	17385	1	1	100.00
CONT_ASSIGN	17386	1	1	100.00
CONT_ASSIGN	17388	1	1	100.00
CONT_ASSIGN	17389	1	1	100.00
CONT_ASSIGN	17391	1	1	100.00
CONT_ASSIGN	17392	1	1	100.00
CONT_ASSIGN	17394	1	1	100.00
CONT_ASSIGN	17395	1	1	100.00
CONT_ASSIGN	17397	1	1	100.00
CONT_ASSIGN	17398	1	1	100.00
CONT_ASSIGN	17400	1	1	100.00
CONT_ASSIGN	17401	1	1	100.00
CONT_ASSIGN	17403	1	1	100.00
CONT_ASSIGN	17404	1	1	100.00
CONT_ASSIGN	17406	1	1	100.00
CONT_ASSIGN	17407	1	1	100.00
CONT_ASSIGN	17409	1	1	100.00
CONT_ASSIGN	17410	1	1	100.00
CONT_ASSIGN	17412	1	1	100.00
CONT_ASSIGN	17413	1	1	100.00
CONT_ASSIGN	17415	1	1	100.00
CONT_ASSIGN	17416	1	1	100.00
CONT_ASSIGN	17418	1	1	100.00
CONT_ASSIGN	17419	1	1	100.00
CONT_ASSIGN	17421	1	1	100.00
CONT_ASSIGN	17422	1	1	100.00
CONT_ASSIGN	17424	1	1	100.00
CONT_ASSIGN	17425	1	1	100.00
CONT_ASSIGN	17427	1	1	100.00
CONT_ASSIGN	17428	1	1	100.00
CONT_ASSIGN	17430	1	1	100.00
CONT_ASSIGN	17431	1	1	100.00
CONT_ASSIGN	17433	1	1	100.00
CONT_ASSIGN	17434	1	1	100.00
CONT_ASSIGN	17436	1	1	100.00
CONT_ASSIGN	17437	1	1	100.00
CONT_ASSIGN	17439	1	1	100.00
CONT_ASSIGN	17440	1	1	100.00
CONT_ASSIGN	17442	1	1	100.00
CONT_ASSIGN	17443	1	1	100.00
CONT_ASSIGN	17445	1	1	100.00
CONT_ASSIGN	17446	1	1	100.00
CONT_ASSIGN	17448	1	1	100.00
CONT_ASSIGN	17449	1	1	100.00
CONT_ASSIGN	17451	1	1	100.00
CONT_ASSIGN	17452	1	1	100.00
CONT_ASSIGN	17454	1	1	100.00
CONT_ASSIGN	17455	1	1	100.00
CONT_ASSIGN	17457	1	1	100.00
CONT_ASSIGN	17458	1	1	100.00
CONT_ASSIGN	17460	1	1	100.00
CONT_ASSIGN	17461	1	1	100.00
CONT_ASSIGN	17463	1	1	100.00
CONT_ASSIGN	17464	1	1	100.00
CONT_ASSIGN	17466	1	1	100.00
CONT_ASSIGN	17467	1	1	100.00
CONT_ASSIGN	17469	1	1	100.00
CONT_ASSIGN	17470	1	1	100.00
CONT_ASSIGN	17472	1	1	100.00
CONT_ASSIGN	17473	1	1	100.00
CONT_ASSIGN	17475	1	1	100.00
CONT_ASSIGN	17476	1	1	100.00
CONT_ASSIGN	17478	1	1	100.00
CONT_ASSIGN	17479	1	1	100.00
CONT_ASSIGN	17481	1	1	100.00
CONT_ASSIGN	17482	1	1	100.00
CONT_ASSIGN	17484	1	1	100.00
CONT_ASSIGN	17485	1	1	100.00
CONT_ASSIGN	17487	1	1	100.00
CONT_ASSIGN	17488	1	1	100.00
CONT_ASSIGN	17490	1	1	100.00
CONT_ASSIGN	17491	1	1	100.00
CONT_ASSIGN	17493	1	1	100.00
CONT_ASSIGN	17494	1	1	100.00
CONT_ASSIGN	17496	1	1	100.00
CONT_ASSIGN	17497	1	1	100.00
CONT_ASSIGN	17499	1	1	100.00
CONT_ASSIGN	17500	1	1	100.00
CONT_ASSIGN	17502	1	1	100.00
CONT_ASSIGN	17503	1	1	100.00
CONT_ASSIGN	17505	1	1	100.00
CONT_ASSIGN	17506	1	1	100.00
CONT_ASSIGN	17508	1	1	100.00
CONT_ASSIGN	17509	1	1	100.00
CONT_ASSIGN	17511	1	1	100.00
CONT_ASSIGN	17512	1	1	100.00
CONT_ASSIGN	17514	1	1	100.00
CONT_ASSIGN	17515	1	1	100.00
CONT_ASSIGN	17517	1	1	100.00
CONT_ASSIGN	17518	1	1	100.00
CONT_ASSIGN	17520	1	1	100.00
CONT_ASSIGN	17521	1	1	100.00
CONT_ASSIGN	17523	1	1	100.00
CONT_ASSIGN	17524	1	1	100.00
CONT_ASSIGN	17526	1	1	100.00
CONT_ASSIGN	17527	1	1	100.00
CONT_ASSIGN	17529	1	1	100.00
CONT_ASSIGN	17530	1	1	100.00
CONT_ASSIGN	17532	1	1	100.00
CONT_ASSIGN	17533	1	1	100.00
CONT_ASSIGN	17535	1	1	100.00
CONT_ASSIGN	17536	1	1	100.00
CONT_ASSIGN	17538	1	1	100.00
CONT_ASSIGN	17539	1	1	100.00
CONT_ASSIGN	17541	1	1	100.00
CONT_ASSIGN	17542	1	1	100.00
CONT_ASSIGN	17544	1	1	100.00
CONT_ASSIGN	17545	1	1	100.00
CONT_ASSIGN	17547	1	1	100.00
CONT_ASSIGN	17548	1	1	100.00
CONT_ASSIGN	17550	1	1	100.00
CONT_ASSIGN	17551	1	1	100.00
CONT_ASSIGN	17553	1	1	100.00
CONT_ASSIGN	17554	1	1	100.00
CONT_ASSIGN	17556	1	1	100.00
CONT_ASSIGN	17557	1	1	100.00
CONT_ASSIGN	17559	1	1	100.00
CONT_ASSIGN	17560	1	1	100.00
CONT_ASSIGN	17562	1	1	100.00
CONT_ASSIGN	17563	1	1	100.00
CONT_ASSIGN	17565	1	1	100.00
CONT_ASSIGN	17566	1	1	100.00
CONT_ASSIGN	17568	1	1	100.00
CONT_ASSIGN	17569	1	1	100.00
CONT_ASSIGN	17571	1	1	100.00
CONT_ASSIGN	17572	1	1	100.00
CONT_ASSIGN	17574	1	1	100.00
CONT_ASSIGN	17575	1	1	100.00
CONT_ASSIGN	17577	1	1	100.00
CONT_ASSIGN	17578	1	1	100.00
CONT_ASSIGN	17580	1	1	100.00
CONT_ASSIGN	17581	1	1	100.00
CONT_ASSIGN	17583	1	1	100.00
CONT_ASSIGN	17584	1	1	100.00
CONT_ASSIGN	17586	1	1	100.00
CONT_ASSIGN	17587	1	1	100.00
CONT_ASSIGN	17589	1	1	100.00
CONT_ASSIGN	17590	1	1	100.00
CONT_ASSIGN	17592	1	1	100.00
CONT_ASSIGN	17593	1	1	100.00
CONT_ASSIGN	17595	1	1	100.00
CONT_ASSIGN	17596	1	1	100.00
CONT_ASSIGN	17598	1	1	100.00
CONT_ASSIGN	17599	1	1	100.00
CONT_ASSIGN	17601	1	1	100.00
CONT_ASSIGN	17602	1	1	100.00
CONT_ASSIGN	17604	1	1	100.00
CONT_ASSIGN	17605	1	1	100.00
CONT_ASSIGN	17607	1	1	100.00
CONT_ASSIGN	17608	1	1	100.00
CONT_ASSIGN	17610	1	1	100.00
CONT_ASSIGN	17611	1	1	100.00
CONT_ASSIGN	17613	1	1	100.00
CONT_ASSIGN	17614	1	1	100.00
CONT_ASSIGN	17616	1	1	100.00
CONT_ASSIGN	17617	1	1	100.00
CONT_ASSIGN	17619	1	1	100.00
CONT_ASSIGN	17620	1	1	100.00
CONT_ASSIGN	17622	1	1	100.00
CONT_ASSIGN	17624	1	1	100.00
CONT_ASSIGN	17626	1	1	100.00
CONT_ASSIGN	17628	1	1	100.00
CONT_ASSIGN	17630	1	1	100.00
CONT_ASSIGN	17632	1	1	100.00
CONT_ASSIGN	17634	1	1	100.00
CONT_ASSIGN	17636	1	1	100.00
CONT_ASSIGN	17638	1	1	100.00
CONT_ASSIGN	17640	1	1	100.00
CONT_ASSIGN	17642	1	1	100.00
CONT_ASSIGN	17644	1	1	100.00
CONT_ASSIGN	17646	1	1	100.00
CONT_ASSIGN	17648	1	1	100.00
CONT_ASSIGN	17650	1	1	100.00
CONT_ASSIGN	17652	1	1	100.00
CONT_ASSIGN	17654	1	1	100.00
CONT_ASSIGN	17656	1	1	100.00
CONT_ASSIGN	17658	1	1	100.00
CONT_ASSIGN	17660	1	1	100.00
CONT_ASSIGN	17662	1	1	100.00
CONT_ASSIGN	17664	1	1	100.00
CONT_ASSIGN	17666	1	1	100.00
CONT_ASSIGN	17668	1	1	100.00
CONT_ASSIGN	17670	1	1	100.00
CONT_ASSIGN	17672	1	1	100.00
CONT_ASSIGN	17674	1	1	100.00
CONT_ASSIGN	17676	1	1	100.00
CONT_ASSIGN	17678	1	1	100.00
CONT_ASSIGN	17680	1	1	100.00
CONT_ASSIGN	17682	1	1	100.00
CONT_ASSIGN	17684	1	1	100.00
CONT_ASSIGN	17685	1	1	100.00
CONT_ASSIGN	17687	1	1	100.00
CONT_ASSIGN	17689	1	1	100.00
CONT_ASSIGN	17691	1	1	100.00
CONT_ASSIGN	17693	1	1	100.00
CONT_ASSIGN	17695	1	1	100.00
CONT_ASSIGN	17697	1	1	100.00
CONT_ASSIGN	17699	1	1	100.00
CONT_ASSIGN	17701	1	1	100.00
CONT_ASSIGN	17703	1	1	100.00
CONT_ASSIGN	17705	1	1	100.00
CONT_ASSIGN	17707	1	1	100.00
CONT_ASSIGN	17709	1	1	100.00
CONT_ASSIGN	17711	1	1	100.00
CONT_ASSIGN	17713	1	1	100.00
CONT_ASSIGN	17715	1	1	100.00
CONT_ASSIGN	17717	1	1	100.00
CONT_ASSIGN	17719	1	1	100.00
CONT_ASSIGN	17721	1	1	100.00
CONT_ASSIGN	17723	1	1	100.00
CONT_ASSIGN	17725	1	1	100.00
CONT_ASSIGN	17727	1	1	100.00
CONT_ASSIGN	17729	1	1	100.00
CONT_ASSIGN	17731	1	1	100.00
CONT_ASSIGN	17733	1	1	100.00
CONT_ASSIGN	17735	1	1	100.00
CONT_ASSIGN	17737	1	1	100.00
CONT_ASSIGN	17739	1	1	100.00
CONT_ASSIGN	17741	1	1	100.00
CONT_ASSIGN	17743	1	1	100.00
CONT_ASSIGN	17745	1	1	100.00
CONT_ASSIGN	17747	1	1	100.00
CONT_ASSIGN	17749	1	1	100.00
CONT_ASSIGN	17750	1	1	100.00
CONT_ASSIGN	17752	1	1	100.00
CONT_ASSIGN	17754	1	1	100.00
CONT_ASSIGN	17756	1	1	100.00
CONT_ASSIGN	17758	1	1	100.00
CONT_ASSIGN	17760	1	1	100.00
CONT_ASSIGN	17762	1	1	100.00
CONT_ASSIGN	17764	1	1	100.00
CONT_ASSIGN	17766	1	1	100.00
CONT_ASSIGN	17768	1	1	100.00
CONT_ASSIGN	17770	1	1	100.00
CONT_ASSIGN	17772	1	1	100.00
CONT_ASSIGN	17774	1	1	100.00
CONT_ASSIGN	17776	1	1	100.00
CONT_ASSIGN	17778	1	1	100.00
CONT_ASSIGN	17780	1	1	100.00
CONT_ASSIGN	17782	1	1	100.00
CONT_ASSIGN	17784	1	1	100.00
CONT_ASSIGN	17786	1	1	100.00
CONT_ASSIGN	17788	1	1	100.00
CONT_ASSIGN	17790	1	1	100.00
CONT_ASSIGN	17792	1	1	100.00
CONT_ASSIGN	17794	1	1	100.00
CONT_ASSIGN	17796	1	1	100.00
CONT_ASSIGN	17798	1	1	100.00
CONT_ASSIGN	17800	1	1	100.00
CONT_ASSIGN	17802	1	1	100.00
CONT_ASSIGN	17804	1	1	100.00
CONT_ASSIGN	17806	1	1	100.00
CONT_ASSIGN	17808	1	1	100.00
CONT_ASSIGN	17810	1	1	100.00
CONT_ASSIGN	17812	1	1	100.00
CONT_ASSIGN	17814	1	1	100.00
CONT_ASSIGN	17815	1	1	100.00
CONT_ASSIGN	17817	1	1	100.00
CONT_ASSIGN	17819	1	1	100.00
CONT_ASSIGN	17821	1	1	100.00
CONT_ASSIGN	17823	1	1	100.00
CONT_ASSIGN	17825	1	1	100.00
CONT_ASSIGN	17827	1	1	100.00
CONT_ASSIGN	17829	1	1	100.00
CONT_ASSIGN	17831	1	1	100.00
CONT_ASSIGN	17833	1	1	100.00
CONT_ASSIGN	17835	1	1	100.00
CONT_ASSIGN	17837	1	1	100.00
CONT_ASSIGN	17839	1	1	100.00
CONT_ASSIGN	17841	1	1	100.00
CONT_ASSIGN	17843	1	1	100.00
CONT_ASSIGN	17845	1	1	100.00
CONT_ASSIGN	17847	1	1	100.00
CONT_ASSIGN	17849	1	1	100.00
CONT_ASSIGN	17851	1	1	100.00
CONT_ASSIGN	17853	1	1	100.00
CONT_ASSIGN	17855	1	1	100.00
CONT_ASSIGN	17857	1	1	100.00
CONT_ASSIGN	17859	1	1	100.00
CONT_ASSIGN	17861	1	1	100.00
CONT_ASSIGN	17863	1	1	100.00
CONT_ASSIGN	17865	1	1	100.00
CONT_ASSIGN	17867	1	1	100.00
CONT_ASSIGN	17869	1	1	100.00
CONT_ASSIGN	17871	1	1	100.00
CONT_ASSIGN	17873	1	1	100.00
CONT_ASSIGN	17875	1	1	100.00
CONT_ASSIGN	17877	1	1	100.00
CONT_ASSIGN	17879	1	1	100.00
CONT_ASSIGN	17880	1	1	100.00
CONT_ASSIGN	17882	1	1	100.00
CONT_ASSIGN	17884	1	1	100.00
CONT_ASSIGN	17886	1	1	100.00
CONT_ASSIGN	17888	1	1	100.00
CONT_ASSIGN	17890	1	1	100.00
CONT_ASSIGN	17892	1	1	100.00
CONT_ASSIGN	17894	1	1	100.00
CONT_ASSIGN	17896	1	1	100.00
CONT_ASSIGN	17898	1	1	100.00
CONT_ASSIGN	17900	1	1	100.00
CONT_ASSIGN	17902	1	1	100.00
CONT_ASSIGN	17904	1	1	100.00
CONT_ASSIGN	17906	1	1	100.00
CONT_ASSIGN	17908	1	1	100.00
CONT_ASSIGN	17910	1	1	100.00
CONT_ASSIGN	17912	1	1	100.00
CONT_ASSIGN	17914	1	1	100.00
CONT_ASSIGN	17916	1	1	100.00
CONT_ASSIGN	17918	1	1	100.00
CONT_ASSIGN	17920	1	1	100.00
CONT_ASSIGN	17922	1	1	100.00
CONT_ASSIGN	17924	1	1	100.00
CONT_ASSIGN	17926	1	1	100.00
CONT_ASSIGN	17928	1	1	100.00
CONT_ASSIGN	17930	1	1	100.00
CONT_ASSIGN	17932	1	1	100.00
CONT_ASSIGN	17934	1	1	100.00
CONT_ASSIGN	17936	1	1	100.00
CONT_ASSIGN	17938	1	1	100.00
CONT_ASSIGN	17940	1	1	100.00
CONT_ASSIGN	17942	1	1	100.00
CONT_ASSIGN	17944	1	1	100.00
CONT_ASSIGN	17945	1	1	100.00
CONT_ASSIGN	17947	1	1	100.00
CONT_ASSIGN	17949	1	1	100.00
CONT_ASSIGN	17951	1	1	100.00
CONT_ASSIGN	17953	1	1	100.00
CONT_ASSIGN	17955	1	1	100.00
CONT_ASSIGN	17957	1	1	100.00
CONT_ASSIGN	17959	1	1	100.00
CONT_ASSIGN	17961	1	1	100.00
CONT_ASSIGN	17963	1	1	100.00
CONT_ASSIGN	17965	1	1	100.00
CONT_ASSIGN	17967	1	1	100.00
CONT_ASSIGN	17969	1	1	100.00
CONT_ASSIGN	17971	1	1	100.00
CONT_ASSIGN	17973	1	1	100.00
CONT_ASSIGN	17975	1	1	100.00
CONT_ASSIGN	17977	1	1	100.00
CONT_ASSIGN	17979	1	1	100.00
CONT_ASSIGN	17981	1	1	100.00
CONT_ASSIGN	17983	1	1	100.00
CONT_ASSIGN	17985	1	1	100.00
CONT_ASSIGN	17987	1	1	100.00
CONT_ASSIGN	17989	1	1	100.00
CONT_ASSIGN	17991	1	1	100.00
CONT_ASSIGN	17993	1	1	100.00
CONT_ASSIGN	17995	1	1	100.00
CONT_ASSIGN	17997	1	1	100.00
CONT_ASSIGN	17998	1	1	100.00
CONT_ASSIGN	18000	1	1	100.00
CONT_ASSIGN	18001	1	1	100.00
CONT_ASSIGN	18002	1	1	100.00
CONT_ASSIGN	18004	1	1	100.00
CONT_ASSIGN	18005	1	1	100.00
CONT_ASSIGN	18007	1	1	100.00
CONT_ASSIGN	18008	1	1	100.00
CONT_ASSIGN	18010	1	1	100.00
ALWAYS	18014	203	203	100.00
ALWAYS	18221	564	564	100.00
CONT_ASSIGN	19402	0	0
CONT_ASSIGN	19410	1	1	100.00
CONT_ASSIGN	19411	1	1	100.00

Click here to see the source line report.

Cond Coverage for Module : rv_plic_reg_top

	Total	Covered	Percent
Conditions	2023	2021	99.90
Logical	2023	2021	99.90
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
58-16780	99.64
16781-16856	100.00
16856	100.00
16856	100.00
16856-17272	100.00
17275-17500	100.00
17503-18008	99.50

Branch Coverage for Module : rv_plic_reg_top

	Line No.	Total	Covered	Percent
Branches		208	208	100.00
TERNARY	16852	2	2	100.00
IF	68	3	3	100.00
CASE	18222	203	203	100.00



16852        assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T1,T2,T3



68             if (!rst_ni) begin
               -1-  
69               err_q <= '0;
                 ==>
70             end else if (intg_err || reg_we_err) begin
                        -2-  
71               err_q <= 1'b1;
                 ==>
72             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T347,T348,T349
0	0	Covered	T1,T2,T3



18222          unique case (1'b1)
                      -1-  
18223            addr_hit[0]: begin
18224              reg_rdata_next[1:0] = prio0_qs;
                   ==>
18225            end
18226      
18227            addr_hit[1]: begin
18228              reg_rdata_next[1:0] = prio1_qs;
                   ==>
18229            end
18230      
18231            addr_hit[2]: begin
18232              reg_rdata_next[1:0] = prio2_qs;
                   ==>
18233            end
18234      
18235            addr_hit[3]: begin
18236              reg_rdata_next[1:0] = prio3_qs;
                   ==>
18237            end
18238      
18239            addr_hit[4]: begin
18240              reg_rdata_next[1:0] = prio4_qs;
                   ==>
18241            end
18242      
18243            addr_hit[5]: begin
18244              reg_rdata_next[1:0] = prio5_qs;
                   ==>
18245            end
18246      
18247            addr_hit[6]: begin
18248              reg_rdata_next[1:0] = prio6_qs;
                   ==>
18249            end
18250      
18251            addr_hit[7]: begin
18252              reg_rdata_next[1:0] = prio7_qs;
                   ==>
18253            end
18254      
18255            addr_hit[8]: begin
18256              reg_rdata_next[1:0] = prio8_qs;
                   ==>
18257            end
18258      
18259            addr_hit[9]: begin
18260              reg_rdata_next[1:0] = prio9_qs;
                   ==>
18261            end
18262      
18263            addr_hit[10]: begin
18264              reg_rdata_next[1:0] = prio10_qs;
                   ==>
18265            end
18266      
18267            addr_hit[11]: begin
18268              reg_rdata_next[1:0] = prio11_qs;
                   ==>
18269            end
18270      
18271            addr_hit[12]: begin
18272              reg_rdata_next[1:0] = prio12_qs;
                   ==>
18273            end
18274      
18275            addr_hit[13]: begin
18276              reg_rdata_next[1:0] = prio13_qs;
                   ==>
18277            end
18278      
18279            addr_hit[14]: begin
18280              reg_rdata_next[1:0] = prio14_qs;
                   ==>
18281            end
18282      
18283            addr_hit[15]: begin
18284              reg_rdata_next[1:0] = prio15_qs;
                   ==>
18285            end
18286      
18287            addr_hit[16]: begin
18288              reg_rdata_next[1:0] = prio16_qs;
                   ==>
18289            end
18290      
18291            addr_hit[17]: begin
18292              reg_rdata_next[1:0] = prio17_qs;
                   ==>
18293            end
18294      
18295            addr_hit[18]: begin
18296              reg_rdata_next[1:0] = prio18_qs;
                   ==>
18297            end
18298      
18299            addr_hit[19]: begin
18300              reg_rdata_next[1:0] = prio19_qs;
                   ==>
18301            end
18302      
18303            addr_hit[20]: begin
18304              reg_rdata_next[1:0] = prio20_qs;
                   ==>
18305            end
18306      
18307            addr_hit[21]: begin
18308              reg_rdata_next[1:0] = prio21_qs;
                   ==>
18309            end
18310      
18311            addr_hit[22]: begin
18312              reg_rdata_next[1:0] = prio22_qs;
                   ==>
18313            end
18314      
18315            addr_hit[23]: begin
18316              reg_rdata_next[1:0] = prio23_qs;
                   ==>
18317            end
18318      
18319            addr_hit[24]: begin
18320              reg_rdata_next[1:0] = prio24_qs;
                   ==>
18321            end
18322      
18323            addr_hit[25]: begin
18324              reg_rdata_next[1:0] = prio25_qs;
                   ==>
18325            end
18326      
18327            addr_hit[26]: begin
18328              reg_rdata_next[1:0] = prio26_qs;
                   ==>
18329            end
18330      
18331            addr_hit[27]: begin
18332              reg_rdata_next[1:0] = prio27_qs;
                   ==>
18333            end
18334      
18335            addr_hit[28]: begin
18336              reg_rdata_next[1:0] = prio28_qs;
                   ==>
18337            end
18338      
18339            addr_hit[29]: begin
18340              reg_rdata_next[1:0] = prio29_qs;
                   ==>
18341            end
18342      
18343            addr_hit[30]: begin
18344              reg_rdata_next[1:0] = prio30_qs;
                   ==>
18345            end
18346      
18347            addr_hit[31]: begin
18348              reg_rdata_next[1:0] = prio31_qs;
                   ==>
18349            end
18350      
18351            addr_hit[32]: begin
18352              reg_rdata_next[1:0] = prio32_qs;
                   ==>
18353            end
18354      
18355            addr_hit[33]: begin
18356              reg_rdata_next[1:0] = prio33_qs;
                   ==>
18357            end
18358      
18359            addr_hit[34]: begin
18360              reg_rdata_next[1:0] = prio34_qs;
                   ==>
18361            end
18362      
18363            addr_hit[35]: begin
18364              reg_rdata_next[1:0] = prio35_qs;
                   ==>
18365            end
18366      
18367            addr_hit[36]: begin
18368              reg_rdata_next[1:0] = prio36_qs;
                   ==>
18369            end
18370      
18371            addr_hit[37]: begin
18372              reg_rdata_next[1:0] = prio37_qs;
                   ==>
18373            end
18374      
18375            addr_hit[38]: begin
18376              reg_rdata_next[1:0] = prio38_qs;
                   ==>
18377            end
18378      
18379            addr_hit[39]: begin
18380              reg_rdata_next[1:0] = prio39_qs;
                   ==>
18381            end
18382      
18383            addr_hit[40]: begin
18384              reg_rdata_next[1:0] = prio40_qs;
                   ==>
18385            end
18386      
18387            addr_hit[41]: begin
18388              reg_rdata_next[1:0] = prio41_qs;
                   ==>
18389            end
18390      
18391            addr_hit[42]: begin
18392              reg_rdata_next[1:0] = prio42_qs;
                   ==>
18393            end
18394      
18395            addr_hit[43]: begin
18396              reg_rdata_next[1:0] = prio43_qs;
                   ==>
18397            end
18398      
18399            addr_hit[44]: begin
18400              reg_rdata_next[1:0] = prio44_qs;
                   ==>
18401            end
18402      
18403            addr_hit[45]: begin
18404              reg_rdata_next[1:0] = prio45_qs;
                   ==>
18405            end
18406      
18407            addr_hit[46]: begin
18408              reg_rdata_next[1:0] = prio46_qs;
                   ==>
18409            end
18410      
18411            addr_hit[47]: begin
18412              reg_rdata_next[1:0] = prio47_qs;
                   ==>
18413            end
18414      
18415            addr_hit[48]: begin
18416              reg_rdata_next[1:0] = prio48_qs;
                   ==>
18417            end
18418      
18419            addr_hit[49]: begin
18420              reg_rdata_next[1:0] = prio49_qs;
                   ==>
18421            end
18422      
18423            addr_hit[50]: begin
18424              reg_rdata_next[1:0] = prio50_qs;
                   ==>
18425            end
18426      
18427            addr_hit[51]: begin
18428              reg_rdata_next[1:0] = prio51_qs;
                   ==>
18429            end
18430      
18431            addr_hit[52]: begin
18432              reg_rdata_next[1:0] = prio52_qs;
                   ==>
18433            end
18434      
18435            addr_hit[53]: begin
18436              reg_rdata_next[1:0] = prio53_qs;
                   ==>
18437            end
18438      
18439            addr_hit[54]: begin
18440              reg_rdata_next[1:0] = prio54_qs;
                   ==>
18441            end
18442      
18443            addr_hit[55]: begin
18444              reg_rdata_next[1:0] = prio55_qs;
                   ==>
18445            end
18446      
18447            addr_hit[56]: begin
18448              reg_rdata_next[1:0] = prio56_qs;
                   ==>
18449            end
18450      
18451            addr_hit[57]: begin
18452              reg_rdata_next[1:0] = prio57_qs;
                   ==>
18453            end
18454      
18455            addr_hit[58]: begin
18456              reg_rdata_next[1:0] = prio58_qs;
                   ==>
18457            end
18458      
18459            addr_hit[59]: begin
18460              reg_rdata_next[1:0] = prio59_qs;
                   ==>
18461            end
18462      
18463            addr_hit[60]: begin
18464              reg_rdata_next[1:0] = prio60_qs;
                   ==>
18465            end
18466      
18467            addr_hit[61]: begin
18468              reg_rdata_next[1:0] = prio61_qs;
                   ==>
18469            end
18470      
18471            addr_hit[62]: begin
18472              reg_rdata_next[1:0] = prio62_qs;
                   ==>
18473            end
18474      
18475            addr_hit[63]: begin
18476              reg_rdata_next[1:0] = prio63_qs;
                   ==>
18477            end
18478      
18479            addr_hit[64]: begin
18480              reg_rdata_next[1:0] = prio64_qs;
                   ==>
18481            end
18482      
18483            addr_hit[65]: begin
18484              reg_rdata_next[1:0] = prio65_qs;
                   ==>
18485            end
18486      
18487            addr_hit[66]: begin
18488              reg_rdata_next[1:0] = prio66_qs;
                   ==>
18489            end
18490      
18491            addr_hit[67]: begin
18492              reg_rdata_next[1:0] = prio67_qs;
                   ==>
18493            end
18494      
18495            addr_hit[68]: begin
18496              reg_rdata_next[1:0] = prio68_qs;
                   ==>
18497            end
18498      
18499            addr_hit[69]: begin
18500              reg_rdata_next[1:0] = prio69_qs;
                   ==>
18501            end
18502      
18503            addr_hit[70]: begin
18504              reg_rdata_next[1:0] = prio70_qs;
                   ==>
18505            end
18506      
18507            addr_hit[71]: begin
18508              reg_rdata_next[1:0] = prio71_qs;
                   ==>
18509            end
18510      
18511            addr_hit[72]: begin
18512              reg_rdata_next[1:0] = prio72_qs;
                   ==>
18513            end
18514      
18515            addr_hit[73]: begin
18516              reg_rdata_next[1:0] = prio73_qs;
                   ==>
18517            end
18518      
18519            addr_hit[74]: begin
18520              reg_rdata_next[1:0] = prio74_qs;
                   ==>
18521            end
18522      
18523            addr_hit[75]: begin
18524              reg_rdata_next[1:0] = prio75_qs;
                   ==>
18525            end
18526      
18527            addr_hit[76]: begin
18528              reg_rdata_next[1:0] = prio76_qs;
                   ==>
18529            end
18530      
18531            addr_hit[77]: begin
18532              reg_rdata_next[1:0] = prio77_qs;
                   ==>
18533            end
18534      
18535            addr_hit[78]: begin
18536              reg_rdata_next[1:0] = prio78_qs;
                   ==>
18537            end
18538      
18539            addr_hit[79]: begin
18540              reg_rdata_next[1:0] = prio79_qs;
                   ==>
18541            end
18542      
18543            addr_hit[80]: begin
18544              reg_rdata_next[1:0] = prio80_qs;
                   ==>
18545            end
18546      
18547            addr_hit[81]: begin
18548              reg_rdata_next[1:0] = prio81_qs;
                   ==>
18549            end
18550      
18551            addr_hit[82]: begin
18552              reg_rdata_next[1:0] = prio82_qs;
                   ==>
18553            end
18554      
18555            addr_hit[83]: begin
18556              reg_rdata_next[1:0] = prio83_qs;
                   ==>
18557            end
18558      
18559            addr_hit[84]: begin
18560              reg_rdata_next[1:0] = prio84_qs;
                   ==>
18561            end
18562      
18563            addr_hit[85]: begin
18564              reg_rdata_next[1:0] = prio85_qs;
                   ==>
18565            end
18566      
18567            addr_hit[86]: begin
18568              reg_rdata_next[1:0] = prio86_qs;
                   ==>
18569            end
18570      
18571            addr_hit[87]: begin
18572              reg_rdata_next[1:0] = prio87_qs;
                   ==>
18573            end
18574      
18575            addr_hit[88]: begin
18576              reg_rdata_next[1:0] = prio88_qs;
                   ==>
18577            end
18578      
18579            addr_hit[89]: begin
18580              reg_rdata_next[1:0] = prio89_qs;
                   ==>
18581            end
18582      
18583            addr_hit[90]: begin
18584              reg_rdata_next[1:0] = prio90_qs;
                   ==>
18585            end
18586      
18587            addr_hit[91]: begin
18588              reg_rdata_next[1:0] = prio91_qs;
                   ==>
18589            end
18590      
18591            addr_hit[92]: begin
18592              reg_rdata_next[1:0] = prio92_qs;
                   ==>
18593            end
18594      
18595            addr_hit[93]: begin
18596              reg_rdata_next[1:0] = prio93_qs;
                   ==>
18597            end
18598      
18599            addr_hit[94]: begin
18600              reg_rdata_next[1:0] = prio94_qs;
                   ==>
18601            end
18602      
18603            addr_hit[95]: begin
18604              reg_rdata_next[1:0] = prio95_qs;
                   ==>
18605            end
18606      
18607            addr_hit[96]: begin
18608              reg_rdata_next[1:0] = prio96_qs;
                   ==>
18609            end
18610      
18611            addr_hit[97]: begin
18612              reg_rdata_next[1:0] = prio97_qs;
                   ==>
18613            end
18614      
18615            addr_hit[98]: begin
18616              reg_rdata_next[1:0] = prio98_qs;
                   ==>
18617            end
18618      
18619            addr_hit[99]: begin
18620              reg_rdata_next[1:0] = prio99_qs;
                   ==>
18621            end
18622      
18623            addr_hit[100]: begin
18624              reg_rdata_next[1:0] = prio100_qs;
                   ==>
18625            end
18626      
18627            addr_hit[101]: begin
18628              reg_rdata_next[1:0] = prio101_qs;
                   ==>
18629            end
18630      
18631            addr_hit[102]: begin
18632              reg_rdata_next[1:0] = prio102_qs;
                   ==>
18633            end
18634      
18635            addr_hit[103]: begin
18636              reg_rdata_next[1:0] = prio103_qs;
                   ==>
18637            end
18638      
18639            addr_hit[104]: begin
18640              reg_rdata_next[1:0] = prio104_qs;
                   ==>
18641            end
18642      
18643            addr_hit[105]: begin
18644              reg_rdata_next[1:0] = prio105_qs;
                   ==>
18645            end
18646      
18647            addr_hit[106]: begin
18648              reg_rdata_next[1:0] = prio106_qs;
                   ==>
18649            end
18650      
18651            addr_hit[107]: begin
18652              reg_rdata_next[1:0] = prio107_qs;
                   ==>
18653            end
18654      
18655            addr_hit[108]: begin
18656              reg_rdata_next[1:0] = prio108_qs;
                   ==>
18657            end
18658      
18659            addr_hit[109]: begin
18660              reg_rdata_next[1:0] = prio109_qs;
                   ==>
18661            end
18662      
18663            addr_hit[110]: begin
18664              reg_rdata_next[1:0] = prio110_qs;
                   ==>
18665            end
18666      
18667            addr_hit[111]: begin
18668              reg_rdata_next[1:0] = prio111_qs;
                   ==>
18669            end
18670      
18671            addr_hit[112]: begin
18672              reg_rdata_next[1:0] = prio112_qs;
                   ==>
18673            end
18674      
18675            addr_hit[113]: begin
18676              reg_rdata_next[1:0] = prio113_qs;
                   ==>
18677            end
18678      
18679            addr_hit[114]: begin
18680              reg_rdata_next[1:0] = prio114_qs;
                   ==>
18681            end
18682      
18683            addr_hit[115]: begin
18684              reg_rdata_next[1:0] = prio115_qs;
                   ==>
18685            end
18686      
18687            addr_hit[116]: begin
18688              reg_rdata_next[1:0] = prio116_qs;
                   ==>
18689            end
18690      
18691            addr_hit[117]: begin
18692              reg_rdata_next[1:0] = prio117_qs;
                   ==>
18693            end
18694      
18695            addr_hit[118]: begin
18696              reg_rdata_next[1:0] = prio118_qs;
                   ==>
18697            end
18698      
18699            addr_hit[119]: begin
18700              reg_rdata_next[1:0] = prio119_qs;
                   ==>
18701            end
18702      
18703            addr_hit[120]: begin
18704              reg_rdata_next[1:0] = prio120_qs;
                   ==>
18705            end
18706      
18707            addr_hit[121]: begin
18708              reg_rdata_next[1:0] = prio121_qs;
                   ==>
18709            end
18710      
18711            addr_hit[122]: begin
18712              reg_rdata_next[1:0] = prio122_qs;
                   ==>
18713            end
18714      
18715            addr_hit[123]: begin
18716              reg_rdata_next[1:0] = prio123_qs;
                   ==>
18717            end
18718      
18719            addr_hit[124]: begin
18720              reg_rdata_next[1:0] = prio124_qs;
                   ==>
18721            end
18722      
18723            addr_hit[125]: begin
18724              reg_rdata_next[1:0] = prio125_qs;
                   ==>
18725            end
18726      
18727            addr_hit[126]: begin
18728              reg_rdata_next[1:0] = prio126_qs;
                   ==>
18729            end
18730      
18731            addr_hit[127]: begin
18732              reg_rdata_next[1:0] = prio127_qs;
                   ==>
18733            end
18734      
18735            addr_hit[128]: begin
18736              reg_rdata_next[1:0] = prio128_qs;
                   ==>
18737            end
18738      
18739            addr_hit[129]: begin
18740              reg_rdata_next[1:0] = prio129_qs;
                   ==>
18741            end
18742      
18743            addr_hit[130]: begin
18744              reg_rdata_next[1:0] = prio130_qs;
                   ==>
18745            end
18746      
18747            addr_hit[131]: begin
18748              reg_rdata_next[1:0] = prio131_qs;
                   ==>
18749            end
18750      
18751            addr_hit[132]: begin
18752              reg_rdata_next[1:0] = prio132_qs;
                   ==>
18753            end
18754      
18755            addr_hit[133]: begin
18756              reg_rdata_next[1:0] = prio133_qs;
                   ==>
18757            end
18758      
18759            addr_hit[134]: begin
18760              reg_rdata_next[1:0] = prio134_qs;
                   ==>
18761            end
18762      
18763            addr_hit[135]: begin
18764              reg_rdata_next[1:0] = prio135_qs;
                   ==>
18765            end
18766      
18767            addr_hit[136]: begin
18768              reg_rdata_next[1:0] = prio136_qs;
                   ==>
18769            end
18770      
18771            addr_hit[137]: begin
18772              reg_rdata_next[1:0] = prio137_qs;
                   ==>
18773            end
18774      
18775            addr_hit[138]: begin
18776              reg_rdata_next[1:0] = prio138_qs;
                   ==>
18777            end
18778      
18779            addr_hit[139]: begin
18780              reg_rdata_next[1:0] = prio139_qs;
                   ==>
18781            end
18782      
18783            addr_hit[140]: begin
18784              reg_rdata_next[1:0] = prio140_qs;
                   ==>
18785            end
18786      
18787            addr_hit[141]: begin
18788              reg_rdata_next[1:0] = prio141_qs;
                   ==>
18789            end
18790      
18791            addr_hit[142]: begin
18792              reg_rdata_next[1:0] = prio142_qs;
                   ==>
18793            end
18794      
18795            addr_hit[143]: begin
18796              reg_rdata_next[1:0] = prio143_qs;
                   ==>
18797            end
18798      
18799            addr_hit[144]: begin
18800              reg_rdata_next[1:0] = prio144_qs;
                   ==>
18801            end
18802      
18803            addr_hit[145]: begin
18804              reg_rdata_next[1:0] = prio145_qs;
                   ==>
18805            end
18806      
18807            addr_hit[146]: begin
18808              reg_rdata_next[1:0] = prio146_qs;
                   ==>
18809            end
18810      
18811            addr_hit[147]: begin
18812              reg_rdata_next[1:0] = prio147_qs;
                   ==>
18813            end
18814      
18815            addr_hit[148]: begin
18816              reg_rdata_next[1:0] = prio148_qs;
                   ==>
18817            end
18818      
18819            addr_hit[149]: begin
18820              reg_rdata_next[1:0] = prio149_qs;
                   ==>
18821            end
18822      
18823            addr_hit[150]: begin
18824              reg_rdata_next[1:0] = prio150_qs;
                   ==>
18825            end
18826      
18827            addr_hit[151]: begin
18828              reg_rdata_next[1:0] = prio151_qs;
                   ==>
18829            end
18830      
18831            addr_hit[152]: begin
18832              reg_rdata_next[1:0] = prio152_qs;
                   ==>
18833            end
18834      
18835            addr_hit[153]: begin
18836              reg_rdata_next[1:0] = prio153_qs;
                   ==>
18837            end
18838      
18839            addr_hit[154]: begin
18840              reg_rdata_next[1:0] = prio154_qs;
                   ==>
18841            end
18842      
18843            addr_hit[155]: begin
18844              reg_rdata_next[1:0] = prio155_qs;
                   ==>
18845            end
18846      
18847            addr_hit[156]: begin
18848              reg_rdata_next[1:0] = prio156_qs;
                   ==>
18849            end
18850      
18851            addr_hit[157]: begin
18852              reg_rdata_next[1:0] = prio157_qs;
                   ==>
18853            end
18854      
18855            addr_hit[158]: begin
18856              reg_rdata_next[1:0] = prio158_qs;
                   ==>
18857            end
18858      
18859            addr_hit[159]: begin
18860              reg_rdata_next[1:0] = prio159_qs;
                   ==>
18861            end
18862      
18863            addr_hit[160]: begin
18864              reg_rdata_next[1:0] = prio160_qs;
                   ==>
18865            end
18866      
18867            addr_hit[161]: begin
18868              reg_rdata_next[1:0] = prio161_qs;
                   ==>
18869            end
18870      
18871            addr_hit[162]: begin
18872              reg_rdata_next[1:0] = prio162_qs;
                   ==>
18873            end
18874      
18875            addr_hit[163]: begin
18876              reg_rdata_next[1:0] = prio163_qs;
                   ==>
18877            end
18878      
18879            addr_hit[164]: begin
18880              reg_rdata_next[1:0] = prio164_qs;
                   ==>
18881            end
18882      
18883            addr_hit[165]: begin
18884              reg_rdata_next[1:0] = prio165_qs;
                   ==>
18885            end
18886      
18887            addr_hit[166]: begin
18888              reg_rdata_next[1:0] = prio166_qs;
                   ==>
18889            end
18890      
18891            addr_hit[167]: begin
18892              reg_rdata_next[1:0] = prio167_qs;
                   ==>
18893            end
18894      
18895            addr_hit[168]: begin
18896              reg_rdata_next[1:0] = prio168_qs;
                   ==>
18897            end
18898      
18899            addr_hit[169]: begin
18900              reg_rdata_next[1:0] = prio169_qs;
                   ==>
18901            end
18902      
18903            addr_hit[170]: begin
18904              reg_rdata_next[1:0] = prio170_qs;
                   ==>
18905            end
18906      
18907            addr_hit[171]: begin
18908              reg_rdata_next[1:0] = prio171_qs;
                   ==>
18909            end
18910      
18911            addr_hit[172]: begin
18912              reg_rdata_next[1:0] = prio172_qs;
                   ==>
18913            end
18914      
18915            addr_hit[173]: begin
18916              reg_rdata_next[1:0] = prio173_qs;
                   ==>
18917            end
18918      
18919            addr_hit[174]: begin
18920              reg_rdata_next[1:0] = prio174_qs;
                   ==>
18921            end
18922      
18923            addr_hit[175]: begin
18924              reg_rdata_next[1:0] = prio175_qs;
                   ==>
18925            end
18926      
18927            addr_hit[176]: begin
18928              reg_rdata_next[1:0] = prio176_qs;
                   ==>
18929            end
18930      
18931            addr_hit[177]: begin
18932              reg_rdata_next[1:0] = prio177_qs;
                   ==>
18933            end
18934      
18935            addr_hit[178]: begin
18936              reg_rdata_next[1:0] = prio178_qs;
                   ==>
18937            end
18938      
18939            addr_hit[179]: begin
18940              reg_rdata_next[1:0] = prio179_qs;
                   ==>
18941            end
18942      
18943            addr_hit[180]: begin
18944              reg_rdata_next[1:0] = prio180_qs;
                   ==>
18945            end
18946      
18947            addr_hit[181]: begin
18948              reg_rdata_next[1:0] = prio181_qs;
                   ==>
18949            end
18950      
18951            addr_hit[182]: begin
18952              reg_rdata_next[1:0] = prio182_qs;
                   ==>
18953            end
18954      
18955            addr_hit[183]: begin
18956              reg_rdata_next[1:0] = prio183_qs;
                   ==>
18957            end
18958      
18959            addr_hit[184]: begin
18960              reg_rdata_next[1:0] = prio184_qs;
                   ==>
18961            end
18962      
18963            addr_hit[185]: begin
18964              reg_rdata_next[1:0] = prio185_qs;
                   ==>
18965            end
18966      
18967            addr_hit[186]: begin
18968              reg_rdata_next[0] = ip_0_p_0_qs;
                   ==>
18969              reg_rdata_next[1] = ip_0_p_1_qs;
18970              reg_rdata_next[2] = ip_0_p_2_qs;
18971              reg_rdata_next[3] = ip_0_p_3_qs;
18972              reg_rdata_next[4] = ip_0_p_4_qs;
18973              reg_rdata_next[5] = ip_0_p_5_qs;
18974              reg_rdata_next[6] = ip_0_p_6_qs;
18975              reg_rdata_next[7] = ip_0_p_7_qs;
18976              reg_rdata_next[8] = ip_0_p_8_qs;
18977              reg_rdata_next[9] = ip_0_p_9_qs;
18978              reg_rdata_next[10] = ip_0_p_10_qs;
18979              reg_rdata_next[11] = ip_0_p_11_qs;
18980              reg_rdata_next[12] = ip_0_p_12_qs;
18981              reg_rdata_next[13] = ip_0_p_13_qs;
18982              reg_rdata_next[14] = ip_0_p_14_qs;
18983              reg_rdata_next[15] = ip_0_p_15_qs;
18984              reg_rdata_next[16] = ip_0_p_16_qs;
18985              reg_rdata_next[17] = ip_0_p_17_qs;
18986              reg_rdata_next[18] = ip_0_p_18_qs;
18987              reg_rdata_next[19] = ip_0_p_19_qs;
18988              reg_rdata_next[20] = ip_0_p_20_qs;
18989              reg_rdata_next[21] = ip_0_p_21_qs;
18990              reg_rdata_next[22] = ip_0_p_22_qs;
18991              reg_rdata_next[23] = ip_0_p_23_qs;
18992              reg_rdata_next[24] = ip_0_p_24_qs;
18993              reg_rdata_next[25] = ip_0_p_25_qs;
18994              reg_rdata_next[26] = ip_0_p_26_qs;
18995              reg_rdata_next[27] = ip_0_p_27_qs;
18996              reg_rdata_next[28] = ip_0_p_28_qs;
18997              reg_rdata_next[29] = ip_0_p_29_qs;
18998              reg_rdata_next[30] = ip_0_p_30_qs;
18999              reg_rdata_next[31] = ip_0_p_31_qs;
19000            end
19001      
19002            addr_hit[187]: begin
19003              reg_rdata_next[0] = ip_1_p_32_qs;
                   ==>
19004              reg_rdata_next[1] = ip_1_p_33_qs;
19005              reg_rdata_next[2] = ip_1_p_34_qs;
19006              reg_rdata_next[3] = ip_1_p_35_qs;
19007              reg_rdata_next[4] = ip_1_p_36_qs;
19008              reg_rdata_next[5] = ip_1_p_37_qs;
19009              reg_rdata_next[6] = ip_1_p_38_qs;
19010              reg_rdata_next[7] = ip_1_p_39_qs;
19011              reg_rdata_next[8] = ip_1_p_40_qs;
19012              reg_rdata_next[9] = ip_1_p_41_qs;
19013              reg_rdata_next[10] = ip_1_p_42_qs;
19014              reg_rdata_next[11] = ip_1_p_43_qs;
19015              reg_rdata_next[12] = ip_1_p_44_qs;
19016              reg_rdata_next[13] = ip_1_p_45_qs;
19017              reg_rdata_next[14] = ip_1_p_46_qs;
19018              reg_rdata_next[15] = ip_1_p_47_qs;
19019              reg_rdata_next[16] = ip_1_p_48_qs;
19020              reg_rdata_next[17] = ip_1_p_49_qs;
19021              reg_rdata_next[18] = ip_1_p_50_qs;
19022              reg_rdata_next[19] = ip_1_p_51_qs;
19023              reg_rdata_next[20] = ip_1_p_52_qs;
19024              reg_rdata_next[21] = ip_1_p_53_qs;
19025              reg_rdata_next[22] = ip_1_p_54_qs;
19026              reg_rdata_next[23] = ip_1_p_55_qs;
19027              reg_rdata_next[24] = ip_1_p_56_qs;
19028              reg_rdata_next[25] = ip_1_p_57_qs;
19029              reg_rdata_next[26] = ip_1_p_58_qs;
19030              reg_rdata_next[27] = ip_1_p_59_qs;
19031              reg_rdata_next[28] = ip_1_p_60_qs;
19032              reg_rdata_next[29] = ip_1_p_61_qs;
19033              reg_rdata_next[30] = ip_1_p_62_qs;
19034              reg_rdata_next[31] = ip_1_p_63_qs;
19035            end
19036      
19037            addr_hit[188]: begin
19038              reg_rdata_next[0] = ip_2_p_64_qs;
                   ==>
19039              reg_rdata_next[1] = ip_2_p_65_qs;
19040              reg_rdata_next[2] = ip_2_p_66_qs;
19041              reg_rdata_next[3] = ip_2_p_67_qs;
19042              reg_rdata_next[4] = ip_2_p_68_qs;
19043              reg_rdata_next[5] = ip_2_p_69_qs;
19044              reg_rdata_next[6] = ip_2_p_70_qs;
19045              reg_rdata_next[7] = ip_2_p_71_qs;
19046              reg_rdata_next[8] = ip_2_p_72_qs;
19047              reg_rdata_next[9] = ip_2_p_73_qs;
19048              reg_rdata_next[10] = ip_2_p_74_qs;
19049              reg_rdata_next[11] = ip_2_p_75_qs;
19050              reg_rdata_next[12] = ip_2_p_76_qs;
19051              reg_rdata_next[13] = ip_2_p_77_qs;
19052              reg_rdata_next[14] = ip_2_p_78_qs;
19053              reg_rdata_next[15] = ip_2_p_79_qs;
19054              reg_rdata_next[16] = ip_2_p_80_qs;
19055              reg_rdata_next[17] = ip_2_p_81_qs;
19056              reg_rdata_next[18] = ip_2_p_82_qs;
19057              reg_rdata_next[19] = ip_2_p_83_qs;
19058              reg_rdata_next[20] = ip_2_p_84_qs;
19059              reg_rdata_next[21] = ip_2_p_85_qs;
19060              reg_rdata_next[22] = ip_2_p_86_qs;
19061              reg_rdata_next[23] = ip_2_p_87_qs;
19062              reg_rdata_next[24] = ip_2_p_88_qs;
19063              reg_rdata_next[25] = ip_2_p_89_qs;
19064              reg_rdata_next[26] = ip_2_p_90_qs;
19065              reg_rdata_next[27] = ip_2_p_91_qs;
19066              reg_rdata_next[28] = ip_2_p_92_qs;
19067              reg_rdata_next[29] = ip_2_p_93_qs;
19068              reg_rdata_next[30] = ip_2_p_94_qs;
19069              reg_rdata_next[31] = ip_2_p_95_qs;
19070            end
19071      
19072            addr_hit[189]: begin
19073              reg_rdata_next[0] = ip_3_p_96_qs;
                   ==>
19074              reg_rdata_next[1] = ip_3_p_97_qs;
19075              reg_rdata_next[2] = ip_3_p_98_qs;
19076              reg_rdata_next[3] = ip_3_p_99_qs;
19077              reg_rdata_next[4] = ip_3_p_100_qs;
19078              reg_rdata_next[5] = ip_3_p_101_qs;
19079              reg_rdata_next[6] = ip_3_p_102_qs;
19080              reg_rdata_next[7] = ip_3_p_103_qs;
19081              reg_rdata_next[8] = ip_3_p_104_qs;
19082              reg_rdata_next[9] = ip_3_p_105_qs;
19083              reg_rdata_next[10] = ip_3_p_106_qs;
19084              reg_rdata_next[11] = ip_3_p_107_qs;
19085              reg_rdata_next[12] = ip_3_p_108_qs;
19086              reg_rdata_next[13] = ip_3_p_109_qs;
19087              reg_rdata_next[14] = ip_3_p_110_qs;
19088              reg_rdata_next[15] = ip_3_p_111_qs;
19089              reg_rdata_next[16] = ip_3_p_112_qs;
19090              reg_rdata_next[17] = ip_3_p_113_qs;
19091              reg_rdata_next[18] = ip_3_p_114_qs;
19092              reg_rdata_next[19] = ip_3_p_115_qs;
19093              reg_rdata_next[20] = ip_3_p_116_qs;
19094              reg_rdata_next[21] = ip_3_p_117_qs;
19095              reg_rdata_next[22] = ip_3_p_118_qs;
19096              reg_rdata_next[23] = ip_3_p_119_qs;
19097              reg_rdata_next[24] = ip_3_p_120_qs;
19098              reg_rdata_next[25] = ip_3_p_121_qs;
19099              reg_rdata_next[26] = ip_3_p_122_qs;
19100              reg_rdata_next[27] = ip_3_p_123_qs;
19101              reg_rdata_next[28] = ip_3_p_124_qs;
19102              reg_rdata_next[29] = ip_3_p_125_qs;
19103              reg_rdata_next[30] = ip_3_p_126_qs;
19104              reg_rdata_next[31] = ip_3_p_127_qs;
19105            end
19106      
19107            addr_hit[190]: begin
19108              reg_rdata_next[0] = ip_4_p_128_qs;
                   ==>
19109              reg_rdata_next[1] = ip_4_p_129_qs;
19110              reg_rdata_next[2] = ip_4_p_130_qs;
19111              reg_rdata_next[3] = ip_4_p_131_qs;
19112              reg_rdata_next[4] = ip_4_p_132_qs;
19113              reg_rdata_next[5] = ip_4_p_133_qs;
19114              reg_rdata_next[6] = ip_4_p_134_qs;
19115              reg_rdata_next[7] = ip_4_p_135_qs;
19116              reg_rdata_next[8] = ip_4_p_136_qs;
19117              reg_rdata_next[9] = ip_4_p_137_qs;
19118              reg_rdata_next[10] = ip_4_p_138_qs;
19119              reg_rdata_next[11] = ip_4_p_139_qs;
19120              reg_rdata_next[12] = ip_4_p_140_qs;
19121              reg_rdata_next[13] = ip_4_p_141_qs;
19122              reg_rdata_next[14] = ip_4_p_142_qs;
19123              reg_rdata_next[15] = ip_4_p_143_qs;
19124              reg_rdata_next[16] = ip_4_p_144_qs;
19125              reg_rdata_next[17] = ip_4_p_145_qs;
19126              reg_rdata_next[18] = ip_4_p_146_qs;
19127              reg_rdata_next[19] = ip_4_p_147_qs;
19128              reg_rdata_next[20] = ip_4_p_148_qs;
19129              reg_rdata_next[21] = ip_4_p_149_qs;
19130              reg_rdata_next[22] = ip_4_p_150_qs;
19131              reg_rdata_next[23] = ip_4_p_151_qs;
19132              reg_rdata_next[24] = ip_4_p_152_qs;
19133              reg_rdata_next[25] = ip_4_p_153_qs;
19134              reg_rdata_next[26] = ip_4_p_154_qs;
19135              reg_rdata_next[27] = ip_4_p_155_qs;
19136              reg_rdata_next[28] = ip_4_p_156_qs;
19137              reg_rdata_next[29] = ip_4_p_157_qs;
19138              reg_rdata_next[30] = ip_4_p_158_qs;
19139              reg_rdata_next[31] = ip_4_p_159_qs;
19140            end
19141      
19142            addr_hit[191]: begin
19143              reg_rdata_next[0] = ip_5_p_160_qs;
                   ==>
19144              reg_rdata_next[1] = ip_5_p_161_qs;
19145              reg_rdata_next[2] = ip_5_p_162_qs;
19146              reg_rdata_next[3] = ip_5_p_163_qs;
19147              reg_rdata_next[4] = ip_5_p_164_qs;
19148              reg_rdata_next[5] = ip_5_p_165_qs;
19149              reg_rdata_next[6] = ip_5_p_166_qs;
19150              reg_rdata_next[7] = ip_5_p_167_qs;
19151              reg_rdata_next[8] = ip_5_p_168_qs;
19152              reg_rdata_next[9] = ip_5_p_169_qs;
19153              reg_rdata_next[10] = ip_5_p_170_qs;
19154              reg_rdata_next[11] = ip_5_p_171_qs;
19155              reg_rdata_next[12] = ip_5_p_172_qs;
19156              reg_rdata_next[13] = ip_5_p_173_qs;
19157              reg_rdata_next[14] = ip_5_p_174_qs;
19158              reg_rdata_next[15] = ip_5_p_175_qs;
19159              reg_rdata_next[16] = ip_5_p_176_qs;
19160              reg_rdata_next[17] = ip_5_p_177_qs;
19161              reg_rdata_next[18] = ip_5_p_178_qs;
19162              reg_rdata_next[19] = ip_5_p_179_qs;
19163              reg_rdata_next[20] = ip_5_p_180_qs;
19164              reg_rdata_next[21] = ip_5_p_181_qs;
19165              reg_rdata_next[22] = ip_5_p_182_qs;
19166              reg_rdata_next[23] = ip_5_p_183_qs;
19167              reg_rdata_next[24] = ip_5_p_184_qs;
19168              reg_rdata_next[25] = ip_5_p_185_qs;
19169            end
19170      
19171            addr_hit[192]: begin
19172              reg_rdata_next[0] = ie0_0_e_0_qs;
                   ==>
19173              reg_rdata_next[1] = ie0_0_e_1_qs;
19174              reg_rdata_next[2] = ie0_0_e_2_qs;
19175              reg_rdata_next[3] = ie0_0_e_3_qs;
19176              reg_rdata_next[4] = ie0_0_e_4_qs;
19177              reg_rdata_next[5] = ie0_0_e_5_qs;
19178              reg_rdata_next[6] = ie0_0_e_6_qs;
19179              reg_rdata_next[7] = ie0_0_e_7_qs;
19180              reg_rdata_next[8] = ie0_0_e_8_qs;
19181              reg_rdata_next[9] = ie0_0_e_9_qs;
19182              reg_rdata_next[10] = ie0_0_e_10_qs;
19183              reg_rdata_next[11] = ie0_0_e_11_qs;
19184              reg_rdata_next[12] = ie0_0_e_12_qs;
19185              reg_rdata_next[13] = ie0_0_e_13_qs;
19186              reg_rdata_next[14] = ie0_0_e_14_qs;
19187              reg_rdata_next[15] = ie0_0_e_15_qs;
19188              reg_rdata_next[16] = ie0_0_e_16_qs;
19189              reg_rdata_next[17] = ie0_0_e_17_qs;
19190              reg_rdata_next[18] = ie0_0_e_18_qs;
19191              reg_rdata_next[19] = ie0_0_e_19_qs;
19192              reg_rdata_next[20] = ie0_0_e_20_qs;
19193              reg_rdata_next[21] = ie0_0_e_21_qs;
19194              reg_rdata_next[22] = ie0_0_e_22_qs;
19195              reg_rdata_next[23] = ie0_0_e_23_qs;
19196              reg_rdata_next[24] = ie0_0_e_24_qs;
19197              reg_rdata_next[25] = ie0_0_e_25_qs;
19198              reg_rdata_next[26] = ie0_0_e_26_qs;
19199              reg_rdata_next[27] = ie0_0_e_27_qs;
19200              reg_rdata_next[28] = ie0_0_e_28_qs;
19201              reg_rdata_next[29] = ie0_0_e_29_qs;
19202              reg_rdata_next[30] = ie0_0_e_30_qs;
19203              reg_rdata_next[31] = ie0_0_e_31_qs;
19204            end
19205      
19206            addr_hit[193]: begin
19207              reg_rdata_next[0] = ie0_1_e_32_qs;
                   ==>
19208              reg_rdata_next[1] = ie0_1_e_33_qs;
19209              reg_rdata_next[2] = ie0_1_e_34_qs;
19210              reg_rdata_next[3] = ie0_1_e_35_qs;
19211              reg_rdata_next[4] = ie0_1_e_36_qs;
19212              reg_rdata_next[5] = ie0_1_e_37_qs;
19213              reg_rdata_next[6] = ie0_1_e_38_qs;
19214              reg_rdata_next[7] = ie0_1_e_39_qs;
19215              reg_rdata_next[8] = ie0_1_e_40_qs;
19216              reg_rdata_next[9] = ie0_1_e_41_qs;
19217              reg_rdata_next[10] = ie0_1_e_42_qs;
19218              reg_rdata_next[11] = ie0_1_e_43_qs;
19219              reg_rdata_next[12] = ie0_1_e_44_qs;
19220              reg_rdata_next[13] = ie0_1_e_45_qs;
19221              reg_rdata_next[14] = ie0_1_e_46_qs;
19222              reg_rdata_next[15] = ie0_1_e_47_qs;
19223              reg_rdata_next[16] = ie0_1_e_48_qs;
19224              reg_rdata_next[17] = ie0_1_e_49_qs;
19225              reg_rdata_next[18] = ie0_1_e_50_qs;
19226              reg_rdata_next[19] = ie0_1_e_51_qs;
19227              reg_rdata_next[20] = ie0_1_e_52_qs;
19228              reg_rdata_next[21] = ie0_1_e_53_qs;
19229              reg_rdata_next[22] = ie0_1_e_54_qs;
19230              reg_rdata_next[23] = ie0_1_e_55_qs;
19231              reg_rdata_next[24] = ie0_1_e_56_qs;
19232              reg_rdata_next[25] = ie0_1_e_57_qs;
19233              reg_rdata_next[26] = ie0_1_e_58_qs;
19234              reg_rdata_next[27] = ie0_1_e_59_qs;
19235              reg_rdata_next[28] = ie0_1_e_60_qs;
19236              reg_rdata_next[29] = ie0_1_e_61_qs;
19237              reg_rdata_next[30] = ie0_1_e_62_qs;
19238              reg_rdata_next[31] = ie0_1_e_63_qs;
19239            end
19240      
19241            addr_hit[194]: begin
19242              reg_rdata_next[0] = ie0_2_e_64_qs;
                   ==>
19243              reg_rdata_next[1] = ie0_2_e_65_qs;
19244              reg_rdata_next[2] = ie0_2_e_66_qs;
19245              reg_rdata_next[3] = ie0_2_e_67_qs;
19246              reg_rdata_next[4] = ie0_2_e_68_qs;
19247              reg_rdata_next[5] = ie0_2_e_69_qs;
19248              reg_rdata_next[6] = ie0_2_e_70_qs;
19249              reg_rdata_next[7] = ie0_2_e_71_qs;
19250              reg_rdata_next[8] = ie0_2_e_72_qs;
19251              reg_rdata_next[9] = ie0_2_e_73_qs;
19252              reg_rdata_next[10] = ie0_2_e_74_qs;
19253              reg_rdata_next[11] = ie0_2_e_75_qs;
19254              reg_rdata_next[12] = ie0_2_e_76_qs;
19255              reg_rdata_next[13] = ie0_2_e_77_qs;
19256              reg_rdata_next[14] = ie0_2_e_78_qs;
19257              reg_rdata_next[15] = ie0_2_e_79_qs;
19258              reg_rdata_next[16] = ie0_2_e_80_qs;
19259              reg_rdata_next[17] = ie0_2_e_81_qs;
19260              reg_rdata_next[18] = ie0_2_e_82_qs;
19261              reg_rdata_next[19] = ie0_2_e_83_qs;
19262              reg_rdata_next[20] = ie0_2_e_84_qs;
19263              reg_rdata_next[21] = ie0_2_e_85_qs;
19264              reg_rdata_next[22] = ie0_2_e_86_qs;
19265              reg_rdata_next[23] = ie0_2_e_87_qs;
19266              reg_rdata_next[24] = ie0_2_e_88_qs;
19267              reg_rdata_next[25] = ie0_2_e_89_qs;
19268              reg_rdata_next[26] = ie0_2_e_90_qs;
19269              reg_rdata_next[27] = ie0_2_e_91_qs;
19270              reg_rdata_next[28] = ie0_2_e_92_qs;
19271              reg_rdata_next[29] = ie0_2_e_93_qs;
19272              reg_rdata_next[30] = ie0_2_e_94_qs;
19273              reg_rdata_next[31] = ie0_2_e_95_qs;
19274            end
19275      
19276            addr_hit[195]: begin
19277              reg_rdata_next[0] = ie0_3_e_96_qs;
                   ==>
19278              reg_rdata_next[1] = ie0_3_e_97_qs;
19279              reg_rdata_next[2] = ie0_3_e_98_qs;
19280              reg_rdata_next[3] = ie0_3_e_99_qs;
19281              reg_rdata_next[4] = ie0_3_e_100_qs;
19282              reg_rdata_next[5] = ie0_3_e_101_qs;
19283              reg_rdata_next[6] = ie0_3_e_102_qs;
19284              reg_rdata_next[7] = ie0_3_e_103_qs;
19285              reg_rdata_next[8] = ie0_3_e_104_qs;
19286              reg_rdata_next[9] = ie0_3_e_105_qs;
19287              reg_rdata_next[10] = ie0_3_e_106_qs;
19288              reg_rdata_next[11] = ie0_3_e_107_qs;
19289              reg_rdata_next[12] = ie0_3_e_108_qs;
19290              reg_rdata_next[13] = ie0_3_e_109_qs;
19291              reg_rdata_next[14] = ie0_3_e_110_qs;
19292              reg_rdata_next[15] = ie0_3_e_111_qs;
19293              reg_rdata_next[16] = ie0_3_e_112_qs;
19294              reg_rdata_next[17] = ie0_3_e_113_qs;
19295              reg_rdata_next[18] = ie0_3_e_114_qs;
19296              reg_rdata_next[19] = ie0_3_e_115_qs;
19297              reg_rdata_next[20] = ie0_3_e_116_qs;
19298              reg_rdata_next[21] = ie0_3_e_117_qs;
19299              reg_rdata_next[22] = ie0_3_e_118_qs;
19300              reg_rdata_next[23] = ie0_3_e_119_qs;
19301              reg_rdata_next[24] = ie0_3_e_120_qs;
19302              reg_rdata_next[25] = ie0_3_e_121_qs;
19303              reg_rdata_next[26] = ie0_3_e_122_qs;
19304              reg_rdata_next[27] = ie0_3_e_123_qs;
19305              reg_rdata_next[28] = ie0_3_e_124_qs;
19306              reg_rdata_next[29] = ie0_3_e_125_qs;
19307              reg_rdata_next[30] = ie0_3_e_126_qs;
19308              reg_rdata_next[31] = ie0_3_e_127_qs;
19309            end
19310      
19311            addr_hit[196]: begin
19312              reg_rdata_next[0] = ie0_4_e_128_qs;
                   ==>
19313              reg_rdata_next[1] = ie0_4_e_129_qs;
19314              reg_rdata_next[2] = ie0_4_e_130_qs;
19315              reg_rdata_next[3] = ie0_4_e_131_qs;
19316              reg_rdata_next[4] = ie0_4_e_132_qs;
19317              reg_rdata_next[5] = ie0_4_e_133_qs;
19318              reg_rdata_next[6] = ie0_4_e_134_qs;
19319              reg_rdata_next[7] = ie0_4_e_135_qs;
19320              reg_rdata_next[8] = ie0_4_e_136_qs;
19321              reg_rdata_next[9] = ie0_4_e_137_qs;
19322              reg_rdata_next[10] = ie0_4_e_138_qs;
19323              reg_rdata_next[11] = ie0_4_e_139_qs;
19324              reg_rdata_next[12] = ie0_4_e_140_qs;
19325              reg_rdata_next[13] = ie0_4_e_141_qs;
19326              reg_rdata_next[14] = ie0_4_e_142_qs;
19327              reg_rdata_next[15] = ie0_4_e_143_qs;
19328              reg_rdata_next[16] = ie0_4_e_144_qs;
19329              reg_rdata_next[17] = ie0_4_e_145_qs;
19330              reg_rdata_next[18] = ie0_4_e_146_qs;
19331              reg_rdata_next[19] = ie0_4_e_147_qs;
19332              reg_rdata_next[20] = ie0_4_e_148_qs;
19333              reg_rdata_next[21] = ie0_4_e_149_qs;
19334              reg_rdata_next[22] = ie0_4_e_150_qs;
19335              reg_rdata_next[23] = ie0_4_e_151_qs;
19336              reg_rdata_next[24] = ie0_4_e_152_qs;
19337              reg_rdata_next[25] = ie0_4_e_153_qs;
19338              reg_rdata_next[26] = ie0_4_e_154_qs;
19339              reg_rdata_next[27] = ie0_4_e_155_qs;
19340              reg_rdata_next[28] = ie0_4_e_156_qs;
19341              reg_rdata_next[29] = ie0_4_e_157_qs;
19342              reg_rdata_next[30] = ie0_4_e_158_qs;
19343              reg_rdata_next[31] = ie0_4_e_159_qs;
19344            end
19345      
19346            addr_hit[197]: begin
19347              reg_rdata_next[0] = ie0_5_e_160_qs;
                   ==>
19348              reg_rdata_next[1] = ie0_5_e_161_qs;
19349              reg_rdata_next[2] = ie0_5_e_162_qs;
19350              reg_rdata_next[3] = ie0_5_e_163_qs;
19351              reg_rdata_next[4] = ie0_5_e_164_qs;
19352              reg_rdata_next[5] = ie0_5_e_165_qs;
19353              reg_rdata_next[6] = ie0_5_e_166_qs;
19354              reg_rdata_next[7] = ie0_5_e_167_qs;
19355              reg_rdata_next[8] = ie0_5_e_168_qs;
19356              reg_rdata_next[9] = ie0_5_e_169_qs;
19357              reg_rdata_next[10] = ie0_5_e_170_qs;
19358              reg_rdata_next[11] = ie0_5_e_171_qs;
19359              reg_rdata_next[12] = ie0_5_e_172_qs;
19360              reg_rdata_next[13] = ie0_5_e_173_qs;
19361              reg_rdata_next[14] = ie0_5_e_174_qs;
19362              reg_rdata_next[15] = ie0_5_e_175_qs;
19363              reg_rdata_next[16] = ie0_5_e_176_qs;
19364              reg_rdata_next[17] = ie0_5_e_177_qs;
19365              reg_rdata_next[18] = ie0_5_e_178_qs;
19366              reg_rdata_next[19] = ie0_5_e_179_qs;
19367              reg_rdata_next[20] = ie0_5_e_180_qs;
19368              reg_rdata_next[21] = ie0_5_e_181_qs;
19369              reg_rdata_next[22] = ie0_5_e_182_qs;
19370              reg_rdata_next[23] = ie0_5_e_183_qs;
19371              reg_rdata_next[24] = ie0_5_e_184_qs;
19372              reg_rdata_next[25] = ie0_5_e_185_qs;
19373            end
19374      
19375            addr_hit[198]: begin
19376              reg_rdata_next[1:0] = threshold0_qs;
                   ==>
19377            end
19378      
19379            addr_hit[199]: begin
19380              reg_rdata_next[7:0] = cc0_qs;
                   ==>
19381            end
19382      
19383            addr_hit[200]: begin
19384              reg_rdata_next[0] = msip0_qs;
                   ==>
19385            end
19386      
19387            addr_hit[201]: begin
19388              reg_rdata_next[0] = '0;
                   ==>
19389            end
19390      
19391            default: begin
19392              reg_rdata_next = '1;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T5,T6,T7
addr_hit[1]	Covered	T128,T275,T124
addr_hit[2]	Covered	T128,T275,T124
addr_hit[3]	Covered	T128,T275,T124
addr_hit[4]	Covered	T128,T275,T124
addr_hit[5]	Covered	T128,T275,T124
addr_hit[6]	Covered	T128,T275,T124
addr_hit[7]	Covered	T128,T275,T124
addr_hit[8]	Covered	T128,T275,T124
addr_hit[9]	Covered	T128,T275,T124
addr_hit[10]	Covered	T129,T130,T131
addr_hit[11]	Covered	T129,T130,T131
addr_hit[12]	Covered	T129,T130,T131
addr_hit[13]	Covered	T129,T130,T131
addr_hit[14]	Covered	T129,T130,T131
addr_hit[15]	Covered	T129,T130,T131
addr_hit[16]	Covered	T129,T130,T131
addr_hit[17]	Covered	T129,T130,T131
addr_hit[18]	Covered	T129,T130,T131
addr_hit[19]	Covered	T30,T275,T124
addr_hit[20]	Covered	T30,T275,T124
addr_hit[21]	Covered	T30,T275,T124
addr_hit[22]	Covered	T30,T275,T124
addr_hit[23]	Covered	T30,T275,T124
addr_hit[24]	Covered	T30,T275,T124
addr_hit[25]	Covered	T30,T275,T124
addr_hit[26]	Covered	T30,T275,T124
addr_hit[27]	Covered	T30,T275,T124
addr_hit[28]	Covered	T28,T275,T124
addr_hit[29]	Covered	T28,T275,T124
addr_hit[30]	Covered	T28,T275,T124
addr_hit[31]	Covered	T28,T275,T124
addr_hit[32]	Covered	T28,T275,T124
addr_hit[33]	Covered	T28,T275,T124
addr_hit[34]	Covered	T28,T275,T124
addr_hit[35]	Covered	T28,T275,T124
addr_hit[36]	Covered	T28,T275,T124
addr_hit[37]	Covered	T29,T275,T124
addr_hit[38]	Covered	T29,T275,T124
addr_hit[39]	Covered	T29,T275,T124
addr_hit[40]	Covered	T29,T275,T124
addr_hit[41]	Covered	T29,T275,T124
addr_hit[42]	Covered	T29,T275,T124
addr_hit[43]	Covered	T29,T275,T124
addr_hit[44]	Covered	T29,T275,T124
addr_hit[45]	Covered	T29,T275,T124
addr_hit[46]	Covered	T29,T275,T124
addr_hit[47]	Covered	T29,T275,T124
addr_hit[48]	Covered	T29,T275,T124
addr_hit[49]	Covered	T29,T275,T124
addr_hit[50]	Covered	T29,T275,T124
addr_hit[51]	Covered	T29,T275,T124
addr_hit[52]	Covered	T29,T275,T124
addr_hit[53]	Covered	T29,T275,T124
addr_hit[54]	Covered	T29,T275,T124
addr_hit[55]	Covered	T29,T275,T124
addr_hit[56]	Covered	T29,T275,T124
addr_hit[57]	Covered	T29,T275,T124
addr_hit[58]	Covered	T29,T275,T124
addr_hit[59]	Covered	T29,T275,T124
addr_hit[60]	Covered	T29,T275,T124
addr_hit[61]	Covered	T29,T275,T124
addr_hit[62]	Covered	T29,T275,T124
addr_hit[63]	Covered	T29,T275,T124
addr_hit[64]	Covered	T29,T275,T124
addr_hit[65]	Covered	T29,T275,T124
addr_hit[66]	Covered	T29,T275,T124
addr_hit[67]	Covered	T29,T275,T124
addr_hit[68]	Covered	T29,T275,T124
addr_hit[69]	Covered	T29,T15,T12
addr_hit[70]	Covered	T15,T275,T124
addr_hit[71]	Covered	T15,T275,T124
addr_hit[72]	Covered	T15,T12,T13
addr_hit[73]	Covered	T15,T12,T13
addr_hit[74]	Covered	T15,T275,T124
addr_hit[75]	Covered	T275,T124,T328
addr_hit[76]	Covered	T275,T124,T328
addr_hit[77]	Covered	T59,T275,T124
addr_hit[78]	Covered	T59,T275,T124
addr_hit[79]	Covered	T275,T124,T328
addr_hit[80]	Covered	T59,T275,T124
addr_hit[81]	Covered	T59,T275,T124
addr_hit[82]	Covered	T59,T275,T124
addr_hit[83]	Covered	T59,T275,T124
addr_hit[84]	Covered	T59,T275,T124
addr_hit[85]	Covered	T275,T124,T328
addr_hit[86]	Covered	T59,T275,T124
addr_hit[87]	Covered	T275,T124,T328
addr_hit[88]	Covered	T275,T124,T328
addr_hit[89]	Covered	T275,T124,T328
addr_hit[90]	Covered	T275,T124,T328
addr_hit[91]	Covered	T275,T124,T328
addr_hit[92]	Covered	T61,T275,T124
addr_hit[93]	Covered	T61,T275,T124
addr_hit[94]	Covered	T275,T124,T328
addr_hit[95]	Covered	T61,T275,T124
addr_hit[96]	Covered	T61,T275,T124
addr_hit[97]	Covered	T61,T275,T124
addr_hit[98]	Covered	T61,T275,T124
addr_hit[99]	Covered	T61,T275,T124
addr_hit[100]	Covered	T275,T124,T328
addr_hit[101]	Covered	T61,T62,T275
addr_hit[102]	Covered	T62,T275,T124
addr_hit[103]	Covered	T275,T124,T328
addr_hit[104]	Covered	T62,T275,T124
addr_hit[105]	Covered	T62,T275,T124
addr_hit[106]	Covered	T62,T275,T124
addr_hit[107]	Covered	T63,T275,T124
addr_hit[108]	Covered	T63,T275,T124
addr_hit[109]	Covered	T275,T124,T328
addr_hit[110]	Covered	T63,T275,T124
addr_hit[111]	Covered	T63,T275,T124
addr_hit[112]	Covered	T63,T275,T124
addr_hit[113]	Covered	T63,T275,T124
addr_hit[114]	Covered	T63,T275,T124
addr_hit[115]	Covered	T275,T124,T328
addr_hit[116]	Covered	T63,T275,T124
addr_hit[117]	Covered	T275,T124,T328
addr_hit[118]	Covered	T275,T124,T328
addr_hit[119]	Covered	T275,T124,T328
addr_hit[120]	Covered	T275,T124,T328
addr_hit[121]	Covered	T275,T124,T328
addr_hit[122]	Covered	T32,T275,T124
addr_hit[123]	Covered	T32,T275,T124
addr_hit[124]	Covered	T275,T124,T328
addr_hit[125]	Covered	T275,T124,T328
addr_hit[126]	Covered	T275,T124,T328
addr_hit[127]	Covered	T46,T47,T82
addr_hit[128]	Covered	T46,T47,T82
addr_hit[129]	Covered	T46,T47,T82
addr_hit[130]	Covered	T46,T47,T82
addr_hit[131]	Covered	T12,T13,T275
addr_hit[132]	Covered	T12,T13,T275
addr_hit[133]	Covered	T275,T124,T328
addr_hit[134]	Covered	T275,T124,T328
addr_hit[135]	Covered	T275,T124,T328
addr_hit[136]	Covered	T275,T124,T328
addr_hit[137]	Covered	T275,T124,T328
addr_hit[138]	Covered	T275,T124,T328
addr_hit[139]	Covered	T275,T124,T328
addr_hit[140]	Covered	T275,T124,T328
addr_hit[141]	Covered	T275,T124,T328
addr_hit[142]	Covered	T275,T124,T328
addr_hit[143]	Covered	T275,T124,T328
addr_hit[144]	Covered	T275,T124,T328
addr_hit[145]	Covered	T275,T124,T328
addr_hit[146]	Covered	T275,T124,T328
addr_hit[147]	Covered	T275,T124,T328
addr_hit[148]	Covered	T275,T124,T328
addr_hit[149]	Covered	T275,T124,T328
addr_hit[150]	Covered	T275,T124,T328
addr_hit[151]	Covered	T275,T124,T328
addr_hit[152]	Covered	T275,T124,T328
addr_hit[153]	Covered	T6,T7,T329
addr_hit[154]	Covered	T67,T275,T124
addr_hit[155]	Covered	T139,T275,T124
addr_hit[156]	Covered	T46,T47,T82
addr_hit[157]	Covered	T46,T257,T47
addr_hit[158]	Covered	T179,T275,T124
addr_hit[159]	Covered	T275,T124,T328
addr_hit[160]	Covered	T5,T146,T330
addr_hit[161]	Covered	T5,T146,T330
addr_hit[162]	Covered	T5,T146,T330
addr_hit[163]	Covered	T5,T146,T330
addr_hit[164]	Covered	T5,T146,T330
addr_hit[165]	Covered	T275,T124,T328
addr_hit[166]	Covered	T331,T332,T275
addr_hit[167]	Covered	T331,T332,T275
addr_hit[168]	Covered	T275,T124,T328
addr_hit[169]	Covered	T275,T124,T328
addr_hit[170]	Covered	T275,T124,T328
addr_hit[171]	Covered	T275,T124,T328
addr_hit[172]	Covered	T161,T275,T124
addr_hit[173]	Covered	T275,T124,T328
addr_hit[174]	Covered	T275,T124,T328
addr_hit[175]	Covered	T275,T124,T328
addr_hit[176]	Covered	T275,T124,T328
addr_hit[177]	Covered	T275,T124,T328
addr_hit[178]	Covered	T275,T124,T328
addr_hit[179]	Covered	T275,T124,T328
addr_hit[180]	Covered	T275,T124,T328
addr_hit[181]	Covered	T275,T124,T328
addr_hit[182]	Covered	T275,T124,T328
addr_hit[183]	Covered	T275,T124,T328
addr_hit[184]	Covered	T275,T124,T328
addr_hit[185]	Covered	T275,T124,T328
addr_hit[186]	Covered	T415,T169,T569
addr_hit[187]	Covered	T415,T169,T569
addr_hit[188]	Covered	T415,T169,T569
addr_hit[189]	Covered	T415,T169,T569
addr_hit[190]	Covered	T329,T700,T701
addr_hit[191]	Covered	T415,T169,T569
addr_hit[192]	Covered	T30,T28,T128
addr_hit[193]	Covered	T28,T29,T275
addr_hit[194]	Covered	T29,T15,T12
addr_hit[195]	Covered	T32,T46,T47
addr_hit[196]	Covered	T6,T7,T46
addr_hit[197]	Covered	T5,T146,T330
addr_hit[198]	Covered	T5,T6,T7
addr_hit[199]	Covered	T5,T6,T7
addr_hit[200]	Covered	T275,T69,T276
addr_hit[201]	Covered	T75,T76,T77
default	Covered	T91,T92,T97

Assert Coverage for Module : rv_plic_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	587217096	166865	0	0
reAfterRv	587217096	166865	0	0
rePulse	587217096	97718	0	0
wePulse	587217096	69147	0	0

en2addrHit

Name	Attempts	Real Successes
Total	587217096	166865
T5	96811	34
T6	127653	18
T7	104030	10
T11	107789	0
T25	193688	0
T28	0	46
T29	0	228
T30	217319	46
T32	103615	11
T46	265130	44
T118	89428	0
T119	82700	0
T128	0	46
T257	0	6

reAfterRv

Name	Attempts	Real Successes
Total	587217096	166865
T5	96811	34
T6	127653	18
T7	104030	10
T11	107789	0
T25	193688	0
T28	0	46
T29	0	228
T30	217319	46
T32	103615	11
T46	265130	44
T118	89428	0
T119	82700	0
T128	0	46
T257	0	6

rePulse

Name	Attempts	Real Successes
Total	587217096	97718
T5	96811	14
T6	127653	8
T7	104030	4
T11	107789	0
T25	193688	0
T28	0	18
T29	0	97
T30	217319	18
T32	103615	4
T46	265130	14
T118	89428	0
T119	82700	0
T128	0	18
T257	0	2

wePulse

Name	Attempts	Real Successes
Total	587217096	69147
T5	96811	20
T6	127653	10
T7	104030	6
T11	107789	0
T25	193688	0
T28	0	28
T29	0	131
T30	217319	28
T32	103615	7
T46	265130	30
T118	89428	0
T119	82700	0
T128	0	28
T257	0	4

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.98	100.00	99.90			100.00	100.00

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_plic.u_reg	99.98	100.00	99.90			100.00	100.00