Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T30,T128,T129	Yes	T30,T128,T129	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T30,T128,T129	Yes	T30,T128,T129	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	INPUT
tl_i.a_valid	Yes	Yes	T30,T28,T128	Yes	T30,T28,T128	INPUT
tl_o.a_ready	Yes	Yes	T30,T28,T128	Yes	T30,T28,T128	OUTPUT
tl_o.d_error	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T30,T128,T129	Yes	T30,T128,T129	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T30,T128,T129	Yes	T30,T28,T128	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T30,T128,T129	Yes	T30,T28,T128	OUTPUT
tl_o.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T95,*T277,*T278	Yes	T95,T277,T278	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T30,*T128,*T129	Yes	T30,T128,T129	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T30,T28,T128	Yes	T30,T28,T128	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T47,T99,T75	Yes	T47,T99,T75	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T99,T75,T100	Yes	T99,T100,T101	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T99,T100,T101	Yes	T99,T75,T100	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T47,T99,T75	Yes	T47,T99,T75	OUTPUT
cio_rx_i	Yes	Yes	T46,T30,T128	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T30,T128,T129	Yes	T30,T128,T129	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T30,T128,T129	Yes	T30,T128,T129	OUTPUT
intr_tx_empty_o	Yes	Yes	T30,T128,T129	Yes	T30,T128,T129	OUTPUT
intr_rx_watermark_o	Yes	Yes	T30,T128,T129	Yes	T30,T128,T129	OUTPUT
intr_tx_done_o	Yes	Yes	T30,T128,T129	Yes	T30,T128,T129	OUTPUT
intr_rx_overflow_o	Yes	Yes	T30,T128,T129	Yes	T30,T128,T129	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T328,T336,T337	Yes	T328,T336,T337	OUTPUT
intr_rx_break_err_o	Yes	Yes	T328,T336,T337	Yes	T328,T336,T337	OUTPUT
intr_rx_timeout_o	Yes	Yes	T328,T336,T337	Yes	T328,T336,T337	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T328,T336,T337	Yes	T328,T336,T337	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T128,T224,T328	Yes	T128,T224,T328	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T128,T224,T328	Yes	T128,T224,T328	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	INPUT
tl_i.a_valid	Yes	Yes	T128,T75,T224	Yes	T128,T75,T224	INPUT
tl_o.a_ready	Yes	Yes	T128,T75,T192	Yes	T128,T75,T192	OUTPUT
tl_o.d_error	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T128,T328,T333	Yes	T128,T328,T333	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T128,T192,T328	Yes	T128,T75,T192	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T128,T192,T328	Yes	T128,T75,T192	OUTPUT
tl_o.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T95,*T277,*T278	Yes	T95,T277,T278	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T97,T98	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T128,*T328,*T333	Yes	T128,T328,T333	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T128,T75,T192	Yes	T128,T75,T192	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T99,T75,T192	Yes	T99,T75,T192	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T99,T75,T192	Yes	T99,T75,T192	OUTPUT
cio_rx_i	Yes	Yes	T46,T128,T47	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T128,T55,T56	Yes	T128,T55,T56	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T128,T328,T333	Yes	T128,T328,T333	OUTPUT
intr_tx_empty_o	Yes	Yes	T128,T328,T95	Yes	T128,T328,T95	OUTPUT
intr_rx_watermark_o	Yes	Yes	T128,T328,T334	Yes	T128,T328,T334	OUTPUT
intr_tx_done_o	Yes	Yes	T128,T328,T335	Yes	T128,T328,T335	OUTPUT
intr_rx_overflow_o	Yes	Yes	T128,T328,T335	Yes	T128,T328,T335	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T328,T336,T337	Yes	T328,T336,T337	OUTPUT
intr_rx_break_err_o	Yes	Yes	T328,T336,T337	Yes	T328,T336,T337	OUTPUT
intr_rx_timeout_o	Yes	Yes	T328,T336,T337	Yes	T328,T336,T337	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T328,T336,T337	Yes	T328,T336,T337	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	INPUT
tl_i.a_valid	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	INPUT
tl_o.a_ready	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	OUTPUT
tl_o.d_error	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	OUTPUT
tl_o.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T95,*T70,*T92	Yes	T95,T70,T91	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T129,*T130,*T131	Yes	T129,T130,T131	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T99,T75,T192	Yes	T99,T75,T192	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T99,T75,T100	Yes	T99,T100,T101	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T99,T100,T101	Yes	T99,T75,T100	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T99,T75,T192	Yes	T99,T75,T192	OUTPUT
cio_rx_i	Yes	Yes	T129,T130,T131	Yes	T8,T11,T129	INPUT
cio_tx_o	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	OUTPUT
intr_tx_empty_o	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	OUTPUT
intr_rx_watermark_o	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	OUTPUT
intr_tx_done_o	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	OUTPUT
intr_rx_overflow_o	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T328,T336,T337	Yes	T328,T336,T337	OUTPUT
intr_rx_break_err_o	Yes	Yes	T328,T336,T337	Yes	T328,T336,T337	OUTPUT
intr_rx_timeout_o	Yes	Yes	T328,T336,T337	Yes	T328,T336,T337	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T328,T336,T337	Yes	T328,T336,T337	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T30,T328,T14	Yes	T30,T328,T14	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T30,T328,T14	Yes	T30,T328,T14	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	INPUT
tl_i.a_valid	Yes	Yes	T30,T75,T192	Yes	T30,T75,T192	INPUT
tl_o.a_ready	Yes	Yes	T30,T75,T192	Yes	T30,T75,T192	OUTPUT
tl_o.d_error	Yes	Yes	T97,T98,T162	Yes	T97,T98,T162	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T30,T328,T14	Yes	T30,T328,T14	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T30,T192,T328	Yes	T30,T75,T192	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T30,T192,T328	Yes	T30,T75,T192	OUTPUT
tl_o.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T95,*T70,*T97	Yes	T95,T70,T91	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T30,*T328,*T14	Yes	T30,T328,T14	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T30,T75,T192	Yes	T30,T75,T192	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T47,T99,T75	Yes	T47,T99,T75	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T47,T99,T75	Yes	T47,T99,T75	OUTPUT
cio_rx_i	Yes	Yes	T30,T65,T132	Yes	T30,T65,T132	INPUT
cio_tx_o	Yes	Yes	T30,T65,T132	Yes	T30,T65,T132	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T30,T328,T65	Yes	T30,T328,T65	OUTPUT
intr_tx_empty_o	Yes	Yes	T30,T328,T95	Yes	T30,T328,T95	OUTPUT
intr_rx_watermark_o	Yes	Yes	T30,T328,T65	Yes	T30,T328,T65	OUTPUT
intr_tx_done_o	Yes	Yes	T30,T328,T65	Yes	T30,T328,T65	OUTPUT
intr_rx_overflow_o	Yes	Yes	T30,T328,T65	Yes	T30,T328,T65	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T328,T336,T337	Yes	T328,T336,T337	OUTPUT
intr_rx_break_err_o	Yes	Yes	T328,T336,T337	Yes	T328,T336,T337	OUTPUT
intr_rx_timeout_o	Yes	Yes	T328,T336,T337	Yes	T328,T336,T337	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T328,T336,T337	Yes	T328,T336,T337	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T28,T328,T66	Yes	T28,T328,T66	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T28,T328,T66	Yes	T28,T328,T66	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	INPUT
tl_i.a_valid	Yes	Yes	T28,T75,T192	Yes	T28,T75,T192	INPUT
tl_o.a_ready	Yes	Yes	T28,T75,T192	Yes	T28,T75,T192	OUTPUT
tl_o.d_error	Yes	Yes	T91,T92,T93	Yes	T91,T92,T97	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T28,T328,T66	Yes	T28,T328,T66	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T28,T192,T328	Yes	T28,T75,T192	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T28,T192,T328	Yes	T28,T75,T192	OUTPUT
tl_o.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T95,*T70,*T91	Yes	T95,T70,T91	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T93	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T28,*T328,*T66	Yes	T28,T328,T66	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T28,T75,T192	Yes	T28,T75,T192	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T99,T75,T192	Yes	T99,T75,T192	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T99,T75,T192	Yes	T99,T75,T192	OUTPUT
cio_rx_i	Yes	Yes	T28,T66,T133	Yes	T28,T66,T133	INPUT
cio_tx_o	Yes	Yes	T28,T66,T133	Yes	T28,T66,T133	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T28,T328,T66	Yes	T28,T328,T66	OUTPUT
intr_tx_empty_o	Yes	Yes	T28,T328,T66	Yes	T28,T328,T66	OUTPUT
intr_rx_watermark_o	Yes	Yes	T28,T328,T66	Yes	T28,T328,T66	OUTPUT
intr_tx_done_o	Yes	Yes	T28,T328,T66	Yes	T28,T328,T66	OUTPUT
intr_rx_overflow_o	Yes	Yes	T28,T328,T66	Yes	T28,T328,T66	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T328,T336,T337	Yes	T328,T336,T337	OUTPUT
intr_rx_break_err_o	Yes	Yes	T328,T336,T337	Yes	T328,T336,T337	OUTPUT
intr_rx_timeout_o	Yes	Yes	T328,T336,T337	Yes	T328,T336,T337	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T328,T336,T337	Yes	T328,T336,T337	OUTPUT

*Tests covering at least one bit in the range