Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T97,T272,T273	Yes	T91,T92,T93	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T98,T274,T273	Yes	T98,T274,T273	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T47,T211,T238	Yes	T47,T211,T238	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T46,T47,T211	Yes	T46,T47,T211	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T95,T97,T162	Yes	T95,T97,T162	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T95,T91,T92	Yes	T95,T91,T92	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T46,T47,T239	Yes	T46,T47,T239	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T46,T47,T41	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T35,T94,T37	Yes	T35,T94,T37	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T46,T47,T41	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T46,T47,T41	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T35,T94,T37	Yes	T35,T94,T37	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T46,T47,T41	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T35,T94,T37	Yes	T35,T94,T37	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T35,T94,T37	Yes	T35,T94,T37	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T35,T37,T88	Yes	T35,T37,T88	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T35,T94,T37	Yes	T35,T94,T37	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T35,*T94,*T37	Yes	T35,T94,T37	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T35,T94,T37	Yes	T35,T94,T37	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T70,T91,T92	Yes	T70,T91,T92	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T70,T91,T92	Yes	T70,T91,T92	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T70,T91,T92	Yes	T70,T91,T92	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T70,T92,T97	Yes	T70,T92,T97	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T70,T91,T92	Yes	T70,T91,T92	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T70,T91,*T92	Yes	T70,T91,T92	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T70,T91,T92	Yes	T70,T91,T92	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T70,T97,T272	Yes	T70,T91,T92	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T91,T97,T98	Yes	T91,T97,T98	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T70,T91,T92	Yes	T70,T91,T92	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T70,T91,T92	Yes	T70,T91,T92	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T70,T91,T92	Yes	T70,T91,T92	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T91,T97,T98	Yes	T91,T92,T97	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T70,T91,T97	Yes	T70,T91,T92	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T70,*T91,*T97	Yes	T70,T91,T92	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T70,T91,T92	Yes	T70,T91,T92	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T94,T277,T278	Yes	T94,T277,T278	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T94,T277,T278	Yes	T94,T277,T278	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T94,T277,T278	Yes	T94,T277,T278	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T94,T277,T278	Yes	T94,T277,T278	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T94,T277,T278	Yes	T94,T277,T278	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T94,*T277,*T278	Yes	T94,T277,T278	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T94,T277,T278	Yes	T94,T277,T278	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T46,T47,T41	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T94,T277,T278	Yes	T94,T277,T278	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T94,T277,T278	Yes	T94,T277,T278	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T46,T47,T41	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T94,*T277,*T278	Yes	T94,T277,T278	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T46,T47,T41	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T94,T277,T278	Yes	T94,T277,T278	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T203,T422	Yes	T1,T203,T422	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T203,T422,T40	Yes	T203,T422,T40	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T75,T76,T70	Yes	T75,T76,T70	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T75,T423,T292	Yes	T75,T423,T292	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T75,T423,T292	Yes	T75,T423,T292	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T75,T76,T70	Yes	T75,T76,T70	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T75,T423,T292	Yes	T75,T423,T292	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T70,*T91,T92	Yes	T70,T91,T92	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T75,T423,T292	Yes	T75,T423,T292	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T75,T423,T292	Yes	T75,T423,T292	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T423,T292,T424	Yes	T423,T292,T424	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T70,T92,T97	Yes	T75,T76,T70	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T423,T292,T424	Yes	T75,T423,T292	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T70,T92,T97	Yes	T70,T91,T92	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T292,*T425,*T70	Yes	T423,T292,T424	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T75,T423,T292	Yes	T75,T423,T292	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T82,T301,T716	Yes	T82,T301,T716	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T91,*T92,*T97	Yes	T91,T92,T97	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T12,T226,T228	Yes	T12,T226,T228	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T91,*T97,*T98	Yes	T91,T92,T97	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T11,*T12,*T13	Yes	T11,T12,T13	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T408,T75,T124	Yes	T408,T75,T124	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T408,T75,T124	Yes	T408,T75,T124	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T408,T75,T124	Yes	T408,T75,T124	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T408,T75,T124	Yes	T408,T75,T124	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T408,T75,T124	Yes	T408,T75,T124	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T408,T75,T124	Yes	T408,T75,T124	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T91,*T92,*T97	Yes	T91,T92,T97	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T91,T97,T98	Yes	T91,T97,T98	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T408,T75,T124	Yes	T408,T75,T124	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T408,T75,T124	Yes	T408,T75,T124	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T91,T97,T98	Yes	T91,T97,T98	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T408,T124,T14	Yes	T408,T124,T14	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T408,T124,T333	Yes	T408,T75,T124	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T408,T124,T14	Yes	T408,T124,T14	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T97,T98,T162	Yes	T91,T97,T98	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T97,*T98,*T274	Yes	T91,T97,T98	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T91,T97,T98	Yes	T91,T97,T98	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T408,*T124,*T333	Yes	T408,T124,T333	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T408,T75,T124	Yes	T408,T75,T124	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T4,T9,T10	Yes	T4,T9,T10	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T4,T9,T10	Yes	T4,T9,T10	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T95,*T70,*T91	Yes	T95,T70,T91	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T91,T97,T98	Yes	T91,T97,T98	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T91,T97,T98	Yes	T91,T97,T98	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	INPUT
tl_usbdev_i.d_error	Yes	Yes	T92,T97,T98	Yes	T97,T98,T274	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T4,T9,T10	Yes	T2,T4,T9	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T4,T9	Yes	T4,T9,T10	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T2,T4,T9	Yes	T4,T9,T10	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T97,T98	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T95,*T70,*T97	Yes	T95,T70,T97	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T91,T97,T98	Yes	T97,T98,T274	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T4,*T9,*T10	Yes	T4,T9,T10	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T2,T4,T9	Yes	T2,T4,T9	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T95,*T231,*T91	Yes	T95,T231,T91	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T8,T25,T46	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T8,T5,T25	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T93,T97	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T95,*T231,*T91	Yes	T95,T231,T91	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T95,T231,T91	Yes	T95,T231,T91	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T95,T231,T91	Yes	T95,T231,T91	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T95,T231,T91	Yes	T95,T231,T91	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T95,T231,T91	Yes	T95,T231,T91	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T95,T231,T97	Yes	T95,T231,T97	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T95,*T231,T91	Yes	T95,T231,T91	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T95,T231,T91	Yes	T95,T231,T91	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T95,T231,T97	Yes	T95,T231,T91	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T91,T97,T98	Yes	T91,T92,T97	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T95,T231,T91	Yes	T95,T231,T91	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T95,T231,T91	Yes	T95,T231,T91	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T95,T231,T91	Yes	T95,T231,T91	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T91,T97,T98	Yes	T91,T92,T93	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T95,*T231,T91	Yes	T95,T231,T91	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T91,T93,T97	Yes	T91,T92,T97	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T95,*T231,*T91	Yes	T95,T231,T91	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T95,T231,T91	Yes	T95,T231,T91	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T3,T4,T102	Yes	T3,T4,T102	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T8,T25,T46	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T91,*T92,*T93	Yes	T91,T92,T93	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_hmac_o.d_ready	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T75,T708,T331	Yes	T75,T708,T331	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T75,T708,T331	Yes	T75,T708,T331	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T75,T708,T331	Yes	T75,T708,T331	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T75,T708,T331	Yes	T75,T708,T331	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T75,T708,T331	Yes	T75,T708,T331	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T95,*T231,*T91	Yes	T95,T231,T91	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T708,T331,T332	Yes	T708,T331,T332	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T75,T708,T331	Yes	T75,T708,T331	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T75,T708,T331	Yes	T75,T708,T331	INPUT
tl_hmac_i.d_error	Yes	Yes	T92,T97,T98	Yes	T92,T93,T97	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T708,T331,T332	Yes	T708,T331,T332	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T708,T331,T332	Yes	T708,T331,T332	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T75,T708,T331	Yes	T708,T331,T332	INPUT
tl_hmac_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T95,*T231,*T97	Yes	T95,T231,T91	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T75,*T708,*T331	Yes	T708,T331,T332	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T75,T708,T331	Yes	T75,T708,T331	INPUT
tl_kmac_o.d_ready	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T119,T75,T462	Yes	T119,T75,T462	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T119,T188,T202	Yes	T119,T188,T202	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T119,T188,T202	Yes	T119,T188,T202	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T119,T75,T462	Yes	T119,T75,T462	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T119,T188,T202	Yes	T119,T188,T202	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T95,*T231,*T91	Yes	T95,T231,T91	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T119,T462,T463	Yes	T119,T462,T463	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T119,T188,T202	Yes	T119,T188,T202	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T119,T188,T202	Yes	T119,T188,T202	INPUT
tl_kmac_i.d_error	Yes	Yes	T91,T97,T98	Yes	T91,T97,T98	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T119,T188,T202	Yes	T119,T188,T202	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T119,T188,T202	Yes	T119,T188,T202	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T119,T188,T202	Yes	T119,T202,T205	INPUT
tl_kmac_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T95,*T231,*T91	Yes	T95,T231,T91	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T91,T97,T98	Yes	T91,T92,T97	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T119,*T188,*T202	Yes	T119,T202,T205	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T119,T188,T202	Yes	T119,T188,T202	INPUT
tl_aes_o.d_ready	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T705,T706,T288	Yes	T705,T706,T288	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T705,T706,T288	Yes	T705,T706,T288	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T705,T706,T288	Yes	T705,T706,T288	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T705,T706,T288	Yes	T705,T706,T288	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T705,T706,T288	Yes	T705,T706,T288	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T91,*T92,*T97	Yes	T91,T92,T97	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T705,T706,T288	Yes	T705,T706,T288	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T705,T706,T288	Yes	T705,T706,T288	INPUT
tl_aes_i.d_error	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T705,T706,T288	Yes	T705,T706,T288	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T705,T706,T288	Yes	T705,T706,T288	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T705,T706,T288	Yes	T705,T706,T288	INPUT
tl_aes_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T92,*T97,*T98	Yes	T91,T92,T97	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T705,*T706,*T288	Yes	T705,T706,T288	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T705,T706,T288	Yes	T705,T706,T288	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T95,*T231,*T91	Yes	T95,T231,T91	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T97,T98,T162	Yes	T97,T98,T162	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T159,T160,T161	Yes	T159,T160,T161	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T97,T98	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T95,*T231,*T97	Yes	T95,T231,T91	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T97,T98	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T159,*T160,*T161	Yes	T159,T160,T161	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T290,T75,T159	Yes	T290,T75,T159	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T95,*T231,*T91	Yes	T95,T231,T91	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T91,T92,T97	Yes	T91,T92,T93	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T290,T159,T401	Yes	T290,T159,T401	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T91,T97,T98	Yes	T91,T92,T93	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T95,*T231,*T97	Yes	T95,T231,T91	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T97	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T290,*T159,*T401	Yes	T290,T159,T401	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T290,T75,T159	Yes	T290,T75,T159	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T290,T75,T159	Yes	T290,T75,T159	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T95,*T231,*T91	Yes	T95,T231,T91	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T91,T97,T98	Yes	T91,T97,T98	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T290,T159,T161	Yes	T290,T159,T161	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T95,*T231,*T97	Yes	T95,T231,T91	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T91,T97,T98	Yes	T97,T98,T274	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T290,*T159,*T161	Yes	T290,T159,T161	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T75,T159,T161	Yes	T75,T159,T161	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T75,T159,T161	Yes	T75,T159,T161	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T75,T159,T161	Yes	T75,T159,T161	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T75,T159,T161	Yes	T75,T159,T161	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T75,T159,T161	Yes	T75,T159,T161	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T95,*T231,*T91	Yes	T95,T231,T91	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T75,T159,T161	Yes	T75,T159,T161	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T75,T159,T161	Yes	T75,T159,T161	INPUT
tl_edn1_i.d_error	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T159,T161,T156	Yes	T159,T161,T156	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T161,T156,T157	Yes	T75,T159,T161	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T161,T156,T157	Yes	T75,T159,T161	INPUT
tl_edn1_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T95,*T231,*T97	Yes	T95,T231,T91	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T91,T97,T98	Yes	T91,T92,T97	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T159,*T161,*T156	Yes	T159,T161,T156	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T75,T159,T161	Yes	T75,T159,T161	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T8,T5,T6	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T91,*T92,*T97	Yes	T91,T92,T97	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T91,T97,T98	Yes	T91,T97,T98	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T91,*T97,*T98	Yes	T91,T92,T97	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tl_otbn_o.d_ready	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T215,T75,T161	Yes	T215,T75,T161	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T215,T75,T161	Yes	T215,T75,T161	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T215,T75,T161	Yes	T215,T75,T161	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T215,T75,T161	Yes	T215,T75,T161	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T215,T75,T161	Yes	T215,T75,T161	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T40,*T96,*T230	Yes	T40,T96,T230	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T215,T75,T161	Yes	T215,T75,T161	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T215,T75,T161	Yes	T215,T75,T161	INPUT
tl_otbn_i.d_error	Yes	Yes	T91,T97,T98	Yes	T91,T92,T97	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T215,T161,T157	Yes	T215,T161,T157	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T215,T161,T157	Yes	T215,T161,T157	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T215,T75,T161	Yes	T215,T161,T157	INPUT
tl_otbn_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T40,*T96,*T230	Yes	T40,T96,T230	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T215,*T75,*T161	Yes	T215,T161,T157	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T215,T75,T161	Yes	T215,T75,T161	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T202,T205,T206	Yes	T202,T205,T206	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T188,T202,T205	Yes	T188,T202,T205	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T188,T202,T205	Yes	T188,T202,T205	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T202,T205,T206	Yes	T202,T205,T206	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T188,T202,T205	Yes	T188,T202,T205	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T95,*T231,*T91	Yes	T95,T231,T91	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T91,T97,T98	Yes	T91,T97,T98	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T91,T97,T98	Yes	T91,T97,T98	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T188,T202,T205	Yes	T188,T202,T205	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T188,T202,T205	Yes	T188,T202,T205	INPUT
tl_keymgr_i.d_error	Yes	Yes	T91,T92,T97	Yes	T91,T92,T93	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T202,T205,T206	Yes	T202,T205,T206	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T202,T205,T206	Yes	T202,T205,T206	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T202,T205,T206	Yes	T202,T205,T206	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T93	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T95,*T231,*T91	Yes	T95,T231,T91	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T93	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T202,*T205,*T206	Yes	T188,T202,T205	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T188,T202,T205	Yes	T188,T202,T205	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T277,*T278,*T70	Yes	T277,T278,T70	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T70,T91,T93	Yes	T70,T91,T98	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T8,T5,T6	Yes	T8,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T8,T5,T6	Yes	T8,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T70,*T97,*T98	Yes	T277,T278,T70	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T75,T209,T211	Yes	T75,T209,T211	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T75,T209,T211	Yes	T75,T209,T211	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T75,T209,T211	Yes	T75,T209,T211	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T75,T209,T211	Yes	T75,T209,T211	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T75,T209,T211	Yes	T75,T209,T211	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T455,*T456,*T91	Yes	T455,T456,T91	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T75,T209,T211	Yes	T75,T209,T211	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T75,T209,T211	Yes	T75,T209,T211	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T92,T97,T98	Yes	T91,T92,T97	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T211,T321,T322	Yes	T211,T321,T322	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T209,T211,T149	Yes	T75,T209,T211	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T209,T211,T149	Yes	T75,T209,T211	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T92,T97,T98	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T97,*T98,*T162	Yes	T455,T456,T91	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T92,T97,T98	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T209,*T211,*T149	Yes	T209,T211,T149	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T75,T209,T211	Yes	T75,T209,T211	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T8,T25,T46	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range