Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T82,T301,T716	Yes	T82,T301,T716	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T128,T224,T328	Yes	T128,T224,T328	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T128,T224,T328	Yes	T128,T224,T328	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T128,T75,T224	Yes	T128,T75,T224	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T128,T75,T192	Yes	T128,T75,T192	INPUT
tl_uart0_i.d_error	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T128,T328,T333	Yes	T128,T328,T333	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T128,T192,T328	Yes	T128,T75,T192	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T128,T192,T328	Yes	T128,T75,T192	INPUT
tl_uart0_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T95,*T277,*T278	Yes	T95,T277,T278	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T97,T98	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T128,*T328,*T333	Yes	T128,T328,T333	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T128,T75,T192	Yes	T128,T75,T192	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	INPUT
tl_uart1_i.d_error	Yes	Yes	T92,T93,T97	Yes	T92,T93,T97	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	INPUT
tl_uart1_i.d_sink	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T95,*T70,*T92	Yes	T95,T70,T91	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T129,*T130,*T131	Yes	T129,T130,T131	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T129,T130,T131	Yes	T129,T130,T131	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T30,T328,T14	Yes	T30,T328,T14	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T30,T328,T14	Yes	T30,T328,T14	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T30,T75,T192	Yes	T30,T75,T192	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T30,T75,T192	Yes	T30,T75,T192	INPUT
tl_uart2_i.d_error	Yes	Yes	T97,T98,T162	Yes	T97,T98,T162	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T30,T328,T14	Yes	T30,T328,T14	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T30,T192,T328	Yes	T30,T75,T192	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T30,T192,T328	Yes	T30,T75,T192	INPUT
tl_uart2_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T95,*T70,*T97	Yes	T95,T70,T91	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T30,*T328,*T14	Yes	T30,T328,T14	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T30,T75,T192	Yes	T30,T75,T192	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T28,T328,T66	Yes	T28,T328,T66	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T28,T328,T66	Yes	T28,T328,T66	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T28,T75,T192	Yes	T28,T75,T192	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T28,T75,T192	Yes	T28,T75,T192	INPUT
tl_uart3_i.d_error	Yes	Yes	T91,T92,T93	Yes	T91,T92,T97	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T28,T328,T66	Yes	T28,T328,T66	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T28,T192,T328	Yes	T28,T75,T192	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T28,T192,T328	Yes	T28,T75,T192	INPUT
tl_uart3_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T95,*T70,*T91	Yes	T95,T70,T91	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T93	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T28,*T328,*T66	Yes	T28,T328,T66	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T28,T75,T192	Yes	T28,T75,T192	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T59,T408,T338	Yes	T59,T408,T338	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T59,T408,T338	Yes	T59,T408,T338	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T59,T408,T75	Yes	T59,T408,T75	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T59,T408,T75	Yes	T59,T408,T75	INPUT
tl_i2c0_i.d_error	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T59,T338,T14	Yes	T59,T338,T14	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T59,T408,T192	Yes	T59,T408,T75	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T59,T408,T192	Yes	T59,T408,T75	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T95,*T231,*T91	Yes	T95,T231,T91	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T59,*T408,*T338	Yes	T59,T408,T338	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T59,T408,T75	Yes	T59,T408,T75	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T61,T62,T408	Yes	T61,T62,T408	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T61,T62,T408	Yes	T61,T62,T408	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T61,T62,T408	Yes	T61,T62,T408	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T61,T62,T408	Yes	T61,T62,T408	INPUT
tl_i2c1_i.d_error	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T61,T62,T338	Yes	T61,T62,T338	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T61,T62,T408	Yes	T61,T62,T408	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T61,T62,T408	Yes	T61,T62,T408	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T91,T97,T98	Yes	T91,T97,T98	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T95,*T231,*T92	Yes	T95,T231,T91	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T61,*T62,*T408	Yes	T61,T62,T408	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T61,T62,T408	Yes	T61,T62,T408	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T408,T63,T338	Yes	T408,T63,T338	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T408,T63,T338	Yes	T408,T63,T338	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T408,T63,T75	Yes	T408,T63,T75	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T408,T63,T75	Yes	T408,T63,T75	INPUT
tl_i2c2_i.d_error	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T63,T338,T14	Yes	T63,T338,T14	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T408,T63,T192	Yes	T408,T63,T75	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T408,T63,T192	Yes	T408,T63,T75	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T95,*T231,*T97	Yes	T95,T231,T91	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T408,*T63,*T338	Yes	T408,T63,T338	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T408,T63,T75	Yes	T408,T63,T75	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T32,T124,T14	Yes	T32,T124,T14	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T32,T124,T14	Yes	T32,T124,T14	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T32,T75,T124	Yes	T32,T75,T124	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T32,T75,T124	Yes	T32,T75,T124	INPUT
tl_pattgen_i.d_error	Yes	Yes	T91,T97,T98	Yes	T91,T92,T97	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T32,T124,T14	Yes	T32,T124,T14	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T32,T124,T14	Yes	T32,T75,T124	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T32,T124,T14	Yes	T32,T75,T124	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T91,T97,T98	Yes	T91,T97,T98	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	T97,T98,*T162	Yes	T91,T92,T97	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T97,T98	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T32,*T124,*T14	Yes	T32,T124,T14	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T32,T75,T124	Yes	T32,T75,T124	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T38,T69,T136	Yes	T38,T69,T136	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T38,T69,T136	Yes	T38,T69,T136	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T38,T75,T69	Yes	T38,T75,T69	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T38,T75,T69	Yes	T38,T75,T69	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T97,T98,T162	Yes	T97,T98,T162	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T38,T69,T136	Yes	T38,T69,T136	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T38,T69,T136	Yes	T38,T75,T69	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T38,T69,T136	Yes	T38,T75,T69	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T70,*T97,*T98	Yes	T70,T91,T92	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T92,T97,T98	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T38,*T69,*T136	Yes	T38,T69,T136	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T38,T75,T69	Yes	T38,T75,T69	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_gpio_i.d_error	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T7,T29,T338	Yes	T7,T29,T338	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T7,T29,T338	Yes	T6,T7,T29	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T7,T29,T338	Yes	T6,T7,T29	INPUT
tl_gpio_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T92,T93,T97	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T95,*T231,*T92	Yes	T95,T231,T92	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T8,*T6,*T25	Yes	T2,T3,T4	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T7,T15,T12	Yes	T7,T15,T12	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T7,T15,T12	Yes	T7,T15,T12	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T7,T15,T12	Yes	T7,T15,T12	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T7,T15,T12	Yes	T7,T15,T12	INPUT
tl_spi_device_i.d_error	Yes	Yes	T91,T93,T97	Yes	T91,T97,T98	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T15,T12,T13	Yes	T15,T12,T13	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T7,T15,T12	Yes	T7,T15,T12	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T7,T15,T12	Yes	T15,T12,T13	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T93	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T91,*T97,*T98	Yes	T91,T92,T97	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T97	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T7,*T15,*T12	Yes	T7,T15,T12	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T7,T15,T12	Yes	T7,T15,T12	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T123,T258,T124	Yes	T123,T258,T124	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T123,T258,T124	Yes	T123,T258,T124	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T123,T258,T75	Yes	T123,T258,T75	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T123,T258,T75	Yes	T123,T258,T75	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T91,T97,T98	Yes	T91,T93,T97	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T123,T258,T124	Yes	T123,T258,T124	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T123,T258,T124	Yes	T123,T258,T75	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T123,T258,T699	Yes	T123,T258,T75	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T93	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T93,*T97,*T98	Yes	T91,T92,T97	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T123,*T258,*T124	Yes	T123,T258,T124	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T123,T258,T75	Yes	T123,T258,T75	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T8,T6,T25	Yes	T8,T6,T25	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T8,T6,T25	Yes	T8,T6,T25	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T8,T6,T25	Yes	T8,T6,T25	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T8,T6,T25	Yes	T8,T6,T25	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T92,T97,T98	Yes	T91,T92,T97	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T8,T6,T25	Yes	T8,T6,T25	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T8,T6,T25	Yes	T8,T6,T25	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T8,T6,T25	Yes	T8,T6,T25	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T70,*T97,*T98	Yes	T70,T91,T92	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T8,*T6,*T25	Yes	T8,T6,T25	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T8,T6,T25	Yes	T8,T6,T25	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T97,T98,T162	Yes	T97,T98,T162	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T25,T46,T47	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T25,T46,T47	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T92,T97,T98	Yes	T91,T97,T98	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T70,*T97,*T98	Yes	T70,T91,T92	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T97,T98,T162	Yes	T91,T92,T97	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T30,T28,T128	Yes	T30,T28,T128	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T30,T28,T128	Yes	T30,T28,T128	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T92,T97,T98	Yes	T91,T92,T97	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T30,T28,T128	Yes	T30,T28,T128	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T46,T30,T28	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T46,T30,T28	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T92,T97,T98	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T97,*T98,*T162	Yes	T35,T185,T186	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T92,T97,T98	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T30,*T28,*T128	Yes	T30,T28,T128	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T70,*T97,*T98	Yes	T70,T91,T92	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T35,*T185,*T186	Yes	T35,T185,T186	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T118,*T187,*T188	Yes	T118,T187,T188	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T1,T2,T3	Yes	T46,T47,T41	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T46,T47,T41	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	T97,T98,T162	Yes	T91,T92,T97	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T46,T47,T41	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T5,T118,T129	Yes	T5,T118,T129	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T5,T118,T129	Yes	T5,T118,T129	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T5,T118,T129	Yes	T5,T118,T129	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T5,T118,T129	Yes	T5,T118,T129	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T92,T98,T274	Yes	T91,T92,T98	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T118,T41,T208	Yes	T5,T118,T41	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T41,T208,T151	Yes	T41,T208,T151	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T118,T41,T208	Yes	T5,T118,T129	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T94,*T358,*T359	Yes	T94,T358,T359	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T91,T97,T98	Yes	T91,T92,T93	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T41,*T208,*T202	Yes	T5,T118,T129	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T5,T118,T129	Yes	T5,T118,T129	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T179,T164,T124	Yes	T179,T164,T124	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T179,T164,T124	Yes	T75,T179,T164	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T46,T47,T41	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T91,*T97,*T98	Yes	T91,T92,T97	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T91,T97,T98	Yes	T97,T98,T162	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T46,*T47,*T41	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T46,T47,T82	Yes	T46,T47,T82	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T46,T47,T82	Yes	T46,T47,T82	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T46,T47,T82	Yes	T46,T47,T82	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T46,T47,T82	Yes	T46,T47,T82	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T46,T47,T82	Yes	T46,T47,T82	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T46,T47,T82	Yes	T46,T47,T82	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T46,T47,T82	Yes	T46,T47,T82	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T92,*T97,*T98	Yes	T91,T92,T97	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T46,*T47,*T82	Yes	T46,T47,T82	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T46,T47,T82	Yes	T46,T47,T82	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T210,T209,T149	Yes	T210,T209,T149	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T210,T209,T149	Yes	T210,T209,T149	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T75,T210,T209	Yes	T75,T210,T209	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T75,T210,T209	Yes	T75,T210,T209	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T210,T209,T149	Yes	T210,T209,T149	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T210,T209,T149	Yes	T75,T210,T209	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T210,T209,T149	Yes	T75,T210,T209	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T92,T97,T98	Yes	T91,T92,T97	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T97,*T98,*T162	Yes	T91,T92,T97	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T210,*T209,*T149	Yes	T210,T209,T149	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T75,T210,T209	Yes	T75,T210,T209	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T25,T46,T257	Yes	T25,T46,T257	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T46,T33,T34	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T46,T257,T47	Yes	T46,T257,T47	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T46,T33,T34	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T46,T47,T82	Yes	T46,T47,T82	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T40,*T278,*T443	Yes	T40,T278,T443	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T97	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T46,T257,T47	Yes	T46,T257,T47	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T46,T257,T47	Yes	T46,T257,T47	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T46,T257,T47	Yes	T46,T257,T47	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T46,T257,T47	Yes	T46,T257,T47	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T46,T257,T47	Yes	T46,T257,T47	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T46,T257,T47	Yes	T46,T257,T47	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T46,T257,T47	Yes	T46,T257,T47	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T92,T97,T98	Yes	T92,T97,T98	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T97,*T98,*T274	Yes	T278,T456,T97	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T46,*T257,*T47	Yes	T46,T257,T47	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T46,T257,T47	Yes	T46,T257,T47	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T31,T16,T68	Yes	T31,T16,T68	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T31,T16,T68	Yes	T31,T16,T68	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T31,T16,T68	Yes	T31,T16,T68	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T31,T16,T68	Yes	T31,T16,T68	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T92,T97,T98	Yes	T92,T93,T97	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T31,T16,T68	Yes	T31,T16,T68	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T68,T19	Yes	T16,T68,T19	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T31,T16,T68	Yes	T31,T16,T68	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T92,T97,T98	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T95,*T70,*T92	Yes	T95,T70,T91	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T92,T97,T98	Yes	T91,T92,T97	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T16,*T68,*T19	Yes	T31,T16,T68	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T31,T16,T68	Yes	T31,T16,T68	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T139,T73,T86	Yes	T139,T73,T86	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T139,T73,T86	Yes	T139,T73,T86	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T139,T75,T73	Yes	T139,T75,T73	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T139,T75,T73	Yes	T139,T75,T73	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T139,T73,T338	Yes	T139,T73,T86	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T139,T73,T86	Yes	T139,T75,T73	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T139,T73,T86	Yes	T139,T75,T73	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T92,T93,T97	Yes	T92,T97,T98	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T91,*T97,*T98	Yes	T91,T92,T93	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T92,T97,T98	Yes	T91,T92,T97	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T139,*T73,*T338	Yes	T139,T73,T86	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T139,T75,T73	Yes	T139,T75,T73	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T40	Yes	T35,T94,T40	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T91,T92,T93	Yes	T91,T92,T93	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T40,T95,T96	Yes	T40,T95,T96	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	Yes	Yes	T92,T98,T162	Yes	T92,T98,T162	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T8,T25,T46	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T92,*T97,*T98	Yes	T91,T92,T97	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T91,T92,T97	Yes	T91,T92,T97	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T92,*T97,*T98	Yes	T91,T92,T97	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range