Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3854375	1			T97	118		T98	116		T99	251
values[2]	776632	1			T97	64		T98	49		T99	10
values[3]	103753	1			T99	5		T105	2		T103	3
values[4]	54132	1			T99	7		T693	291		T574	2
values[5]	36314	1			T99	8		T693	214		T564	93
values[6]	26769	1			T99	18		T693	141		T564	71
values[7]	21613	1			T99	19		T693	121		T564	45
values[8]	17480	1			T99	5		T693	79		T564	38
values[9]	15857	1			T99	4		T693	68		T564	26
values[10]	14552	1			T99	1		T693	78		T564	35
values[11]	13645	1			T99	1		T693	59		T564	26
values[12]	12775	1			T99	2		T693	42		T564	20
values[13]	12442	1			T99	2		T693	45		T564	30
values[14]	11967	1			T99	8		T693	57		T564	24
values[15]	11476	1			T99	8		T693	37		T564	16
values[16]	10956	1			T99	21		T693	46		T564	18
values[17]	10382	1			T99	19		T693	30		T564	30
values[18]	10014	1			T99	23		T693	27		T564	34
values[19]	9861	1			T99	10		T693	44		T564	30
values[20]	9352	1			T99	2		T693	29		T564	35
values[21]	8944	1			T99	1		T693	49		T564	28
values[22]	8856	1			T99	1		T693	49		T564	21
values[23]	8813	1			T99	1		T693	53		T564	19
values[24]	8489	1			T99	10		T693	42		T564	25
values[25]	8066	1			T99	6		T693	31		T564	30
values[26]	7604	1			T99	4		T693	22		T564	28
values[27]	7331	1			T99	8		T693	28		T564	19
values[28]	7094	1			T99	11		T693	22		T564	20
values[29]	6760	1			T99	4		T693	19		T564	17
values[30]	6245	1			T99	1		T693	10		T564	15
values[31]	5689	1			T99	2		T693	9		T564	20
values[32]	5280	1			T99	1		T693	15		T564	17
values[33]	5058	1			T99	2		T693	11		T564	14
values[34]	4736	1			T99	1		T693	5		T564	19
values[35]	4278	1			T99	1		T693	2		T564	24
values[36]	3988	1			T99	2		T693	2		T564	12
values[37]	3722	1			T99	4		T693	2		T564	17
values[38]	3776	1			T99	4		T693	4		T564	18
values[39]	3642	1			T99	4		T693	7		T564	10
values[40]	3471	1			T99	1		T693	6		T564	11
values[41]	3315	1			T99	2		T693	3		T564	10
values[42]	3199	1			T99	1		T693	2		T564	14
values[43]	3126	1			T99	1		T693	4		T564	22
values[44]	3105	1			T99	8		T693	9		T564	14
values[45]	3095	1			T99	8		T693	3		T564	11
values[46]	2973	1			T99	1		T693	2		T564	9
values[47]	2958	1			T99	2		T693	2		T564	11
values[48]	2893	1			T99	5		T693	4		T564	23
values[49]	2903	1			T99	1		T693	5		T564	24
values[50]	2860	1			T99	4		T693	3		T564	14
values[51]	2806	1			T99	2		T693	3		T564	11
values[52]	2757	1			T99	2		T693	2		T564	16
values[53]	2655	1			T99	2		T693	5		T564	11
values[54]	2570	1			T693	5		T564	12		T565	3
values[55]	2518	1			T693	2		T564	21		T565	3
values[56]	2469	1			T693	2		T564	26		T565	6
values[57]	2465	1			T693	4		T564	12		T565	15
values[58]	2420	1			T693	4		T564	13		T565	4
values[59]	2279	1			T693	10		T564	16		T565	2
values[60]	2330	1			T693	5		T564	20		T565	1
values[61]	2489	1			T693	12		T564	25		T810	3
values[62]	3421	1			T693	10		T564	42		T810	2
values[63]	9268	1			T693	38		T564	154		T810	6
values[64]	235980	1			T693	104		T564	326		T810	7

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4902035	1			T97	141		T98	89		T99	402
values[2]	832550	1			T97	40		T98	31		T99	87
values[3]	86265	1			T97	2		T98	1		T99	1
values[4]	15273	1			T309	2		T458	5		T479	3
values[5]	6010	1			T582	2		T574	1		T569	1
values[6]	3552	1			T564	5		T659	14		T802	3
values[7]	2829	1			T564	2		T659	22		T802	3
values[8]	2327	1			T564	4		T659	30		T802	1
values[9]	2025	1			T564	1		T659	17		T802	2
values[10]	1715	1			T564	1		T659	7		T802	3
values[11]	1593	1			T564	5		T659	10		T802	5
values[12]	1380	1			T564	10		T659	7		T802	8
values[13]	1236	1			T564	7		T659	6		T802	7
values[14]	1139	1			T564	7		T659	6		T802	6
values[15]	1130	1			T564	1		T659	9		T802	9
values[16]	1051	1			T564	2		T659	19		T802	8
values[17]	958	1			T564	4		T659	16		T802	1
values[18]	960	1			T564	5		T659	23		T802	1
values[19]	937	1			T564	5		T659	12		T802	4
values[20]	883	1			T564	7		T659	14		T802	9
values[21]	867	1			T564	3		T659	11		T802	5
values[22]	829	1			T564	6		T659	11		T802	4
values[23]	717	1			T564	2		T659	2		T802	3
values[24]	727	1			T564	2		T659	2		T802	9
values[25]	635	1			T564	4		T659	3		T802	9
values[26]	615	1			T564	7		T659	5		T802	7
values[27]	671	1			T564	2		T659	7		T802	5
values[28]	650	1			T564	5		T659	5		T802	5
values[29]	523	1			T564	1		T659	3		T802	3
values[30]	584	1			T564	4		T659	3		T802	7
values[31]	592	1			T564	5		T659	5		T802	12
values[32]	556	1			T564	4		T659	8		T802	8
values[33]	541	1			T564	8		T659	10		T802	19
values[34]	479	1			T564	2		T659	5		T802	6
values[35]	486	1			T564	1		T659	5		T802	7
values[36]	489	1			T564	1		T659	4		T802	5
values[37]	502	1			T564	1		T659	4		T660	1
values[38]	479	1			T564	1		T659	3		T660	1
values[39]	484	1			T564	1		T659	2		T660	1
values[40]	449	1			T564	1		T659	3		T660	1
values[41]	426	1			T564	1		T659	2		T660	1
values[42]	412	1			T564	3		T659	3		T660	1
values[43]	403	1			T564	9		T659	3		T660	3
values[44]	398	1			T564	9		T659	3		T660	1
values[45]	379	1			T564	10		T659	3		T660	2
values[46]	354	1			T564	2		T659	4		T660	6
values[47]	364	1			T564	1		T659	9		T660	1
values[48]	366	1			T564	1		T659	5		T660	1
values[49]	377	1			T564	5		T659	6		T660	1
values[50]	392	1			T564	2		T659	9		T660	2
values[51]	367	1			T564	9		T659	6		T660	1
values[52]	350	1			T564	5		T659	5		T660	2
values[53]	351	1			T564	1		T659	6		T660	2
values[54]	330	1			T564	7		T659	6		T660	4
values[55]	345	1			T564	7		T659	3		T660	2
values[56]	328	1			T564	2		T659	6		T660	1
values[57]	334	1			T564	3		T659	7		T660	2
values[58]	348	1			T564	1		T659	5		T660	1
values[59]	305	1			T564	1		T659	7		T660	2
values[60]	306	1			T564	1		T659	5		T660	2
values[61]	334	1			T564	1		T659	6		T660	2
values[62]	523	1			T564	2		T659	16		T660	4
values[63]	2058	1			T564	13		T659	46		T660	19
values[64]	26959	1			T564	24		T659	121		T660	73

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	548987	1			T97	1		T98	1		T99	2
values[2]	2778699	1			T97	70		T98	80		T99	251
values[3]	1237158	1			T97	34		T98	44		T99	46
values[4]	145385	1			T99	7		T105	1		T184	5
values[5]	73802	1			T99	17		T476	4		T582	1
values[6]	47094	1			T99	7		T693	147		T564	112
values[7]	34012	1			T99	2		T693	124		T564	78
values[8]	26997	1			T99	1		T693	112		T564	43
values[9]	22938	1			T99	4		T693	103		T564	22
values[10]	20208	1			T99	8		T693	124		T564	24
values[11]	17797	1			T99	11		T693	85		T564	20
values[12]	16128	1			T99	15		T693	54		T564	32
values[13]	15180	1			T99	10		T693	43		T564	35
values[14]	14286	1			T99	11		T693	48		T564	28
values[15]	13551	1			T99	10		T693	50		T564	22
values[16]	12937	1			T99	12		T693	42		T564	28
values[17]	12188	1			T99	1		T693	56		T564	24
values[18]	11696	1			T99	3		T693	55		T564	25
values[19]	11485	1			T99	8		T693	79		T564	25
values[20]	11227	1			T99	4		T693	74		T564	25
values[21]	10832	1			T99	1		T693	56		T564	23
values[22]	10427	1			T99	6		T693	30		T564	22
values[23]	10011	1			T99	9		T693	29		T564	22
values[24]	9758	1			T99	6		T693	32		T564	16
values[25]	9360	1			T99	9		T693	25		T564	15
values[26]	8974	1			T99	20		T693	30		T564	22
values[27]	8700	1			T99	10		T693	27		T564	13
values[28]	8166	1			T99	8		T693	28		T564	19
values[29]	7418	1			T99	1		T693	13		T564	18
values[30]	7199	1			T99	3		T693	15		T564	23
values[31]	6576	1			T693	7		T564	26		T565	31
values[32]	5842	1			T693	5		T564	17		T565	22
values[33]	5506	1			T693	6		T564	9		T565	9
values[34]	5261	1			T693	4		T564	16		T565	2
values[35]	4807	1			T693	3		T564	12		T565	1
values[36]	4507	1			T693	5		T564	12		T565	2
values[37]	4139	1			T693	3		T564	19		T565	1
values[38]	3814	1			T693	3		T564	23		T565	1
values[39]	3772	1			T693	7		T564	27		T565	5
values[40]	3526	1			T693	2		T564	25		T565	1
values[41]	3351	1			T693	3		T564	11		T565	1
values[42]	3360	1			T693	6		T564	9		T565	1
values[43]	3269	1			T693	6		T564	13		T565	1
values[44]	3218	1			T693	3		T564	20		T565	1
values[45]	3128	1			T693	4		T564	26		T565	5
values[46]	3108	1			T693	3		T564	19		T565	4
values[47]	3067	1			T693	7		T564	10		T565	1
values[48]	3107	1			T693	3		T564	12		T565	2
values[49]	3099	1			T693	9		T564	15		T821	2
values[50]	3046	1			T693	4		T564	14		T821	4
values[51]	3009	1			T693	3		T564	16		T821	3
values[52]	2973	1			T693	6		T564	16		T821	2
values[53]	2924	1			T693	6		T564	12		T821	1
values[54]	2876	1			T693	3		T564	14		T810	1
values[55]	2818	1			T693	5		T564	16		T810	3
values[56]	2703	1			T693	4		T564	15		T810	3
values[57]	2648	1			T693	7		T564	11		T810	3
values[58]	2610	1			T693	12		T564	17		T810	2
values[59]	2639	1			T693	6		T564	17		T810	5
values[60]	2543	1			T693	2		T564	12		T810	1
values[61]	2602	1			T693	3		T564	18		T810	1
values[62]	3284	1			T693	10		T564	20		T810	6
values[63]	8063	1			T693	52		T564	75		T810	27
values[64]	231745	1			T693	87		T564	245		T810	65