Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1806863	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37606755

1

T1

6495

T2

5731

T3

350

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	26969947	1			T1	2543		T2	2178		T3	175
values[0x0]	10992853	1			T1	3952		T2	3553		T3	175
values[0x1]	1450818	1			T1	249		T2	258		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	555386	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38858232

1

T1

6744

T2

5989

T3

353

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18629725	1			T1	3372		T2	2995		T3	177
valid_sources[0x01]	18628948	1			T1	3372		T2	2994		T3	176
valid_sources[0x02]	34306	1			T40	2		T417	23		T418	14
valid_sources[0x03]	34813	1			T40	1		T417	29		T418	18
valid_sources[0x04]	33963	1			T96	2		T101	1		T69	15
valid_sources[0x05]	34818	1			T40	1		T417	18		T418	22
valid_sources[0x06]	35232	1			T417	16		T418	19		T407	92
valid_sources[0x07]	34627	1			T101	1		T417	10		T418	10
valid_sources[0x08]	35015	1			T417	18		T418	7		T407	74
valid_sources[0x09]	34924	1			T74	39		T69	1		T417	18
valid_sources[0x0a]	34719	1			T417	21		T418	13		T407	64
valid_sources[0x0b]	36964	1			T69	4		T417	33		T418	10
valid_sources[0x0c]	34577	1			T40	1		T101	3		T417	27
valid_sources[0x0d]	34477	1			T417	18		T418	16		T407	100
valid_sources[0x0e]	34223	1			T40	1		T417	18		T418	9
valid_sources[0x0f]	35207	1			T40	3		T417	18		T418	18
valid_sources[0x10]	34477	1			T96	9		T417	13		T418	14
valid_sources[0x11]	35483	1			T40	1		T417	19		T418	12
valid_sources[0x12]	34713	1			T417	23		T418	13		T407	91
valid_sources[0x13]	35257	1			T417	25		T871	621		T418	12
valid_sources[0x14]	34360	1			T417	32		T418	14		T407	84
valid_sources[0x15]	35562	1			T417	22		T418	13		T407	129
valid_sources[0x16]	33985	1			T417	12		T418	13		T407	68
valid_sources[0x17]	34658	1			T40	2		T96	3		T101	1
valid_sources[0x18]	35009	1			T417	22		T418	16		T407	63
valid_sources[0x19]	34412	1			T40	1		T101	4		T417	26
valid_sources[0x1a]	34263	1			T40	1		T101	2		T417	36
valid_sources[0x1b]	34446	1			T101	2		T417	18		T418	16
valid_sources[0x1c]	33674	1			T417	25		T418	15		T407	77
valid_sources[0x1d]	34503	1			T40	1		T96	5		T101	1
valid_sources[0x1e]	34949	1			T96	1		T101	1		T417	13
valid_sources[0x1f]	34215	1			T40	1		T101	2		T417	33
valid_sources[0x20]	34288	1			T40	1		T101	1		T417	26

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26393393

1

T1

2543

T2

2178

T3

175

values[0x0]

all_enables

biggest_size

10938166

1

T1

3952

T2

3553

T3

175

values[0x1]

all_enables

biggest_size

275196

1

T40

17

T96

18

T101

18

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3001177	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

474616

1

T97

32

T98

20

T99

65

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1177508	1			T97	50		T98	50		T99	202
values[0x0]	1123526	1			T97	61		T98	55		T99	165
values[0x1]	1174759	1			T97	71		T98	60		T99	165

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2323324	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1152469

1

T97

72

T98

51

T99

184

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54738	1			T97	3		T99	8		T102	1
valid_sources[0x01]	53660	1			T97	6		T99	3		T102	2
valid_sources[0x02]	53402	1			T99	3		T102	2		T105	16
valid_sources[0x03]	54741	1			T97	3		T99	4		T102	1
valid_sources[0x04]	54228	1			T97	3		T99	9		T102	3
valid_sources[0x05]	55025	1			T99	2		T102	4		T103	17
valid_sources[0x06]	53701	1			T97	3		T99	2		T102	4
valid_sources[0x07]	54899	1			T97	2		T99	3		T102	2
valid_sources[0x08]	53431	1			T97	5		T98	15		T99	3
valid_sources[0x09]	54376	1			T97	5		T99	4		T102	1
valid_sources[0x0a]	54942	1			T98	9		T99	13		T102	1
valid_sources[0x0b]	53621	1			T97	1		T99	9		T105	14
valid_sources[0x0c]	54922	1			T97	6		T99	9		T102	3
valid_sources[0x0d]	54164	1			T97	1		T99	22		T102	1
valid_sources[0x0e]	56046	1			T97	10		T99	16		T102	3
valid_sources[0x0f]	53185	1			T97	4		T99	17		T102	4
valid_sources[0x10]	53823	1			T97	1		T98	3		T99	10
valid_sources[0x11]	53174	1			T97	3		T98	1		T99	4
valid_sources[0x12]	53186	1			T99	12		T102	2		T104	2
valid_sources[0x13]	53979	1			T97	2		T98	4		T99	4
valid_sources[0x14]	54731	1			T97	1		T98	4		T99	28
valid_sources[0x15]	55526	1			T97	6		T99	20		T104	6
valid_sources[0x16]	54516	1			T98	5		T99	34		T102	2
valid_sources[0x17]	54156	1			T99	9		T102	7		T104	7
valid_sources[0x18]	54145	1			T97	4		T102	2		T104	4
valid_sources[0x19]	55193	1			T97	3		T99	9		T102	2
valid_sources[0x1a]	54771	1			T97	8		T98	5		T99	4
valid_sources[0x1b]	54712	1			T97	2		T98	3		T99	1
valid_sources[0x1c]	54138	1			T99	4		T102	3		T103	14
valid_sources[0x1d]	52366	1			T97	7		T98	10		T99	1
valid_sources[0x1e]	54331	1			T97	1		T99	1		T102	2
valid_sources[0x1f]	54564	1			T97	3		T98	18		T99	2
valid_sources[0x20]	54438	1			T97	3		T99	19		T104	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49474

1

T97

3

T98

1

T99

5

values[0x0]

all_enables

biggest_size

375216

1

T97

24

T98

17

T99

56

values[0x1]

all_enables

biggest_size

49926

1

T97

5

T98

2

T99

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3189892	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

519581

1

T97

22

T98

17

T99

83

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1270259	1			T97	56		T98	48		T99	155
values[0x0]	1169731	1			T97	71		T98	41		T99	168
values[0x1]	1269483	1			T97	56		T98	32		T99	167

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2448123	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1261350

1

T97

57

T98

47

T99

183

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	58061	1			T99	2		T104	1		T105	4
valid_sources[0x01]	57406	1			T97	11		T99	4		T104	3
valid_sources[0x02]	57474	1			T98	12		T99	3		T104	3
valid_sources[0x03]	57964	1			T97	9		T99	2		T104	2
valid_sources[0x04]	58022	1			T99	10		T102	20		T104	1
valid_sources[0x05]	57965	1			T98	3		T99	3		T104	2
valid_sources[0x06]	57817	1			T98	8		T99	5		T104	3
valid_sources[0x07]	57811	1			T99	8		T104	4		T105	10
valid_sources[0x08]	58250	1			T99	1		T104	2		T105	4
valid_sources[0x09]	57376	1			T97	21		T105	6		T103	17
valid_sources[0x0a]	57960	1			T99	2		T102	6		T104	4
valid_sources[0x0b]	58556	1			T99	16		T102	6		T104	1
valid_sources[0x0c]	59170	1			T99	14		T104	1		T105	11
valid_sources[0x0d]	56908	1			T97	14		T99	4		T102	4
valid_sources[0x0e]	58068	1			T97	1		T98	11		T99	5
valid_sources[0x0f]	57314	1			T97	3		T99	9		T104	3
valid_sources[0x10]	57748	1			T99	19		T105	9		T103	18
valid_sources[0x11]	56871	1			T99	4		T104	4		T105	4
valid_sources[0x12]	57570	1			T98	3		T99	5		T104	2
valid_sources[0x13]	58793	1			T97	9		T99	2		T104	3
valid_sources[0x14]	58305	1			T97	3		T99	2		T104	7
valid_sources[0x15]	57839	1			T98	4		T99	10		T102	3
valid_sources[0x16]	57552	1			T97	10		T99	10		T104	4
valid_sources[0x17]	58182	1			T99	15		T102	3		T104	1
valid_sources[0x18]	58809	1			T97	4		T98	1		T99	7
valid_sources[0x19]	58040	1			T97	6		T98	6		T99	8
valid_sources[0x1a]	57424	1			T99	9		T104	3		T105	7
valid_sources[0x1b]	57439	1			T97	2		T98	20		T99	27
valid_sources[0x1c]	57440	1			T97	19		T98	1		T99	4
valid_sources[0x1d]	56895	1			T99	6		T104	2		T105	9
valid_sources[0x1e]	58399	1			T97	6		T98	4		T99	14
valid_sources[0x1f]	58537	1			T102	5		T104	2		T105	6
valid_sources[0x20]	58074	1			T99	3		T102	7		T104	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

54714

1

T97

3

T98

2

T99

4

values[0x0]

all_enables

biggest_size

410128

1

T97

18

T98

13

T99

70

values[0x1]

all_enables

biggest_size

54739

1

T97

1

T98

2

T99

9

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3022307	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

478236

1

T97

11

T98

20

T99

82

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1183636	1			T97	38		T98	38		T99	179
values[0x0]	1133217	1			T97	28		T98	42		T99	166
values[0x1]	1183690	1			T97	39		T98	45		T99	158

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2340693	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1159850

1

T97

30

T98

39

T99

179

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54222	1			T97	2		T99	1		T105	4
valid_sources[0x01]	54889	1			T97	1		T98	2		T99	5
valid_sources[0x02]	54114	1			T97	1		T99	3		T102	1
valid_sources[0x03]	55402	1			T97	2		T98	3		T99	1
valid_sources[0x04]	54503	1			T97	1		T102	3		T104	2
valid_sources[0x05]	54691	1			T97	3		T98	3		T99	1
valid_sources[0x06]	54501	1			T97	2		T98	7		T99	1
valid_sources[0x07]	55019	1			T98	1		T99	6		T103	17
valid_sources[0x08]	53995	1			T97	1		T99	7		T103	21
valid_sources[0x09]	55126	1			T97	1		T99	2		T103	17
valid_sources[0x0a]	55242	1			T97	1		T98	2		T99	1
valid_sources[0x0b]	55178	1			T97	2		T102	1		T105	4
valid_sources[0x0c]	55207	1			T97	2		T99	10		T105	1
valid_sources[0x0d]	54674	1			T97	1		T98	4		T99	1
valid_sources[0x0e]	55474	1			T97	1		T98	2		T99	1
valid_sources[0x0f]	54809	1			T97	1		T98	2		T99	7
valid_sources[0x10]	54133	1			T97	1		T99	5		T102	5
valid_sources[0x11]	53877	1			T97	1		T98	1		T99	3
valid_sources[0x12]	54037	1			T97	1		T99	7		T102	2
valid_sources[0x13]	54277	1			T97	3		T98	5		T99	4
valid_sources[0x14]	55535	1			T97	2		T98	5		T99	10
valid_sources[0x15]	55242	1			T97	5		T104	2		T103	18
valid_sources[0x16]	54348	1			T99	14		T102	3		T105	10
valid_sources[0x17]	55050	1			T97	1		T98	7		T99	5
valid_sources[0x18]	54367	1			T97	1		T99	95		T102	5
valid_sources[0x19]	54381	1			T97	2		T98	4		T99	6
valid_sources[0x1a]	55872	1			T97	1		T99	14		T102	2
valid_sources[0x1b]	55028	1			T97	1		T98	1		T102	2
valid_sources[0x1c]	53877	1			T97	1		T105	10		T103	21
valid_sources[0x1d]	53873	1			T98	2		T99	9		T105	10
valid_sources[0x1e]	55000	1			T98	5		T99	2		T104	9
valid_sources[0x1f]	54154	1			T97	2		T98	4		T99	1
valid_sources[0x20]	54460	1			T97	1		T98	2		T99	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50113

1

T98

1

T99

12

T102

2

values[0x0]

all_enables

biggest_size

377807

1

T97

10

T98

18

T99

65

values[0x1]

all_enables

biggest_size

50316

1

T97

1

T98

1

T99

5