Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_133

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_133

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_134

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_135

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_136

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_137

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_138

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_139

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_140

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_141

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_142

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_143

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_144

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_145

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_146

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_147

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_148

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_149

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_150

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_151

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_152

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_153

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_154

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_155

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_156

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_157

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_158

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_159

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_160

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_161

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_162

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_163

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_164

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.90	85.71	100.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.26	77.78	100.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
wr_en_data_arb	50.00	50.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_133

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T169 T189 T190 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T169 T189 T190 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_133

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_133

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_134

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T169 T189 T190 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T169 T189 T190 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_134

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_134

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_135

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T246 T255 T256 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T246 T255 T256 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_135

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_135

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_136

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T246 T255 T256 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T246 T255 T256 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_136

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_136

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_137

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T246 T255 T256 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T246 T255 T256 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_137

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_137

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_138

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T246 T255 T256 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T246 T255 T256 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_138

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_138

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_139

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T246 T255 T256 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T246 T255 T256 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_139

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_139

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_140

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T246 T255 T256 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T246 T255 T256 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_140

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_140

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_141

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T246 T255 T256 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T246 T255 T256 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_141

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_141

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_142

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T246 T255 T256 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T246 T255 T256 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_142

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_142

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_143

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T246 T255 T256 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T246 T255 T256 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_143

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_143

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_144

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T246 T255 T256 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T246 T255 T256 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_144

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_144

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_145

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T246 T255 T256 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T246 T255 T256 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_145

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_145

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_146

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T246 T255 T256 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T246 T255 T256 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_146

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_146

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_147

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T246 T255 T256 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T246 T255 T256 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_147

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_147

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_148

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T246 T255 T256 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T246 T255 T256 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_148

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_148

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_149

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T246 T255 T256 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T246 T255 T256 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_149

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_149

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_150

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T246 T255 T256 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T246 T255 T256 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_150

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_150

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_151

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T246 T255 T256 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T246 T255 T256 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_151

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_151

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_152

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T246 T255 T256 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T246 T255 T256 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_152

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_152

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_153

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T6 T25 T29 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T6 T25 T29 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_153

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_153

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_154

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T71 T246 T239 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T71 T246 T239 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_154

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_154

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_155

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T140 T257 T267 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T140 T257 T267 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_155

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_155

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_156

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T268 T39 T269 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T268 T39 T269 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_156

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_156

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_157

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T247 T269 T270 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T247 T269 T270 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_157

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_157

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_158

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T131 T169 T271 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T131 T169 T271 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_158

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_158

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_159

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T169 T189 T190 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T169 T189 T190 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_159

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_4_p_159

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_160

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T1 T248 T134 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T1 T248 T134 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_160

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_160

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_161

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T1 T248 T134 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T1 T248 T134 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_161

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_161

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_162

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T248 T134 T257 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T248 T134 T257 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_162

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_162

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_163

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T248 T134 T257 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T248 T134 T257 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_163

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_163

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_164

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
ALWAYS	56	4	4	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	0	0.00
CONT_ASSIGN	72	1	1	100.00

55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T1 T2 T3 
60                          end
                   ==>  MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T1 T248 T134 
65         0/1     ==>    assign qe = wr_en;
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T1 T248 T134 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_164

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--

-1-	Status	Tests	Exclude Annotation
0	Excluded		[UNR] Tied off
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_ip_5_p_164

	Line No.	Total	Covered	Percent
Branches		5	3	60.00
TERNARY	64	2	1	50.00
IF	56	3	2	66.67

64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Not Covered