Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491686938	58820405	0	0
DataKnown_AKnownEnable	491686938	491581718	0	0
DepthKnown_A	491686938	491581718	0	0
RvalidKnown_A	491686938	491581718	0	0
WreadyKnown_A	491686938	491581718	0	0
gen_passthru_fifo.paramCheckPass	1017	1017	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	58820405	0	0
T1	111924	72372	0	0
T2	78951	9394	0	0
T3	42255	3485	0	0
T4	103207	11780	0	0
T5	100889	12560	0	0
T6	100982	13270	0	0
T7	100472	10901	0	0
T28	97609	11970	0	0
T109	67839	6643	0	0
T110	68617	6748	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	491581718	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	491581718	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	491581718	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	491581718	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017	1017	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T28	1	1	0	0
T109	1	1	0	0
T110	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         0/1     ==>      assign wready_o = rready_i;
49         0/1     ==>      assign full_o = rready_i;
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491686938	44196538	0	0
DataKnown_AKnownEnable	491686938	491581718	0	0
DepthKnown_A	491686938	491581718	0	0
RvalidKnown_A	491686938	491581718	0	0
WreadyKnown_A	491686938	491581718	0	0
gen_passthru_fifo.paramCheckPass	1017	1017	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	44196538	0	0
T1	111924	35785	0	0
T2	78951	6877	0	0
T3	42255	1880	0	0
T4	103207	9350	0	0
T5	100889	9726	0	0
T6	100982	9072	0	0
T7	100472	8363	0	0
T28	97609	9098	0	0
T109	67839	4973	0	0
T110	68617	5073	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	491581718	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	491581718	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	491581718	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	491581718	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017	1017	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T28	1	1	0	0
T109	1	1	0	0
T110	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491686938	44646925	0	0
DataKnown_AKnownEnable	491686938	491581718	0	0
DepthKnown_A	491686938	491581718	0	0
RvalidKnown_A	491686938	491581718	0	0
WreadyKnown_A	491686938	491581718	0	0
gen_passthru_fifo.paramCheckPass	1017	1017	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	44646925	0	0
T1	111924	7365	0	0
T2	78951	6161	0	0
T3	42255	461	0	0
T4	103207	5991	0	0
T5	100889	6919	0	0
T6	100982	6041	0	0
T7	100472	8553	0	0
T28	97609	6571	0	0
T109	67839	3996	0	0
T110	68617	4067	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	491581718	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	491581718	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	491581718	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	491581718	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017	1017	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T28	1	1	0	0
T109	1	1	0	0
T110	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T40 T96 T101 
49         1/1              assign full_o = rready_i;
           Tests:       T40 T96 T101 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491686938	37255209	0	0
DataKnown_AKnownEnable	491686938	491581718	0	0
DepthKnown_A	491686938	491581718	0	0
RvalidKnown_A	491686938	491581718	0	0
WreadyKnown_A	491686938	491581718	0	0
gen_passthru_fifo.paramCheckPass	1017	1017	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	37255209	0	0
T1	111924	6744	0	0
T2	78951	5989	0	0
T3	42255	353	0	0
T4	103207	5852	0	0
T5	100889	6745	0	0
T6	100982	5806	0	0
T7	100472	8100	0	0
T28	97609	6389	0	0
T109	67839	3882	0	0
T110	68617	3954	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	491581718	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	491581718	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	491581718	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	491581718	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017	1017	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T28	1	1	0	0
T109	1	1	0	0
T110	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	575290469	102726	0	0
DataKnown_AKnownEnable	575290469	575169212	0	0
DepthKnown_A	575290469	575169212	0	0
RvalidKnown_A	575290469	575169212	0	0
WreadyKnown_A	575290469	575169212	0	0
gen_passthru_fifo.paramCheckPass	2927	2927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	102726	0	0
T1	111924	34	0	0
T2	78951	24	0	0
T3	42255	8	0	0
T4	103207	13	0	0
T5	100889	24	0	0
T6	100982	25	0	0
T7	100472	208	0	0
T28	97609	22	0	0
T109	67839	13	0	0
T110	68617	13	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2927	2927	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T28	1	1	0	0
T109	1	1	0	0
T110	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	575290469	106991	0	0
DataKnown_AKnownEnable	575290469	575169212	0	0
DepthKnown_A	575290469	575169212	0	0
RvalidKnown_A	575290469	575169212	0	0
WreadyKnown_A	575290469	575169212	0	0
gen_passthru_fifo.paramCheckPass	2927	2927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	106991	0	0
T1	111924	34	0	0
T2	78951	24	0	0
T3	42255	8	0	0
T4	103207	13	0	0
T5	100889	24	0	0
T6	100982	25	0	0
T7	100472	208	0	0
T28	97609	22	0	0
T109	67839	13	0	0
T110	68617	13	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2927	2927	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T28	1	1	0	0
T109	1	1	0	0
T110	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	575290469	52506	0	0
DataKnown_AKnownEnable	575290469	575169212	0	0
DepthKnown_A	575290469	575169212	0	0
RvalidKnown_A	575290469	575169212	0	0
WreadyKnown_A	575290469	575169212	0	0
gen_passthru_fifo.paramCheckPass	2927	2927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	52506	0	0
T1	111924	31	0	0
T2	78951	23	0	0
T3	42255	8	0	0
T4	103207	12	0	0
T5	100889	21	0	0
T6	100982	22	0	0
T7	100472	205	0	0
T28	97609	19	0	0
T109	67839	12	0	0
T110	68617	12	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2927	2927	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T28	1	1	0	0
T109	1	1	0	0
T110	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	575290469	52506	0	0
DataKnown_AKnownEnable	575290469	575169212	0	0
DepthKnown_A	575290469	575169212	0	0
RvalidKnown_A	575290469	575169212	0	0
WreadyKnown_A	575290469	575169212	0	0
gen_passthru_fifo.paramCheckPass	2927	2927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	52506	0	0
T1	111924	31	0	0
T2	78951	23	0	0
T3	42255	8	0	0
T4	103207	12	0	0
T5	100889	21	0	0
T6	100982	22	0	0
T7	100472	205	0	0
T28	97609	19	0	0
T109	67839	12	0	0
T110	68617	12	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2927	2927	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T28	1	1	0	0
T109	1	1	0	0
T110	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T4 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T4 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	575290469	50220	0	0
DataKnown_AKnownEnable	575290469	575169212	0	0
DepthKnown_A	575290469	575169212	0	0
RvalidKnown_A	575290469	575169212	0	0
WreadyKnown_A	575290469	575169212	0	0
gen_passthru_fifo.paramCheckPass	2927	2927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	50220	0	0
T1	111924	3	0	0
T2	78951	1	0	0
T3	42255	0	0	0
T4	103207	1	0	0
T5	100889	3	0	0
T6	100982	3	0	0
T7	100472	3	0	0
T28	97609	3	0	0
T46	0	56	0	0
T109	67839	1	0	0
T110	68617	1	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2927	2927	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T28	1	1	0	0
T109	1	1	0	0
T110	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	575290469	54485	0	0
DataKnown_AKnownEnable	575290469	575169212	0	0
DepthKnown_A	575290469	575169212	0	0
RvalidKnown_A	575290469	575169212	0	0
WreadyKnown_A	575290469	575169212	0	0
gen_passthru_fifo.paramCheckPass	2927	2927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	54485	0	0
T1	111924	3	0	0
T2	78951	1	0	0
T3	42255	0	0	0
T4	103207	1	0	0
T5	100889	3	0	0
T6	100982	3	0	0
T7	100472	3	0	0
T28	97609	3	0	0
T46	0	56	0	0
T109	67839	1	0	0
T110	68617	1	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575290469	575169212	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2927	2927	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T28	1	1	0	0
T109	1	1	0	0
T110	1	1	0	0