Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sram_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.94 97.94

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_sram_ctrl_ret_aon 99.64 99.64
tb.dut.top_earlgrey.u_sram_ctrl_main 99.65 99.65


Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.64 99.64


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.64 99.64


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.91 92.47 89.25 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.65 99.65


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.65 99.65


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.91 92.47 89.25 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : sram_ctrl
TotalCoveredPercent
Totals 66 60 90.91
Total Bits 1164 1140 97.94
Total Bits 0->1 582 570 97.94
Total Bits 1->0 582 570 97.94

Ports 66 60 90.91
Port Bits 1164 1140 97.94
Port Bits 0->1 582 570 97.94
Port Bits 1->0 582 570 97.94

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T7,T46,T41 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T7,T46,T41 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[16:0] Yes Yes *T97,*T98,*T99 Yes T97,T98,T99 INPUT
ram_tl_i.a_address[20:17] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[22:21] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
ram_tl_i.a_address[27:23] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[28] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[29] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T97,T98,T99 Yes T97,T98,T99 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T7,T46,T41 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_sink Yes Yes T97,T98,T99 Yes T97,T98,T99 OUTPUT
ram_tl_o.d_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[1:0] Yes Yes T97,T98,T99 Yes T97,T98,T99 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T80,T210,T213 Yes T80,T210,T213 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T80,T210,T213 Yes T80,T210,T213 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[5:0] Yes Yes *T97,*T98,*T99 Yes T97,T98,T99 INPUT
regs_tl_i.a_address[17:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:18] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[23] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T80,*T210,*T213 Yes T80,T210,T213 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T100,*T40,*T96 Yes T100,T40,T96 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T97,T98,T99 Yes T97,T98,T99 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[2:0] Yes Yes T40,T96,T101 Yes T40,T96,T101 INPUT
regs_tl_i.a_valid Yes Yes T80,T210,T213 Yes T80,T210,T213 INPUT
regs_tl_o.a_ready Yes Yes T80,T210,T213 Yes T80,T210,T213 OUTPUT
regs_tl_o.d_error Yes Yes T97,T98,T99 Yes T97,T98,T102 OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T210,T213,T138 Yes T210,T213,T138 OUTPUT
regs_tl_o.d_user.rsp_intg[6:0] Yes Yes T210,T213,T138 Yes T80,T210,T213 OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T210,T213,T138 Yes T80,T210,T213 OUTPUT
regs_tl_o.d_sink Yes Yes T97,T98,T102 Yes T97,T98,T102 OUTPUT
regs_tl_o.d_source[5:0] Yes Yes *T97,*T98,*T99 Yes T460,T97,T98 OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[1:0] Yes Yes T97,T98,T102 Yes T97,T98,T102 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T210,*T213,*T138 Yes T210,T213,T138 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T80,T210,T213 Yes T80,T210,T213 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T80,T106,T107 Yes T80,T106,T107 INPUT
alert_rx_i[0].ping_n Yes Yes T106,T107,T108 Yes T106,T107,T108 INPUT
alert_rx_i[0].ping_p Yes Yes T106,T107,T108 Yes T106,T107,T108 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T80,T106,T107 Yes T80,T106,T107 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T46,T47,T87 Yes T46,T34,T47 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T46,T41,T47 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[7:0] Yes Yes T1,T2,T3 Yes T7,T46,T41 INPUT
sram_otp_key_o.req Yes Yes T210,T138,T212 Yes T210,T138,T212 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T7,T46,T41 Yes T2,T4,T109 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T1,T109,T7 Yes T1,T109,T110 INPUT
sram_otp_key_i.key[127:0] Yes Yes T1,T2,T4 Yes T7,T46,T13 INPUT
sram_otp_key_i.ack Yes Yes T210,T138,T212 Yes T210,T138,T212 INPUT
cfg_i.rf_cfg.cfg[3:0] No No No INPUT
cfg_i.rf_cfg.cfg_en No No No INPUT
cfg_i.rf_cfg.test No No No INPUT
cfg_i.ram_cfg.cfg[3:0] No No No INPUT
cfg_i.ram_cfg.cfg_en No No No INPUT
cfg_i.ram_cfg.test No No No INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon
TotalCoveredPercent
Totals 60 58 96.67
Total Bits 1102 1098 99.64
Total Bits 0->1 551 549 99.64
Total Bits 1->0 551 549 99.64

Ports 60 58 96.67
Port Bits 1102 1098 99.64
Port Bits 0->1 551 549 99.64
Port Bits 1->0 551 549 99.64

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T46,T41,T34 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T46,T41,T34 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T46,T247,T47 Yes T46,T247,T47 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[11:0] Yes Yes *T97,*T98,*T99 Yes T97,T98,T99 INPUT
ram_tl_i.a_address[20:12] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[22:21] Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
ram_tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes *T100,*T40,*T96 Yes T100,T40,T96 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T97,T98,T99 Yes T97,T98,T99 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[2:0] Yes Yes T40,T96,T101 Yes T40,T96,T101 INPUT
ram_tl_i.a_valid Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T46,T41,T34 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T46,T247,T47 Yes T46,T247,T47 OUTPUT
ram_tl_o.d_user.rsp_intg[6:0] Yes Yes T46,T41,T247 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T46,T47,T87 Yes T46,T47,T87 OUTPUT
ram_tl_o.d_sink Yes Yes T102,T104,T105 Yes T97,T98,T102 OUTPUT
ram_tl_o.d_source[5:0] Yes Yes *T40,*T58,*T101 Yes T40,T58,T101 OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[1:0] Yes Yes T97,T98,T102 Yes T97,T98,T102 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T4 Yes T1,T2,T4 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
regs_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T210,T138,T212 Yes T210,T138,T212 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T210,T138,T212 Yes T210,T138,T212 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[5:0] Yes Yes *T97,*T98,*T99 Yes T97,T98,T99 INPUT
regs_tl_i.a_address[19:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T100,*T40,*T96 Yes T100,T40,T96 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T97,T98,T99 Yes T97,T98,T99 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[2:0] Yes Yes T40,T96,T101 Yes T40,T96,T101 INPUT
regs_tl_i.a_valid Yes Yes T80,T210,T138 Yes T80,T210,T138 INPUT
regs_tl_o.a_ready Yes Yes T80,T210,T138 Yes T80,T210,T138 OUTPUT
regs_tl_o.d_error Yes Yes T97,T98,T102 Yes T98,T102,T105 OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T210,T138,T212 Yes T210,T138,T212 OUTPUT
regs_tl_o.d_user.rsp_intg[6:0] Yes Yes T210,T138,T212 Yes T80,T210,T138 OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T210,T138,T212 Yes T80,T210,T138 OUTPUT
regs_tl_o.d_sink Yes Yes T97,T98,T102 Yes T97,T98,T102 OUTPUT
regs_tl_o.d_source[5:0] Yes Yes *T98,*T105,*T103 Yes T97,T98,T102 OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[1:0] Yes Yes T97,T98,T102 Yes T97,T98,T102 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T210,*T138,*T212 Yes T210,T138,T212 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T80,T210,T138 Yes T80,T210,T138 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T80,T106,T107 Yes T80,T106,T107 INPUT
alert_rx_i[0].ping_n Yes Yes T106,T107,T108 Yes T106,T107,T108 INPUT
alert_rx_i[0].ping_p Yes Yes T106,T107,T108 Yes T106,T107,T108 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T80,T106,T107 Yes T80,T106,T107 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T46,T47,T87 Yes T46,T34,T47 INPUT
lc_hw_debug_en_i[3:0] Unreachable Unreachable Unreachable INPUT
otp_en_sram_ifetch_i[7:0] Unreachable Unreachable Unreachable INPUT
sram_otp_key_o.req Yes Yes T210,T138,T212 Yes T210,T138,T212 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T7,T46,T41 Yes T2,T4,T109 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T1,T109,T7 Yes T1,T109,T110 INPUT
sram_otp_key_i.key[127:0] Yes Yes T1,T2,T4 Yes T7,T46,T13 INPUT
sram_otp_key_i.ack Yes Yes T210,T138,T212 Yes T210,T138,T212 INPUT
cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.test No No No INPUT
cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.test No No No INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_main
TotalCoveredPercent
Totals 62 60 96.77
Total Bits 1136 1132 99.65
Total Bits 0->1 568 566 99.65
Total Bits 1->0 568 566 99.65

Ports 62 60 96.77
Port Bits 1136 1132 99.65
Port Bits 0->1 568 566 99.65
Port Bits 1->0 568 566 99.65

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T7,T46,T41 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T7,T46,T41 Yes T1,T2,T3 INPUT
ram_tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[16:0] Yes Yes *T97,*T98,*T99 Yes T97,T98,T99 INPUT
ram_tl_i.a_address[27:17] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_address[28] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_address[31:29] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_size[1:0] Yes Yes T97,T98,T99 Yes T97,T98,T99 INPUT
ram_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
ram_tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
ram_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_error Yes Yes T1,T2,T3 Yes T7,T46,T41 OUTPUT
ram_tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_sink Yes Yes T97,T98,T99 Yes T97,T98,T99 OUTPUT
ram_tl_o.d_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_size[1:0] Yes Yes T97,T98,T99 Yes T97,T98,T99 OUTPUT
ram_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
ram_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
ram_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_i.d_ready Yes Yes T7,T46,T41 Yes T1,T2,T3 INPUT
regs_tl_i.a_user.data_intg[6:0] Yes Yes T80,T210,T213 Yes T80,T210,T213 INPUT
regs_tl_i.a_user.cmd_intg[6:0] Yes Yes T80,T210,T213 Yes T80,T210,T213 INPUT
regs_tl_i.a_user.instr_type[3:0] Yes Yes T80,T210,T213 Yes T80,T210,T213 INPUT
regs_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_data[31:0] Yes Yes T80,T210,T213 Yes T80,T210,T213 INPUT
regs_tl_i.a_mask[3:0] Yes Yes T80,T210,T213 Yes T80,T210,T213 INPUT
regs_tl_i.a_address[5:0] Yes Yes *T98,*T102,*T104 Yes T98,T102,T104 INPUT
regs_tl_i.a_address[17:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[20:18] Yes Yes T80,T210,T213 Yes T80,T210,T213 INPUT
regs_tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[24] Yes Yes *T80,*T210,*T213 Yes T80,T210,T213 INPUT
regs_tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_address[30] Yes Yes *T80,*T210,*T213 Yes T80,T210,T213 INPUT
regs_tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_source[5:0] Yes Yes *T460,*T97,*T98 Yes T460,T97,T98 INPUT
regs_tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_size[1:0] Yes Yes T97,T98,T104 Yes T97,T98,T104 INPUT
regs_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
regs_tl_i.a_opcode[2:0] Yes Yes T97,T98,T102 Yes T97,T98,T102 INPUT
regs_tl_i.a_valid Yes Yes T80,T210,T213 Yes T80,T210,T213 INPUT
regs_tl_o.a_ready Yes Yes T80,T210,T213 Yes T80,T210,T213 OUTPUT
regs_tl_o.d_error Yes Yes T97,T98,T99 Yes T97,T98,T104 OUTPUT
regs_tl_o.d_user.data_intg[6:0] Yes Yes T213,T349,T350 Yes T213,T349,T350 OUTPUT
regs_tl_o.d_user.rsp_intg[6:0] Yes Yes T210,T213,T138 Yes T80,T210,T213 OUTPUT
regs_tl_o.d_data[31:0] Yes Yes T210,T213,T138 Yes T80,T210,T213 OUTPUT
regs_tl_o.d_sink Yes Yes T97,T98,T105 Yes T97,T102,T105 OUTPUT
regs_tl_o.d_source[5:0] Yes Yes *T97,*T99,*T105 Yes T460,T97,T98 OUTPUT
regs_tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_size[1:0] Yes Yes T97,T98,T104 Yes T97,T98,T104 OUTPUT
regs_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_opcode[0] Yes Yes *T210,*T213,*T138 Yes T210,T213,T138 OUTPUT
regs_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
regs_tl_o.d_valid Yes Yes T80,T210,T213 Yes T80,T210,T213 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T80,T106,T107 Yes T80,T106,T107 INPUT
alert_rx_i[0].ping_n Yes Yes T106,T107,T108 Yes T106,T107,T108 INPUT
alert_rx_i[0].ping_p Yes Yes T106,T107,T108 Yes T106,T107,T108 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T80,T106,T107 Yes T80,T106,T107 OUTPUT
lc_escalate_en_i[3:0] Yes Yes T46,T47,T87 Yes T46,T34,T47 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T46,T41,T47 Yes T1,T2,T3 INPUT
otp_en_sram_ifetch_i[7:0] Yes Yes T1,T2,T3 Yes T7,T46,T41 INPUT
sram_otp_key_o.req Yes Yes T210,T138,T211 Yes T210,T138,T211 OUTPUT
sram_otp_key_i.seed_valid Yes Yes T7,T46,T41 Yes T2,T4,T109 INPUT
sram_otp_key_i.nonce[127:0] Yes Yes T1,T109,T7 Yes T1,T109,T110 INPUT
sram_otp_key_i.key[127:0] Yes Yes T1,T2,T4 Yes T7,T46,T13 INPUT
sram_otp_key_i.ack Yes Yes T210,T138,T211 Yes T210,T138,T211 INPUT
cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.test No No No INPUT
cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.test No No No INPUT

*Tests covering at least one bit in the range
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