Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.91	92.47		89.25			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.91	92.47		89.25			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.91	92.47		89.25			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.91	92.47		89.25			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T73,T32,T173	Yes	T73,T32,T173	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T73,T32,T173	Yes	T73,T32,T173	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T97,*T98,*T99	Yes	T97,T98,T99	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	INPUT
tl_i.a_valid	Yes	Yes	T73,T32,T30	Yes	T73,T32,T30	INPUT
tl_o.a_ready	Yes	Yes	T73,T32,T30	Yes	T73,T32,T30	OUTPUT
tl_o.d_error	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T73,T32,T173	Yes	T73,T32,T173	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T73,T32,T173	Yes	T73,T32,T30	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T73,T32,T173	Yes	T73,T32,T30	OUTPUT
tl_o.d_sink	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T96,*T58,*T310	Yes	T96,T58,T310	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T73,*T32,*T173	Yes	T73,T32,T173	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T73,T32,T30	Yes	T73,T32,T30	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T80,T106,T264	Yes	T80,T106,T264	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T106,T264,T107	Yes	T106,T107,T108	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T106,T107,T108	Yes	T106,T264,T107	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T80,T106,T264	Yes	T80,T106,T264	OUTPUT
cio_rx_i	Yes	Yes	T28,T46,T73	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T73,T32,T173	Yes	T73,T32,T173	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T73,T32,T173	Yes	T73,T32,T173	OUTPUT
intr_tx_empty_o	Yes	Yes	T73,T32,T173	Yes	T73,T32,T173	OUTPUT
intr_rx_watermark_o	Yes	Yes	T73,T32,T173	Yes	T73,T32,T173	OUTPUT
intr_tx_done_o	Yes	Yes	T73,T32,T173	Yes	T73,T32,T173	OUTPUT
intr_rx_overflow_o	Yes	Yes	T73,T32,T173	Yes	T73,T32,T173	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T246,T255,T256	Yes	T246,T255,T256	OUTPUT
intr_rx_break_err_o	Yes	Yes	T246,T255,T256	Yes	T246,T255,T256	OUTPUT
intr_rx_timeout_o	Yes	Yes	T246,T255,T256	Yes	T246,T255,T256	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T246,T255,T256	Yes	T246,T255,T256	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T173,T231,T246	Yes	T173,T231,T246	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T173,T231,T246	Yes	T173,T231,T246	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T97,*T98,*T99	Yes	T97,T98,T99	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	INPUT
tl_i.a_valid	Yes	Yes	T173,T80,T231	Yes	T173,T80,T231	INPUT
tl_o.a_ready	Yes	Yes	T173,T80,T192	Yes	T173,T80,T192	OUTPUT
tl_o.d_error	Yes	Yes	T98,T102,T105	Yes	T98,T102,T105	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T173,T246,T252	Yes	T173,T246,T252	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T173,T192,T246	Yes	T173,T80,T192	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T173,T192,T246	Yes	T173,T80,T192	OUTPUT
tl_o.d_sink	Yes	Yes	T97,T98,T102	Yes	T98,T99,T102	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T96,*T58,*T310	Yes	T96,T58,T310	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T98,T102,T105	Yes	T97,T98,T102	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T173,*T246,*T252	Yes	T173,T246,T252	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T173,T80,T192	Yes	T173,T80,T192	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T80,T106,T264	Yes	T80,T106,T264	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T106,T264,T107	Yes	T106,T107,T394	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T106,T107,T394	Yes	T106,T264,T107	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T80,T106,T264	Yes	T80,T106,T264	OUTPUT
cio_rx_i	Yes	Yes	T46,T41,T173	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T173,T57,T58	Yes	T173,T57,T58	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T173,T246,T252	Yes	T173,T246,T252	OUTPUT
intr_tx_empty_o	Yes	Yes	T173,T246,T96	Yes	T173,T246,T96	OUTPUT
intr_rx_watermark_o	Yes	Yes	T173,T246,T253	Yes	T173,T246,T253	OUTPUT
intr_tx_done_o	Yes	Yes	T173,T246,T254	Yes	T173,T246,T254	OUTPUT
intr_rx_overflow_o	Yes	Yes	T173,T246,T254	Yes	T173,T246,T254	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T246,T255,T256	Yes	T246,T255,T256	OUTPUT
intr_rx_break_err_o	Yes	Yes	T246,T255,T256	Yes	T246,T255,T256	OUTPUT
intr_rx_timeout_o	Yes	Yes	T246,T255,T256	Yes	T246,T255,T256	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T246,T255,T256	Yes	T246,T255,T256	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T73,T246,T96	Yes	T73,T246,T96	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T73,T246,T96	Yes	T73,T246,T96	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T97,*T98,*T99	Yes	T97,T98,T99	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	INPUT
tl_i.a_valid	Yes	Yes	T73,T80,T192	Yes	T73,T80,T192	INPUT
tl_o.a_ready	Yes	Yes	T73,T80,T192	Yes	T73,T80,T192	OUTPUT
tl_o.d_error	Yes	Yes	T97,T104,T103	Yes	T97,T104,T103	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T73,T246,T96	Yes	T73,T246,T96	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T73,T192,T246	Yes	T73,T80,T192	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T73,T192,T246	Yes	T73,T80,T192	OUTPUT
tl_o.d_sink	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T96,*T97,*T105	Yes	T96,T97,T98	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T73,*T246,*T96	Yes	T73,T246,T96	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T73,T80,T192	Yes	T73,T80,T192	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T80,T106,T192	Yes	T80,T106,T192	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T106,T107,T108	Yes	T106,T107,T108	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T106,T107,T108	Yes	T106,T107,T108	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T80,T106,T192	Yes	T80,T106,T192	OUTPUT
cio_rx_i	Yes	Yes	T28,T73,T174	Yes	T7,T28,T73	INPUT
cio_tx_o	Yes	Yes	T73,T174,T175	Yes	T73,T174,T175	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T73,T246,T96	Yes	T73,T246,T96	OUTPUT
intr_tx_empty_o	Yes	Yes	T73,T246,T174	Yes	T73,T246,T174	OUTPUT
intr_rx_watermark_o	Yes	Yes	T73,T246,T174	Yes	T73,T246,T174	OUTPUT
intr_tx_done_o	Yes	Yes	T73,T246,T174	Yes	T73,T246,T174	OUTPUT
intr_rx_overflow_o	Yes	Yes	T73,T246,T174	Yes	T73,T246,T174	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T246,T255,T256	Yes	T246,T255,T256	OUTPUT
intr_rx_break_err_o	Yes	Yes	T246,T255,T256	Yes	T246,T255,T256	OUTPUT
intr_rx_timeout_o	Yes	Yes	T246,T255,T256	Yes	T246,T255,T256	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T246,T255,T256	Yes	T246,T255,T256	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T32,T66,T246	Yes	T32,T66,T246	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T32,T66,T246	Yes	T32,T66,T246	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T97,*T98,*T99	Yes	T97,T98,T99	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	INPUT
tl_i.a_valid	Yes	Yes	T32,T66,T80	Yes	T32,T66,T80	INPUT
tl_o.a_ready	Yes	Yes	T32,T66,T80	Yes	T32,T66,T80	OUTPUT
tl_o.d_error	Yes	Yes	T97,T98,T102	Yes	T97,T98,T184	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T32,T66,T246	Yes	T32,T66,T246	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T32,T66,T192	Yes	T32,T66,T80	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T32,T66,T192	Yes	T32,T66,T80	OUTPUT
tl_o.d_sink	Yes	Yes	T97,T98,T99	Yes	T97,T98,T105	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T96,*T97,*T105	Yes	T96,T97,T98	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T97,T98,T104	Yes	T97,T98,T99	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T32,*T66,*T246	Yes	T32,T66,T246	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T32,T66,T80	Yes	T32,T66,T80	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T80,T106,T192	Yes	T80,T106,T192	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T106,T107,T108	Yes	T106,T107,T108	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T106,T107,T108	Yes	T106,T107,T108	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T80,T106,T192	Yes	T80,T106,T192	OUTPUT
cio_rx_i	Yes	Yes	T32,T66,T67	Yes	T32,T66,T67	INPUT
cio_tx_o	Yes	Yes	T32,T66,T67	Yes	T32,T66,T67	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T32,T66,T246	Yes	T32,T66,T246	OUTPUT
intr_tx_empty_o	Yes	Yes	T32,T66,T246	Yes	T32,T66,T246	OUTPUT
intr_rx_watermark_o	Yes	Yes	T32,T66,T246	Yes	T32,T66,T246	OUTPUT
intr_tx_done_o	Yes	Yes	T32,T66,T246	Yes	T32,T66,T246	OUTPUT
intr_rx_overflow_o	Yes	Yes	T32,T66,T246	Yes	T32,T66,T246	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T246,T255,T256	Yes	T246,T255,T256	OUTPUT
intr_rx_break_err_o	Yes	Yes	T246,T255,T256	Yes	T246,T255,T256	OUTPUT
intr_rx_timeout_o	Yes	Yes	T246,T255,T256	Yes	T246,T255,T256	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T246,T255,T256	Yes	T246,T255,T256	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T30,T68,T246	Yes	T30,T68,T246	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T30,T68,T246	Yes	T30,T68,T246	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T97,*T98,*T99	Yes	T97,T98,T99	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	INPUT
tl_i.a_valid	Yes	Yes	T30,T68,T80	Yes	T30,T68,T80	INPUT
tl_o.a_ready	Yes	Yes	T30,T68,T80	Yes	T30,T68,T80	OUTPUT
tl_o.d_error	Yes	Yes	T97,T98,T102	Yes	T98,T102,T104	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T30,T68,T246	Yes	T30,T68,T246	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T30,T68,T192	Yes	T30,T68,T80	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T30,T68,T192	Yes	T30,T68,T80	OUTPUT
tl_o.d_sink	Yes	Yes	T97,T98,T105	Yes	T98,T102,T104	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T96,*T105,*T103	Yes	T96,T97,T98	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T98,T99,T102	Yes	T97,T98,T102	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T30,*T68,*T246	Yes	T30,T68,T246	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T30,T68,T80	Yes	T30,T68,T80	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T80,T106,T192	Yes	T80,T106,T192	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T106,T107,T108	Yes	T106,T107,T108	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T106,T107,T108	Yes	T106,T107,T108	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T80,T106,T192	Yes	T80,T106,T192	OUTPUT
cio_rx_i	Yes	Yes	T30,T68,T371	Yes	T30,T68,T371	INPUT
cio_tx_o	Yes	Yes	T30,T68,T96	Yes	T30,T68,T96	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T30,T68,T246	Yes	T30,T68,T246	OUTPUT
intr_tx_empty_o	Yes	Yes	T30,T68,T246	Yes	T30,T68,T246	OUTPUT
intr_rx_watermark_o	Yes	Yes	T30,T68,T246	Yes	T30,T68,T246	OUTPUT
intr_tx_done_o	Yes	Yes	T30,T68,T246	Yes	T30,T68,T246	OUTPUT
intr_rx_overflow_o	Yes	Yes	T30,T68,T246	Yes	T30,T68,T246	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T246,T255,T256	Yes	T246,T255,T256	OUTPUT
intr_rx_break_err_o	Yes	Yes	T246,T255,T256	Yes	T246,T255,T256	OUTPUT
intr_rx_timeout_o	Yes	Yes	T246,T255,T256	Yes	T246,T255,T256	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T246,T255,T256	Yes	T246,T255,T256	OUTPUT

*Tests covering at least one bit in the range