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 LINE       1303
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T87
1	0	1	Covered	T46,T47,T87
1	1	0	Covered	T481,T564,T490
1	1	1	Covered	T471,T75,T178

 LINE       1308
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T46,T47,T87
1	0	1	Covered	T47,T265,T74
1	1	0	Covered	T570,T564,T418
1	1	1	Covered	T74,T407,T158

 LINE       1317
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T74,T102,T481
1	1	0	Covered	T666
1	1	1	Covered	T1,T7,T28

 LINE       1318
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T74,T481,T475
1	1	0	Covered	T667
1	1	1	Covered	T1,T7,T28

 LINE       1319
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T7,T28
1	0	1	Covered	T74,T456,T570
1	1	0	Covered	T668
1	1	1	Covered	T1,T2,T4