Line Coverage for Module :
rv_core_ibex_cfg_reg_top
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 178 | 178 | 100.00 |
| ALWAYS | 73 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 103 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 104 | 1 | 1 | 100.00 |
| ALWAYS | 130 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 263 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 278 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 294 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 310 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 326 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 447 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 511 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 543 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 575 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 607 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 697 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 729 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 761 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 793 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 825 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 857 | 1 | 1 | 100.00 |
| ALWAYS | 1174 | 26 | 26 | 100.00 |
| CONT_ASSIGN | 1202 | 1 | 1 | 100.00 |
| ALWAYS | 1206 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1235 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1237 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1239 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1241 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1243 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1244 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1246 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1247 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1249 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1250 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1252 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1253 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1255 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1256 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1258 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1259 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1261 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1262 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1264 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1265 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1267 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1268 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1270 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1271 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1273 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1274 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1276 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1277 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1279 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1280 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1282 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1283 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1285 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1286 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1288 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1289 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1291 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1292 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1294 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1295 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1297 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1298 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1300 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1302 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1303 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1305 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1307 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1308 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1310 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1312 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1314 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1316 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1317 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1318 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1319 | 1 | 1 | 100.00 |
| ALWAYS | 1323 | 26 | 26 | 100.00 |
| ALWAYS | 1353 | 36 | 36 | 100.00 |
| CONT_ASSIGN | 1475 | 0 | 0 | |
| CONT_ASSIGN | 1483 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1484 | 1 | 1 | 100.00 |
72 always_ff @(posedge clk_i or negedge rst_ni) begin
73 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
74 1/1 err_q <= '0;
Tests: T1 T2 T3
75 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
76 1/1 err_q <= 1'b1;
Tests: T306 T307 T308
77 end
MISSING_ELSE
78 end
79
80 // integrity error output is permanent and should be used for alert generation
81 // register errors are transactional
82 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T2 T3
83
84 // outgoing integrity generation
85 tlul_pkg::tl_d2h_t tl_o_pre;
86 tlul_rsp_intg_gen #(
87 .EnableRspIntgGen(1),
88 .EnableDataIntgGen(1)
89 ) u_rsp_intg_gen (
90 .tl_i(tl_o_pre),
91 .tl_o(tl_o)
92 );
93
94 tlul_pkg::tl_h2d_t tl_socket_h2d [2];
95 tlul_pkg::tl_d2h_t tl_socket_d2h [2];
96
97 logic [0:0] reg_steer;
98
99 // socket_1n connection
100 1/1 assign tl_reg_h2d = tl_socket_h2d[1];
Tests: T1 T2 T3
101 1/1 assign tl_socket_d2h[1] = tl_reg_d2h;
Tests: T1 T2 T4
102
103 1/1 assign tl_win_o = tl_socket_h2d[0];
Tests: T1 T2 T3
104 1/1 assign tl_socket_d2h[0] = tl_win_i;
Tests: T1 T2 T3
105
106 // Create Socket_1n
107 tlul_socket_1n #(
108 .N (2),
109 .HReqPass (1'b1),
110 .HRspPass (1'b1),
111 .DReqPass ({2{1'b1}}),
112 .DRspPass ({2{1'b1}}),
113 .HReqDepth (4'h0),
114 .HRspDepth (4'h0),
115 .DReqDepth ({2{4'h0}}),
116 .DRspDepth ({2{4'h0}}),
117 .ExplicitErrs (1'b0)
118 ) u_socket (
119 .clk_i (clk_i),
120 .rst_ni (rst_ni),
121 .tl_h_i (tl_i),
122 .tl_h_o (tl_o_pre),
123 .tl_d_o (tl_socket_h2d),
124 .tl_d_i (tl_socket_d2h),
125 .dev_select_i (reg_steer)
126 );
127
128 // Create steering logic
129 always_comb begin
130 1/1 reg_steer =
Tests: T1 T2 T3
131 tl_i.a_address[AW-1:0] inside {[128:159]} ? 1'd0 :
132 // Default set to register
133 1'd1;
134
135 // Override this in case of an integrity error
136 1/1 if (intg_err) begin
Tests: T1 T2 T3
137 1/1 reg_steer = 1'd1;
Tests: T184 T309 T479
138 end
MISSING_ELSE
139 end
140
141 tlul_adapter_reg #(
142 .RegAw(AW),
143 .RegDw(DW),
144 .EnableDataIntgGen(0)
145 ) u_reg_if (
146 .clk_i (clk_i),
147 .rst_ni (rst_ni),
148
149 .tl_i (tl_reg_h2d),
150 .tl_o (tl_reg_d2h),
151
152 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
153 .intg_error_o(),
154
155 .we_o (reg_we),
156 .re_o (reg_re),
157 .addr_o (reg_addr),
158 .wdata_o (reg_wdata),
159 .be_o (reg_be),
160 .busy_i (reg_busy),
161 .rdata_i (reg_rdata),
162 .error_i (reg_error)
163 );
164
165 // cdc oversampling signals
166
167 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T1 T2 T3
168 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T1 T2 T3
169
170 // Define SW related signals
171 // Format: <reg>_<field>_{wd|we|qs}
172 // or <reg>_{wd|we|qs} if field == 1 or 0
173 logic alert_test_we;
174 logic alert_test_fatal_sw_err_wd;
175 logic alert_test_recov_sw_err_wd;
176 logic alert_test_fatal_hw_err_wd;
177 logic alert_test_recov_hw_err_wd;
178 logic sw_recov_err_we;
179 logic [3:0] sw_recov_err_qs;
180 logic [3:0] sw_recov_err_wd;
181 logic sw_fatal_err_we;
182 logic [3:0] sw_fatal_err_qs;
183 logic [3:0] sw_fatal_err_wd;
184 logic ibus_regwen_0_we;
185 logic ibus_regwen_0_qs;
186 logic ibus_regwen_0_wd;
187 logic ibus_regwen_1_we;
188 logic ibus_regwen_1_qs;
189 logic ibus_regwen_1_wd;
190 logic ibus_addr_en_0_we;
191 logic ibus_addr_en_0_qs;
192 logic ibus_addr_en_0_wd;
193 logic ibus_addr_en_1_we;
194 logic ibus_addr_en_1_qs;
195 logic ibus_addr_en_1_wd;
196 logic ibus_addr_matching_0_we;
197 logic [31:0] ibus_addr_matching_0_qs;
198 logic [31:0] ibus_addr_matching_0_wd;
199 logic ibus_addr_matching_1_we;
200 logic [31:0] ibus_addr_matching_1_qs;
201 logic [31:0] ibus_addr_matching_1_wd;
202 logic ibus_remap_addr_0_we;
203 logic [31:0] ibus_remap_addr_0_qs;
204 logic [31:0] ibus_remap_addr_0_wd;
205 logic ibus_remap_addr_1_we;
206 logic [31:0] ibus_remap_addr_1_qs;
207 logic [31:0] ibus_remap_addr_1_wd;
208 logic dbus_regwen_0_we;
209 logic dbus_regwen_0_qs;
210 logic dbus_regwen_0_wd;
211 logic dbus_regwen_1_we;
212 logic dbus_regwen_1_qs;
213 logic dbus_regwen_1_wd;
214 logic dbus_addr_en_0_we;
215 logic dbus_addr_en_0_qs;
216 logic dbus_addr_en_0_wd;
217 logic dbus_addr_en_1_we;
218 logic dbus_addr_en_1_qs;
219 logic dbus_addr_en_1_wd;
220 logic dbus_addr_matching_0_we;
221 logic [31:0] dbus_addr_matching_0_qs;
222 logic [31:0] dbus_addr_matching_0_wd;
223 logic dbus_addr_matching_1_we;
224 logic [31:0] dbus_addr_matching_1_qs;
225 logic [31:0] dbus_addr_matching_1_wd;
226 logic dbus_remap_addr_0_we;
227 logic [31:0] dbus_remap_addr_0_qs;
228 logic [31:0] dbus_remap_addr_0_wd;
229 logic dbus_remap_addr_1_we;
230 logic [31:0] dbus_remap_addr_1_qs;
231 logic [31:0] dbus_remap_addr_1_wd;
232 logic nmi_enable_we;
233 logic nmi_enable_alert_en_qs;
234 logic nmi_enable_alert_en_wd;
235 logic nmi_enable_wdog_en_qs;
236 logic nmi_enable_wdog_en_wd;
237 logic nmi_state_we;
238 logic nmi_state_alert_qs;
239 logic nmi_state_alert_wd;
240 logic nmi_state_wdog_qs;
241 logic nmi_state_wdog_wd;
242 logic err_status_we;
243 logic err_status_reg_intg_err_qs;
244 logic err_status_reg_intg_err_wd;
245 logic err_status_fatal_intg_err_qs;
246 logic err_status_fatal_intg_err_wd;
247 logic err_status_fatal_core_err_qs;
248 logic err_status_fatal_core_err_wd;
249 logic err_status_recov_core_err_qs;
250 logic err_status_recov_core_err_wd;
251 logic rnd_data_re;
252 logic [31:0] rnd_data_qs;
253 logic rnd_status_re;
254 logic rnd_status_rnd_data_valid_qs;
255 logic rnd_status_rnd_data_fips_qs;
256 logic fpga_info_re;
257 logic [31:0] fpga_info_qs;
258
259 // Register instances
260 // R[alert_test]: V(True)
261 logic alert_test_qe;
262 logic [3:0] alert_test_flds_we;
263 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T80 T231 T192
264 // F[fatal_sw_err]: 0:0
265 prim_subreg_ext #(
266 .DW (1)
267 ) u_alert_test_fatal_sw_err (
268 .re (1'b0),
269 .we (alert_test_we),
270 .wd (alert_test_fatal_sw_err_wd),
271 .d ('0),
272 .qre (),
273 .qe (alert_test_flds_we[0]),
274 .q (reg2hw.alert_test.fatal_sw_err.q),
275 .ds (),
276 .qs ()
277 );
278 1/1 assign reg2hw.alert_test.fatal_sw_err.qe = alert_test_qe;
Tests: T80 T231 T192
279
280 // F[recov_sw_err]: 1:1
281 prim_subreg_ext #(
282 .DW (1)
283 ) u_alert_test_recov_sw_err (
284 .re (1'b0),
285 .we (alert_test_we),
286 .wd (alert_test_recov_sw_err_wd),
287 .d ('0),
288 .qre (),
289 .qe (alert_test_flds_we[1]),
290 .q (reg2hw.alert_test.recov_sw_err.q),
291 .ds (),
292 .qs ()
293 );
294 1/1 assign reg2hw.alert_test.recov_sw_err.qe = alert_test_qe;
Tests: T80 T231 T192
295
296 // F[fatal_hw_err]: 2:2
297 prim_subreg_ext #(
298 .DW (1)
299 ) u_alert_test_fatal_hw_err (
300 .re (1'b0),
301 .we (alert_test_we),
302 .wd (alert_test_fatal_hw_err_wd),
303 .d ('0),
304 .qre (),
305 .qe (alert_test_flds_we[2]),
306 .q (reg2hw.alert_test.fatal_hw_err.q),
307 .ds (),
308 .qs ()
309 );
310 1/1 assign reg2hw.alert_test.fatal_hw_err.qe = alert_test_qe;
Tests: T80 T231 T192
311
312 // F[recov_hw_err]: 3:3
313 prim_subreg_ext #(
314 .DW (1)
315 ) u_alert_test_recov_hw_err (
316 .re (1'b0),
317 .we (alert_test_we),
318 .wd (alert_test_recov_hw_err_wd),
319 .d ('0),
320 .qre (),
321 .qe (alert_test_flds_we[3]),
322 .q (reg2hw.alert_test.recov_hw_err.q),
323 .ds (),
324 .qs ()
325 );
326 1/1 assign reg2hw.alert_test.recov_hw_err.qe = alert_test_qe;
Tests: T80 T231 T192
327
328
329 // R[sw_recov_err]: V(False)
330 prim_subreg #(
331 .DW (4),
332 .SwAccess(prim_subreg_pkg::SwAccessRW),
333 .RESVAL (4'h9),
334 .Mubi (1'b1)
335 ) u_sw_recov_err (
336 .clk_i (clk_i),
337 .rst_ni (rst_ni),
338
339 // from register interface
340 .we (sw_recov_err_we),
341 .wd (sw_recov_err_wd),
342
343 // from internal hardware
344 .de (hw2reg.sw_recov_err.de),
345 .d (hw2reg.sw_recov_err.d),
346
347 // to internal hardware
348 .qe (),
349 .q (reg2hw.sw_recov_err.q),
350 .ds (),
351
352 // to register interface (read)
353 .qs (sw_recov_err_qs)
354 );
355
356
357 // R[sw_fatal_err]: V(False)
358 prim_subreg #(
359 .DW (4),
360 .SwAccess(prim_subreg_pkg::SwAccessW1S),
361 .RESVAL (4'h9),
362 .Mubi (1'b1)
363 ) u_sw_fatal_err (
364 .clk_i (clk_i),
365 .rst_ni (rst_ni),
366
367 // from register interface
368 .we (sw_fatal_err_we),
369 .wd (sw_fatal_err_wd),
370
371 // from internal hardware
372 .de (1'b0),
373 .d ('0),
374
375 // to internal hardware
376 .qe (),
377 .q (reg2hw.sw_fatal_err.q),
378 .ds (),
379
380 // to register interface (read)
381 .qs (sw_fatal_err_qs)
382 );
383
384
385 // Subregister 0 of Multireg ibus_regwen
386 // R[ibus_regwen_0]: V(False)
387 prim_subreg #(
388 .DW (1),
389 .SwAccess(prim_subreg_pkg::SwAccessW0C),
390 .RESVAL (1'h1),
391 .Mubi (1'b0)
392 ) u_ibus_regwen_0 (
393 .clk_i (clk_i),
394 .rst_ni (rst_ni),
395
396 // from register interface
397 .we (ibus_regwen_0_we),
398 .wd (ibus_regwen_0_wd),
399
400 // from internal hardware
401 .de (1'b0),
402 .d ('0),
403
404 // to internal hardware
405 .qe (),
406 .q (),
407 .ds (),
408
409 // to register interface (read)
410 .qs (ibus_regwen_0_qs)
411 );
412
413
414 // Subregister 1 of Multireg ibus_regwen
415 // R[ibus_regwen_1]: V(False)
416 prim_subreg #(
417 .DW (1),
418 .SwAccess(prim_subreg_pkg::SwAccessW0C),
419 .RESVAL (1'h1),
420 .Mubi (1'b0)
421 ) u_ibus_regwen_1 (
422 .clk_i (clk_i),
423 .rst_ni (rst_ni),
424
425 // from register interface
426 .we (ibus_regwen_1_we),
427 .wd (ibus_regwen_1_wd),
428
429 // from internal hardware
430 .de (1'b0),
431 .d ('0),
432
433 // to internal hardware
434 .qe (),
435 .q (),
436 .ds (),
437
438 // to register interface (read)
439 .qs (ibus_regwen_1_qs)
440 );
441
442
443 // Subregister 0 of Multireg ibus_addr_en
444 // R[ibus_addr_en_0]: V(False)
445 // Create REGWEN-gated WE signal
446 logic ibus_addr_en_0_gated_we;
447 1/1 assign ibus_addr_en_0_gated_we = ibus_addr_en_0_we & ibus_regwen_0_qs;
Tests: T214 T301 T74
448 prim_subreg #(
449 .DW (1),
450 .SwAccess(prim_subreg_pkg::SwAccessRW),
451 .RESVAL (1'h0),
452 .Mubi (1'b0)
453 ) u_ibus_addr_en_0 (
454 .clk_i (clk_i),
455 .rst_ni (rst_ni),
456
457 // from register interface
458 .we (ibus_addr_en_0_gated_we),
459 .wd (ibus_addr_en_0_wd),
460
461 // from internal hardware
462 .de (1'b0),
463 .d ('0),
464
465 // to internal hardware
466 .qe (),
467 .q (reg2hw.ibus_addr_en[0].q),
468 .ds (),
469
470 // to register interface (read)
471 .qs (ibus_addr_en_0_qs)
472 );
473
474
475 // Subregister 1 of Multireg ibus_addr_en
476 // R[ibus_addr_en_1]: V(False)
477 // Create REGWEN-gated WE signal
478 logic ibus_addr_en_1_gated_we;
479 1/1 assign ibus_addr_en_1_gated_we = ibus_addr_en_1_we & ibus_regwen_1_qs;
Tests: T214 T301 T74
480 prim_subreg #(
481 .DW (1),
482 .SwAccess(prim_subreg_pkg::SwAccessRW),
483 .RESVAL (1'h0),
484 .Mubi (1'b0)
485 ) u_ibus_addr_en_1 (
486 .clk_i (clk_i),
487 .rst_ni (rst_ni),
488
489 // from register interface
490 .we (ibus_addr_en_1_gated_we),
491 .wd (ibus_addr_en_1_wd),
492
493 // from internal hardware
494 .de (1'b0),
495 .d ('0),
496
497 // to internal hardware
498 .qe (),
499 .q (reg2hw.ibus_addr_en[1].q),
500 .ds (),
501
502 // to register interface (read)
503 .qs (ibus_addr_en_1_qs)
504 );
505
506
507 // Subregister 0 of Multireg ibus_addr_matching
508 // R[ibus_addr_matching_0]: V(False)
509 // Create REGWEN-gated WE signal
510 logic ibus_addr_matching_0_gated_we;
511 1/1 assign ibus_addr_matching_0_gated_we = ibus_addr_matching_0_we & ibus_regwen_0_qs;
Tests: T214 T301 T74
512 prim_subreg #(
513 .DW (32),
514 .SwAccess(prim_subreg_pkg::SwAccessRW),
515 .RESVAL (32'h0),
516 .Mubi (1'b0)
517 ) u_ibus_addr_matching_0 (
518 .clk_i (clk_i),
519 .rst_ni (rst_ni),
520
521 // from register interface
522 .we (ibus_addr_matching_0_gated_we),
523 .wd (ibus_addr_matching_0_wd),
524
525 // from internal hardware
526 .de (1'b0),
527 .d ('0),
528
529 // to internal hardware
530 .qe (),
531 .q (reg2hw.ibus_addr_matching[0].q),
532 .ds (),
533
534 // to register interface (read)
535 .qs (ibus_addr_matching_0_qs)
536 );
537
538
539 // Subregister 1 of Multireg ibus_addr_matching
540 // R[ibus_addr_matching_1]: V(False)
541 // Create REGWEN-gated WE signal
542 logic ibus_addr_matching_1_gated_we;
543 1/1 assign ibus_addr_matching_1_gated_we = ibus_addr_matching_1_we & ibus_regwen_1_qs;
Tests: T214 T301 T74
544 prim_subreg #(
545 .DW (32),
546 .SwAccess(prim_subreg_pkg::SwAccessRW),
547 .RESVAL (32'h0),
548 .Mubi (1'b0)
549 ) u_ibus_addr_matching_1 (
550 .clk_i (clk_i),
551 .rst_ni (rst_ni),
552
553 // from register interface
554 .we (ibus_addr_matching_1_gated_we),
555 .wd (ibus_addr_matching_1_wd),
556
557 // from internal hardware
558 .de (1'b0),
559 .d ('0),
560
561 // to internal hardware
562 .qe (),
563 .q (reg2hw.ibus_addr_matching[1].q),
564 .ds (),
565
566 // to register interface (read)
567 .qs (ibus_addr_matching_1_qs)
568 );
569
570
571 // Subregister 0 of Multireg ibus_remap_addr
572 // R[ibus_remap_addr_0]: V(False)
573 // Create REGWEN-gated WE signal
574 logic ibus_remap_addr_0_gated_we;
575 1/1 assign ibus_remap_addr_0_gated_we = ibus_remap_addr_0_we & ibus_regwen_0_qs;
Tests: T214 T301 T74
576 prim_subreg #(
577 .DW (32),
578 .SwAccess(prim_subreg_pkg::SwAccessRW),
579 .RESVAL (32'h0),
580 .Mubi (1'b0)
581 ) u_ibus_remap_addr_0 (
582 .clk_i (clk_i),
583 .rst_ni (rst_ni),
584
585 // from register interface
586 .we (ibus_remap_addr_0_gated_we),
587 .wd (ibus_remap_addr_0_wd),
588
589 // from internal hardware
590 .de (1'b0),
591 .d ('0),
592
593 // to internal hardware
594 .qe (),
595 .q (reg2hw.ibus_remap_addr[0].q),
596 .ds (),
597
598 // to register interface (read)
599 .qs (ibus_remap_addr_0_qs)
600 );
601
602
603 // Subregister 1 of Multireg ibus_remap_addr
604 // R[ibus_remap_addr_1]: V(False)
605 // Create REGWEN-gated WE signal
606 logic ibus_remap_addr_1_gated_we;
607 1/1 assign ibus_remap_addr_1_gated_we = ibus_remap_addr_1_we & ibus_regwen_1_qs;
Tests: T214 T301 T74
608 prim_subreg #(
609 .DW (32),
610 .SwAccess(prim_subreg_pkg::SwAccessRW),
611 .RESVAL (32'h0),
612 .Mubi (1'b0)
613 ) u_ibus_remap_addr_1 (
614 .clk_i (clk_i),
615 .rst_ni (rst_ni),
616
617 // from register interface
618 .we (ibus_remap_addr_1_gated_we),
619 .wd (ibus_remap_addr_1_wd),
620
621 // from internal hardware
622 .de (1'b0),
623 .d ('0),
624
625 // to internal hardware
626 .qe (),
627 .q (reg2hw.ibus_remap_addr[1].q),
628 .ds (),
629
630 // to register interface (read)
631 .qs (ibus_remap_addr_1_qs)
632 );
633
634
635 // Subregister 0 of Multireg dbus_regwen
636 // R[dbus_regwen_0]: V(False)
637 prim_subreg #(
638 .DW (1),
639 .SwAccess(prim_subreg_pkg::SwAccessW0C),
640 .RESVAL (1'h1),
641 .Mubi (1'b0)
642 ) u_dbus_regwen_0 (
643 .clk_i (clk_i),
644 .rst_ni (rst_ni),
645
646 // from register interface
647 .we (dbus_regwen_0_we),
648 .wd (dbus_regwen_0_wd),
649
650 // from internal hardware
651 .de (1'b0),
652 .d ('0),
653
654 // to internal hardware
655 .qe (),
656 .q (),
657 .ds (),
658
659 // to register interface (read)
660 .qs (dbus_regwen_0_qs)
661 );
662
663
664 // Subregister 1 of Multireg dbus_regwen
665 // R[dbus_regwen_1]: V(False)
666 prim_subreg #(
667 .DW (1),
668 .SwAccess(prim_subreg_pkg::SwAccessW0C),
669 .RESVAL (1'h1),
670 .Mubi (1'b0)
671 ) u_dbus_regwen_1 (
672 .clk_i (clk_i),
673 .rst_ni (rst_ni),
674
675 // from register interface
676 .we (dbus_regwen_1_we),
677 .wd (dbus_regwen_1_wd),
678
679 // from internal hardware
680 .de (1'b0),
681 .d ('0),
682
683 // to internal hardware
684 .qe (),
685 .q (),
686 .ds (),
687
688 // to register interface (read)
689 .qs (dbus_regwen_1_qs)
690 );
691
692
693 // Subregister 0 of Multireg dbus_addr_en
694 // R[dbus_addr_en_0]: V(False)
695 // Create REGWEN-gated WE signal
696 logic dbus_addr_en_0_gated_we;
697 1/1 assign dbus_addr_en_0_gated_we = dbus_addr_en_0_we & dbus_regwen_0_qs;
Tests: T214 T301 T74
698 prim_subreg #(
699 .DW (1),
700 .SwAccess(prim_subreg_pkg::SwAccessRW),
701 .RESVAL (1'h0),
702 .Mubi (1'b0)
703 ) u_dbus_addr_en_0 (
704 .clk_i (clk_i),
705 .rst_ni (rst_ni),
706
707 // from register interface
708 .we (dbus_addr_en_0_gated_we),
709 .wd (dbus_addr_en_0_wd),
710
711 // from internal hardware
712 .de (1'b0),
713 .d ('0),
714
715 // to internal hardware
716 .qe (),
717 .q (reg2hw.dbus_addr_en[0].q),
718 .ds (),
719
720 // to register interface (read)
721 .qs (dbus_addr_en_0_qs)
722 );
723
724
725 // Subregister 1 of Multireg dbus_addr_en
726 // R[dbus_addr_en_1]: V(False)
727 // Create REGWEN-gated WE signal
728 logic dbus_addr_en_1_gated_we;
729 1/1 assign dbus_addr_en_1_gated_we = dbus_addr_en_1_we & dbus_regwen_1_qs;
Tests: T214 T301 T74
730 prim_subreg #(
731 .DW (1),
732 .SwAccess(prim_subreg_pkg::SwAccessRW),
733 .RESVAL (1'h0),
734 .Mubi (1'b0)
735 ) u_dbus_addr_en_1 (
736 .clk_i (clk_i),
737 .rst_ni (rst_ni),
738
739 // from register interface
740 .we (dbus_addr_en_1_gated_we),
741 .wd (dbus_addr_en_1_wd),
742
743 // from internal hardware
744 .de (1'b0),
745 .d ('0),
746
747 // to internal hardware
748 .qe (),
749 .q (reg2hw.dbus_addr_en[1].q),
750 .ds (),
751
752 // to register interface (read)
753 .qs (dbus_addr_en_1_qs)
754 );
755
756
757 // Subregister 0 of Multireg dbus_addr_matching
758 // R[dbus_addr_matching_0]: V(False)
759 // Create REGWEN-gated WE signal
760 logic dbus_addr_matching_0_gated_we;
761 1/1 assign dbus_addr_matching_0_gated_we = dbus_addr_matching_0_we & dbus_regwen_0_qs;
Tests: T214 T301 T74
762 prim_subreg #(
763 .DW (32),
764 .SwAccess(prim_subreg_pkg::SwAccessRW),
765 .RESVAL (32'h0),
766 .Mubi (1'b0)
767 ) u_dbus_addr_matching_0 (
768 .clk_i (clk_i),
769 .rst_ni (rst_ni),
770
771 // from register interface
772 .we (dbus_addr_matching_0_gated_we),
773 .wd (dbus_addr_matching_0_wd),
774
775 // from internal hardware
776 .de (1'b0),
777 .d ('0),
778
779 // to internal hardware
780 .qe (),
781 .q (reg2hw.dbus_addr_matching[0].q),
782 .ds (),
783
784 // to register interface (read)
785 .qs (dbus_addr_matching_0_qs)
786 );
787
788
789 // Subregister 1 of Multireg dbus_addr_matching
790 // R[dbus_addr_matching_1]: V(False)
791 // Create REGWEN-gated WE signal
792 logic dbus_addr_matching_1_gated_we;
793 1/1 assign dbus_addr_matching_1_gated_we = dbus_addr_matching_1_we & dbus_regwen_1_qs;
Tests: T214 T301 T74
794 prim_subreg #(
795 .DW (32),
796 .SwAccess(prim_subreg_pkg::SwAccessRW),
797 .RESVAL (32'h0),
798 .Mubi (1'b0)
799 ) u_dbus_addr_matching_1 (
800 .clk_i (clk_i),
801 .rst_ni (rst_ni),
802
803 // from register interface
804 .we (dbus_addr_matching_1_gated_we),
805 .wd (dbus_addr_matching_1_wd),
806
807 // from internal hardware
808 .de (1'b0),
809 .d ('0),
810
811 // to internal hardware
812 .qe (),
813 .q (reg2hw.dbus_addr_matching[1].q),
814 .ds (),
815
816 // to register interface (read)
817 .qs (dbus_addr_matching_1_qs)
818 );
819
820
821 // Subregister 0 of Multireg dbus_remap_addr
822 // R[dbus_remap_addr_0]: V(False)
823 // Create REGWEN-gated WE signal
824 logic dbus_remap_addr_0_gated_we;
825 1/1 assign dbus_remap_addr_0_gated_we = dbus_remap_addr_0_we & dbus_regwen_0_qs;
Tests: T214 T301 T74
826 prim_subreg #(
827 .DW (32),
828 .SwAccess(prim_subreg_pkg::SwAccessRW),
829 .RESVAL (32'h0),
830 .Mubi (1'b0)
831 ) u_dbus_remap_addr_0 (
832 .clk_i (clk_i),
833 .rst_ni (rst_ni),
834
835 // from register interface
836 .we (dbus_remap_addr_0_gated_we),
837 .wd (dbus_remap_addr_0_wd),
838
839 // from internal hardware
840 .de (1'b0),
841 .d ('0),
842
843 // to internal hardware
844 .qe (),
845 .q (reg2hw.dbus_remap_addr[0].q),
846 .ds (),
847
848 // to register interface (read)
849 .qs (dbus_remap_addr_0_qs)
850 );
851
852
853 // Subregister 1 of Multireg dbus_remap_addr
854 // R[dbus_remap_addr_1]: V(False)
855 // Create REGWEN-gated WE signal
856 logic dbus_remap_addr_1_gated_we;
857 1/1 assign dbus_remap_addr_1_gated_we = dbus_remap_addr_1_we & dbus_regwen_1_qs;
Tests: T214 T301 T74
858 prim_subreg #(
859 .DW (32),
860 .SwAccess(prim_subreg_pkg::SwAccessRW),
861 .RESVAL (32'h0),
862 .Mubi (1'b0)
863 ) u_dbus_remap_addr_1 (
864 .clk_i (clk_i),
865 .rst_ni (rst_ni),
866
867 // from register interface
868 .we (dbus_remap_addr_1_gated_we),
869 .wd (dbus_remap_addr_1_wd),
870
871 // from internal hardware
872 .de (1'b0),
873 .d ('0),
874
875 // to internal hardware
876 .qe (),
877 .q (reg2hw.dbus_remap_addr[1].q),
878 .ds (),
879
880 // to register interface (read)
881 .qs (dbus_remap_addr_1_qs)
882 );
883
884
885 // R[nmi_enable]: V(False)
886 // F[alert_en]: 0:0
887 prim_subreg #(
888 .DW (1),
889 .SwAccess(prim_subreg_pkg::SwAccessW1S),
890 .RESVAL (1'h0),
891 .Mubi (1'b0)
892 ) u_nmi_enable_alert_en (
893 .clk_i (clk_i),
894 .rst_ni (rst_ni),
895
896 // from register interface
897 .we (nmi_enable_we),
898 .wd (nmi_enable_alert_en_wd),
899
900 // from internal hardware
901 .de (1'b0),
902 .d ('0),
903
904 // to internal hardware
905 .qe (),
906 .q (reg2hw.nmi_enable.alert_en.q),
907 .ds (),
908
909 // to register interface (read)
910 .qs (nmi_enable_alert_en_qs)
911 );
912
913 // F[wdog_en]: 1:1
914 prim_subreg #(
915 .DW (1),
916 .SwAccess(prim_subreg_pkg::SwAccessW1S),
917 .RESVAL (1'h0),
918 .Mubi (1'b0)
919 ) u_nmi_enable_wdog_en (
920 .clk_i (clk_i),
921 .rst_ni (rst_ni),
922
923 // from register interface
924 .we (nmi_enable_we),
925 .wd (nmi_enable_wdog_en_wd),
926
927 // from internal hardware
928 .de (1'b0),
929 .d ('0),
930
931 // to internal hardware
932 .qe (),
933 .q (reg2hw.nmi_enable.wdog_en.q),
934 .ds (),
935
936 // to register interface (read)
937 .qs (nmi_enable_wdog_en_qs)
938 );
939
940
941 // R[nmi_state]: V(False)
942 // F[alert]: 0:0
943 prim_subreg #(
944 .DW (1),
945 .SwAccess(prim_subreg_pkg::SwAccessW1C),
946 .RESVAL (1'h0),
947 .Mubi (1'b0)
948 ) u_nmi_state_alert (
949 .clk_i (clk_i),
950 .rst_ni (rst_ni),
951
952 // from register interface
953 .we (nmi_state_we),
954 .wd (nmi_state_alert_wd),
955
956 // from internal hardware
957 .de (hw2reg.nmi_state.alert.de),
958 .d (hw2reg.nmi_state.alert.d),
959
960 // to internal hardware
961 .qe (),
962 .q (reg2hw.nmi_state.alert.q),
963 .ds (),
964
965 // to register interface (read)
966 .qs (nmi_state_alert_qs)
967 );
968
969 // F[wdog]: 1:1
970 prim_subreg #(
971 .DW (1),
972 .SwAccess(prim_subreg_pkg::SwAccessW1C),
973 .RESVAL (1'h0),
974 .Mubi (1'b0)
975 ) u_nmi_state_wdog (
976 .clk_i (clk_i),
977 .rst_ni (rst_ni),
978
979 // from register interface
980 .we (nmi_state_we),
981 .wd (nmi_state_wdog_wd),
982
983 // from internal hardware
984 .de (hw2reg.nmi_state.wdog.de),
985 .d (hw2reg.nmi_state.wdog.d),
986
987 // to internal hardware
988 .qe (),
989 .q (reg2hw.nmi_state.wdog.q),
990 .ds (),
991
992 // to register interface (read)
993 .qs (nmi_state_wdog_qs)
994 );
995
996
997 // R[err_status]: V(False)
998 // F[reg_intg_err]: 0:0
999 prim_subreg #(
1000 .DW (1),
1001 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1002 .RESVAL (1'h0),
1003 .Mubi (1'b0)
1004 ) u_err_status_reg_intg_err (
1005 .clk_i (clk_i),
1006 .rst_ni (rst_ni),
1007
1008 // from register interface
1009 .we (err_status_we),
1010 .wd (err_status_reg_intg_err_wd),
1011
1012 // from internal hardware
1013 .de (hw2reg.err_status.reg_intg_err.de),
1014 .d (hw2reg.err_status.reg_intg_err.d),
1015
1016 // to internal hardware
1017 .qe (),
1018 .q (),
1019 .ds (),
1020
1021 // to register interface (read)
1022 .qs (err_status_reg_intg_err_qs)
1023 );
1024
1025 // F[fatal_intg_err]: 8:8
1026 prim_subreg #(
1027 .DW (1),
1028 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1029 .RESVAL (1'h0),
1030 .Mubi (1'b0)
1031 ) u_err_status_fatal_intg_err (
1032 .clk_i (clk_i),
1033 .rst_ni (rst_ni),
1034
1035 // from register interface
1036 .we (err_status_we),
1037 .wd (err_status_fatal_intg_err_wd),
1038
1039 // from internal hardware
1040 .de (hw2reg.err_status.fatal_intg_err.de),
1041 .d (hw2reg.err_status.fatal_intg_err.d),
1042
1043 // to internal hardware
1044 .qe (),
1045 .q (),
1046 .ds (),
1047
1048 // to register interface (read)
1049 .qs (err_status_fatal_intg_err_qs)
1050 );
1051
1052 // F[fatal_core_err]: 9:9
1053 prim_subreg #(
1054 .DW (1),
1055 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1056 .RESVAL (1'h0),
1057 .Mubi (1'b0)
1058 ) u_err_status_fatal_core_err (
1059 .clk_i (clk_i),
1060 .rst_ni (rst_ni),
1061
1062 // from register interface
1063 .we (err_status_we),
1064 .wd (err_status_fatal_core_err_wd),
1065
1066 // from internal hardware
1067 .de (hw2reg.err_status.fatal_core_err.de),
1068 .d (hw2reg.err_status.fatal_core_err.d),
1069
1070 // to internal hardware
1071 .qe (),
1072 .q (),
1073 .ds (),
1074
1075 // to register interface (read)
1076 .qs (err_status_fatal_core_err_qs)
1077 );
1078
1079 // F[recov_core_err]: 10:10
1080 prim_subreg #(
1081 .DW (1),
1082 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1083 .RESVAL (1'h0),
1084 .Mubi (1'b0)
1085 ) u_err_status_recov_core_err (
1086 .clk_i (clk_i),
1087 .rst_ni (rst_ni),
1088
1089 // from register interface
1090 .we (err_status_we),
1091 .wd (err_status_recov_core_err_wd),
1092
1093 // from internal hardware
1094 .de (hw2reg.err_status.recov_core_err.de),
1095 .d (hw2reg.err_status.recov_core_err.d),
1096
1097 // to internal hardware
1098 .qe (),
1099 .q (),
1100 .ds (),
1101
1102 // to register interface (read)
1103 .qs (err_status_recov_core_err_qs)
1104 );
1105
1106
1107 // R[rnd_data]: V(True)
1108 prim_subreg_ext #(
1109 .DW (32)
1110 ) u_rnd_data (
1111 .re (rnd_data_re),
1112 .we (1'b0),
1113 .wd ('0),
1114 .d (hw2reg.rnd_data.d),
1115 .qre (reg2hw.rnd_data.re),
1116 .qe (),
1117 .q (reg2hw.rnd_data.q),
1118 .ds (),
1119 .qs (rnd_data_qs)
1120 );
1121
1122
1123 // R[rnd_status]: V(True)
1124 // F[rnd_data_valid]: 0:0
1125 prim_subreg_ext #(
1126 .DW (1)
1127 ) u_rnd_status_rnd_data_valid (
1128 .re (rnd_status_re),
1129 .we (1'b0),
1130 .wd ('0),
1131 .d (hw2reg.rnd_status.rnd_data_valid.d),
1132 .qre (),
1133 .qe (),
1134 .q (),
1135 .ds (),
1136 .qs (rnd_status_rnd_data_valid_qs)
1137 );
1138
1139 // F[rnd_data_fips]: 1:1
1140 prim_subreg_ext #(
1141 .DW (1)
1142 ) u_rnd_status_rnd_data_fips (
1143 .re (rnd_status_re),
1144 .we (1'b0),
1145 .wd ('0),
1146 .d (hw2reg.rnd_status.rnd_data_fips.d),
1147 .qre (),
1148 .qe (),
1149 .q (),
1150 .ds (),
1151 .qs (rnd_status_rnd_data_fips_qs)
1152 );
1153
1154
1155 // R[fpga_info]: V(True)
1156 prim_subreg_ext #(
1157 .DW (32)
1158 ) u_fpga_info (
1159 .re (fpga_info_re),
1160 .we (1'b0),
1161 .wd ('0),
1162 .d (hw2reg.fpga_info.d),
1163 .qre (),
1164 .qe (),
1165 .q (),
1166 .ds (),
1167 .qs (fpga_info_qs)
1168 );
1169
1170
1171
1172 logic [24:0] addr_hit;
1173 always_comb begin
1174 1/1 addr_hit = '0;
Tests: T1 T2 T3
1175 1/1 addr_hit[ 0] = (reg_addr == RV_CORE_IBEX_ALERT_TEST_OFFSET);
Tests: T1 T2 T3
1176 1/1 addr_hit[ 1] = (reg_addr == RV_CORE_IBEX_SW_RECOV_ERR_OFFSET);
Tests: T1 T2 T3
1177 1/1 addr_hit[ 2] = (reg_addr == RV_CORE_IBEX_SW_FATAL_ERR_OFFSET);
Tests: T1 T2 T3
1178 1/1 addr_hit[ 3] = (reg_addr == RV_CORE_IBEX_IBUS_REGWEN_0_OFFSET);
Tests: T1 T2 T3
1179 1/1 addr_hit[ 4] = (reg_addr == RV_CORE_IBEX_IBUS_REGWEN_1_OFFSET);
Tests: T1 T2 T3
1180 1/1 addr_hit[ 5] = (reg_addr == RV_CORE_IBEX_IBUS_ADDR_EN_0_OFFSET);
Tests: T1 T2 T3
1181 1/1 addr_hit[ 6] = (reg_addr == RV_CORE_IBEX_IBUS_ADDR_EN_1_OFFSET);
Tests: T1 T2 T3
1182 1/1 addr_hit[ 7] = (reg_addr == RV_CORE_IBEX_IBUS_ADDR_MATCHING_0_OFFSET);
Tests: T1 T2 T3
1183 1/1 addr_hit[ 8] = (reg_addr == RV_CORE_IBEX_IBUS_ADDR_MATCHING_1_OFFSET);
Tests: T1 T2 T3
1184 1/1 addr_hit[ 9] = (reg_addr == RV_CORE_IBEX_IBUS_REMAP_ADDR_0_OFFSET);
Tests: T1 T2 T3
1185 1/1 addr_hit[10] = (reg_addr == RV_CORE_IBEX_IBUS_REMAP_ADDR_1_OFFSET);
Tests: T1 T2 T3
1186 1/1 addr_hit[11] = (reg_addr == RV_CORE_IBEX_DBUS_REGWEN_0_OFFSET);
Tests: T1 T2 T3
1187 1/1 addr_hit[12] = (reg_addr == RV_CORE_IBEX_DBUS_REGWEN_1_OFFSET);
Tests: T1 T2 T3
1188 1/1 addr_hit[13] = (reg_addr == RV_CORE_IBEX_DBUS_ADDR_EN_0_OFFSET);
Tests: T1 T2 T3
1189 1/1 addr_hit[14] = (reg_addr == RV_CORE_IBEX_DBUS_ADDR_EN_1_OFFSET);
Tests: T1 T2 T3
1190 1/1 addr_hit[15] = (reg_addr == RV_CORE_IBEX_DBUS_ADDR_MATCHING_0_OFFSET);
Tests: T1 T2 T3
1191 1/1 addr_hit[16] = (reg_addr == RV_CORE_IBEX_DBUS_ADDR_MATCHING_1_OFFSET);
Tests: T1 T2 T3
1192 1/1 addr_hit[17] = (reg_addr == RV_CORE_IBEX_DBUS_REMAP_ADDR_0_OFFSET);
Tests: T1 T2 T3
1193 1/1 addr_hit[18] = (reg_addr == RV_CORE_IBEX_DBUS_REMAP_ADDR_1_OFFSET);
Tests: T1 T2 T3
1194 1/1 addr_hit[19] = (reg_addr == RV_CORE_IBEX_NMI_ENABLE_OFFSET);
Tests: T1 T2 T3
1195 1/1 addr_hit[20] = (reg_addr == RV_CORE_IBEX_NMI_STATE_OFFSET);
Tests: T1 T2 T3
1196 1/1 addr_hit[21] = (reg_addr == RV_CORE_IBEX_ERR_STATUS_OFFSET);
Tests: T1 T2 T3
1197 1/1 addr_hit[22] = (reg_addr == RV_CORE_IBEX_RND_DATA_OFFSET);
Tests: T1 T2 T3
1198 1/1 addr_hit[23] = (reg_addr == RV_CORE_IBEX_RND_STATUS_OFFSET);
Tests: T1 T2 T3
1199 1/1 addr_hit[24] = (reg_addr == RV_CORE_IBEX_FPGA_INFO_OFFSET);
Tests: T1 T2 T3
1200 end
1201
1202 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T1 T2 T3
1203
1204 // Check sub-word write is permitted
1205 always_comb begin
1206 1/1 wr_err = (reg_we &
Tests: T1 T2 T3
1207 ((addr_hit[ 0] & (|(RV_CORE_IBEX_CFG_PERMIT[ 0] & ~reg_be))) |
1208 (addr_hit[ 1] & (|(RV_CORE_IBEX_CFG_PERMIT[ 1] & ~reg_be))) |
1209 (addr_hit[ 2] & (|(RV_CORE_IBEX_CFG_PERMIT[ 2] & ~reg_be))) |
1210 (addr_hit[ 3] & (|(RV_CORE_IBEX_CFG_PERMIT[ 3] & ~reg_be))) |
1211 (addr_hit[ 4] & (|(RV_CORE_IBEX_CFG_PERMIT[ 4] & ~reg_be))) |
1212 (addr_hit[ 5] & (|(RV_CORE_IBEX_CFG_PERMIT[ 5] & ~reg_be))) |
1213 (addr_hit[ 6] & (|(RV_CORE_IBEX_CFG_PERMIT[ 6] & ~reg_be))) |
1214 (addr_hit[ 7] & (|(RV_CORE_IBEX_CFG_PERMIT[ 7] & ~reg_be))) |
1215 (addr_hit[ 8] & (|(RV_CORE_IBEX_CFG_PERMIT[ 8] & ~reg_be))) |
1216 (addr_hit[ 9] & (|(RV_CORE_IBEX_CFG_PERMIT[ 9] & ~reg_be))) |
1217 (addr_hit[10] & (|(RV_CORE_IBEX_CFG_PERMIT[10] & ~reg_be))) |
1218 (addr_hit[11] & (|(RV_CORE_IBEX_CFG_PERMIT[11] & ~reg_be))) |
1219 (addr_hit[12] & (|(RV_CORE_IBEX_CFG_PERMIT[12] & ~reg_be))) |
1220 (addr_hit[13] & (|(RV_CORE_IBEX_CFG_PERMIT[13] & ~reg_be))) |
1221 (addr_hit[14] & (|(RV_CORE_IBEX_CFG_PERMIT[14] & ~reg_be))) |
1222 (addr_hit[15] & (|(RV_CORE_IBEX_CFG_PERMIT[15] & ~reg_be))) |
1223 (addr_hit[16] & (|(RV_CORE_IBEX_CFG_PERMIT[16] & ~reg_be))) |
1224 (addr_hit[17] & (|(RV_CORE_IBEX_CFG_PERMIT[17] & ~reg_be))) |
1225 (addr_hit[18] & (|(RV_CORE_IBEX_CFG_PERMIT[18] & ~reg_be))) |
1226 (addr_hit[19] & (|(RV_CORE_IBEX_CFG_PERMIT[19] & ~reg_be))) |
1227 (addr_hit[20] & (|(RV_CORE_IBEX_CFG_PERMIT[20] & ~reg_be))) |
1228 (addr_hit[21] & (|(RV_CORE_IBEX_CFG_PERMIT[21] & ~reg_be))) |
1229 (addr_hit[22] & (|(RV_CORE_IBEX_CFG_PERMIT[22] & ~reg_be))) |
1230 (addr_hit[23] & (|(RV_CORE_IBEX_CFG_PERMIT[23] & ~reg_be))) |
1231 (addr_hit[24] & (|(RV_CORE_IBEX_CFG_PERMIT[24] & ~reg_be)))));
1232 end
1233
1234 // Generate write-enables
1235 1/1 assign alert_test_we = addr_hit[0] & reg_we & !reg_error;
Tests: T1 T2 T3
1236
1237 1/1 assign alert_test_fatal_sw_err_wd = reg_wdata[0];
Tests: T1 T2 T3
1238
1239 1/1 assign alert_test_recov_sw_err_wd = reg_wdata[1];
Tests: T1 T2 T3
1240
1241 1/1 assign alert_test_fatal_hw_err_wd = reg_wdata[2];
Tests: T1 T2 T3
1242
1243 1/1 assign alert_test_recov_hw_err_wd = reg_wdata[3];
Tests: T1 T2 T3
1244 1/1 assign sw_recov_err_we = addr_hit[1] & reg_we & !reg_error;
Tests: T1 T2 T3
1245
1246 1/1 assign sw_recov_err_wd = reg_wdata[3:0];
Tests: T1 T2 T3
1247 1/1 assign sw_fatal_err_we = addr_hit[2] & reg_we & !reg_error;
Tests: T1 T2 T3
1248
1249 1/1 assign sw_fatal_err_wd = reg_wdata[3:0];
Tests: T1 T2 T3
1250 1/1 assign ibus_regwen_0_we = addr_hit[3] & reg_we & !reg_error;
Tests: T1 T2 T3
1251
1252 1/1 assign ibus_regwen_0_wd = reg_wdata[0];
Tests: T1 T2 T3
1253 1/1 assign ibus_regwen_1_we = addr_hit[4] & reg_we & !reg_error;
Tests: T1 T2 T3
1254
1255 1/1 assign ibus_regwen_1_wd = reg_wdata[0];
Tests: T1 T2 T3
1256 1/1 assign ibus_addr_en_0_we = addr_hit[5] & reg_we & !reg_error;
Tests: T1 T2 T3
1257
1258 1/1 assign ibus_addr_en_0_wd = reg_wdata[0];
Tests: T1 T2 T3
1259 1/1 assign ibus_addr_en_1_we = addr_hit[6] & reg_we & !reg_error;
Tests: T1 T2 T3
1260
1261 1/1 assign ibus_addr_en_1_wd = reg_wdata[0];
Tests: T1 T2 T3
1262 1/1 assign ibus_addr_matching_0_we = addr_hit[7] & reg_we & !reg_error;
Tests: T1 T2 T3
1263
1264 1/1 assign ibus_addr_matching_0_wd = reg_wdata[31:0];
Tests: T1 T2 T3
1265 1/1 assign ibus_addr_matching_1_we = addr_hit[8] & reg_we & !reg_error;
Tests: T1 T2 T3
1266
1267 1/1 assign ibus_addr_matching_1_wd = reg_wdata[31:0];
Tests: T1 T2 T3
1268 1/1 assign ibus_remap_addr_0_we = addr_hit[9] & reg_we & !reg_error;
Tests: T1 T2 T3
1269
1270 1/1 assign ibus_remap_addr_0_wd = reg_wdata[31:0];
Tests: T1 T2 T3
1271 1/1 assign ibus_remap_addr_1_we = addr_hit[10] & reg_we & !reg_error;
Tests: T1 T2 T3
1272
1273 1/1 assign ibus_remap_addr_1_wd = reg_wdata[31:0];
Tests: T1 T2 T3
1274 1/1 assign dbus_regwen_0_we = addr_hit[11] & reg_we & !reg_error;
Tests: T1 T2 T3
1275
1276 1/1 assign dbus_regwen_0_wd = reg_wdata[0];
Tests: T1 T2 T3
1277 1/1 assign dbus_regwen_1_we = addr_hit[12] & reg_we & !reg_error;
Tests: T1 T2 T3
1278
1279 1/1 assign dbus_regwen_1_wd = reg_wdata[0];
Tests: T1 T2 T3
1280 1/1 assign dbus_addr_en_0_we = addr_hit[13] & reg_we & !reg_error;
Tests: T1 T2 T3
1281
1282 1/1 assign dbus_addr_en_0_wd = reg_wdata[0];
Tests: T1 T2 T3
1283 1/1 assign dbus_addr_en_1_we = addr_hit[14] & reg_we & !reg_error;
Tests: T1 T2 T3
1284
1285 1/1 assign dbus_addr_en_1_wd = reg_wdata[0];
Tests: T1 T2 T3
1286 1/1 assign dbus_addr_matching_0_we = addr_hit[15] & reg_we & !reg_error;
Tests: T1 T2 T3
1287
1288 1/1 assign dbus_addr_matching_0_wd = reg_wdata[31:0];
Tests: T1 T2 T3
1289 1/1 assign dbus_addr_matching_1_we = addr_hit[16] & reg_we & !reg_error;
Tests: T1 T2 T3
1290
1291 1/1 assign dbus_addr_matching_1_wd = reg_wdata[31:0];
Tests: T1 T2 T3
1292 1/1 assign dbus_remap_addr_0_we = addr_hit[17] & reg_we & !reg_error;
Tests: T1 T2 T3
1293
1294 1/1 assign dbus_remap_addr_0_wd = reg_wdata[31:0];
Tests: T1 T2 T3
1295 1/1 assign dbus_remap_addr_1_we = addr_hit[18] & reg_we & !reg_error;
Tests: T1 T2 T3
1296
1297 1/1 assign dbus_remap_addr_1_wd = reg_wdata[31:0];
Tests: T1 T2 T3
1298 1/1 assign nmi_enable_we = addr_hit[19] & reg_we & !reg_error;
Tests: T1 T2 T3
1299
1300 1/1 assign nmi_enable_alert_en_wd = reg_wdata[0];
Tests: T1 T2 T3
1301
1302 1/1 assign nmi_enable_wdog_en_wd = reg_wdata[1];
Tests: T1 T2 T3
1303 1/1 assign nmi_state_we = addr_hit[20] & reg_we & !reg_error;
Tests: T1 T2 T3
1304
1305 1/1 assign nmi_state_alert_wd = reg_wdata[0];
Tests: T1 T2 T3
1306
1307 1/1 assign nmi_state_wdog_wd = reg_wdata[1];
Tests: T1 T2 T3
1308 1/1 assign err_status_we = addr_hit[21] & reg_we & !reg_error;
Tests: T1 T2 T3
1309
1310 1/1 assign err_status_reg_intg_err_wd = reg_wdata[0];
Tests: T1 T2 T3
1311
1312 1/1 assign err_status_fatal_intg_err_wd = reg_wdata[8];
Tests: T1 T2 T3
1313
1314 1/1 assign err_status_fatal_core_err_wd = reg_wdata[9];
Tests: T1 T2 T3
1315
1316 1/1 assign err_status_recov_core_err_wd = reg_wdata[10];
Tests: T1 T2 T3
1317 1/1 assign rnd_data_re = addr_hit[22] & reg_re & !reg_error;
Tests: T1 T2 T3
1318 1/1 assign rnd_status_re = addr_hit[23] & reg_re & !reg_error;
Tests: T1 T2 T3
1319 1/1 assign fpga_info_re = addr_hit[24] & reg_re & !reg_error;
Tests: T1 T2 T3
1320
1321 // Assign write-enables to checker logic vector.
1322 always_comb begin
1323 1/1 reg_we_check = '0;
Tests: T46 T47 T87
1324 1/1 reg_we_check[0] = alert_test_we;
Tests: T46 T47 T87
1325 1/1 reg_we_check[1] = sw_recov_err_we;
Tests: T46 T47 T87
1326 1/1 reg_we_check[2] = sw_fatal_err_we;
Tests: T46 T47 T87
1327 1/1 reg_we_check[3] = ibus_regwen_0_we;
Tests: T46 T47 T87
1328 1/1 reg_we_check[4] = ibus_regwen_1_we;
Tests: T46 T47 T87
1329 1/1 reg_we_check[5] = ibus_addr_en_0_gated_we;
Tests: T46 T47 T87
1330 1/1 reg_we_check[6] = ibus_addr_en_1_gated_we;
Tests: T46 T47 T87
1331 1/1 reg_we_check[7] = ibus_addr_matching_0_gated_we;
Tests: T46 T47 T87
1332 1/1 reg_we_check[8] = ibus_addr_matching_1_gated_we;
Tests: T46 T47 T87
1333 1/1 reg_we_check[9] = ibus_remap_addr_0_gated_we;
Tests: T46 T47 T87
1334 1/1 reg_we_check[10] = ibus_remap_addr_1_gated_we;
Tests: T46 T47 T87
1335 1/1 reg_we_check[11] = dbus_regwen_0_we;
Tests: T46 T47 T87
1336 1/1 reg_we_check[12] = dbus_regwen_1_we;
Tests: T46 T47 T87
1337 1/1 reg_we_check[13] = dbus_addr_en_0_gated_we;
Tests: T46 T47 T87
1338 1/1 reg_we_check[14] = dbus_addr_en_1_gated_we;
Tests: T46 T47 T87
1339 1/1 reg_we_check[15] = dbus_addr_matching_0_gated_we;
Tests: T46 T47 T87
1340 1/1 reg_we_check[16] = dbus_addr_matching_1_gated_we;
Tests: T46 T47 T87
1341 1/1 reg_we_check[17] = dbus_remap_addr_0_gated_we;
Tests: T46 T47 T87
1342 1/1 reg_we_check[18] = dbus_remap_addr_1_gated_we;
Tests: T46 T47 T87
1343 1/1 reg_we_check[19] = nmi_enable_we;
Tests: T46 T47 T87
1344 1/1 reg_we_check[20] = nmi_state_we;
Tests: T46 T47 T87
1345 1/1 reg_we_check[21] = err_status_we;
Tests: T46 T47 T87
1346 1/1 reg_we_check[22] = 1'b0;
Tests: T46 T47 T87
1347 1/1 reg_we_check[23] = 1'b0;
Tests: T46 T47 T87
1348 1/1 reg_we_check[24] = 1'b0;
Tests: T46 T47 T87
1349 end
1350
1351 // Read data return
1352 always_comb begin
1353 1/1 reg_rdata_next = '0;
Tests: T1 T2 T3
1354 1/1 unique case (1'b1)
Tests: T1 T2 T3
1355 addr_hit[0]: begin
1356 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
1357 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T3
1358 1/1 reg_rdata_next[2] = '0;
Tests: T1 T2 T3
1359 1/1 reg_rdata_next[3] = '0;
Tests: T1 T2 T3
1360 end
1361
1362 addr_hit[1]: begin
1363 1/1 reg_rdata_next[3:0] = sw_recov_err_qs;
Tests: T74 T97 T103
1364 end
1365
1366 addr_hit[2]: begin
1367 1/1 reg_rdata_next[3:0] = sw_fatal_err_qs;
Tests: T303 T304 T104
1368 end
1369
1370 addr_hit[3]: begin
1371 1/1 reg_rdata_next[0] = ibus_regwen_0_qs;
Tests: T214 T301 T74
1372 end
1373
1374 addr_hit[4]: begin
1375 1/1 reg_rdata_next[0] = ibus_regwen_1_qs;
Tests: T214 T301 T74
1376 end
1377
1378 addr_hit[5]: begin
1379 1/1 reg_rdata_next[0] = ibus_addr_en_0_qs;
Tests: T214 T301 T74
1380 end
1381
1382 addr_hit[6]: begin
1383 1/1 reg_rdata_next[0] = ibus_addr_en_1_qs;
Tests: T214 T301 T74
1384 end
1385
1386 addr_hit[7]: begin
1387 1/1 reg_rdata_next[31:0] = ibus_addr_matching_0_qs;
Tests: T214 T301 T74
1388 end
1389
1390 addr_hit[8]: begin
1391 1/1 reg_rdata_next[31:0] = ibus_addr_matching_1_qs;
Tests: T214 T301 T74
1392 end
1393
1394 addr_hit[9]: begin
1395 1/1 reg_rdata_next[31:0] = ibus_remap_addr_0_qs;
Tests: T214 T301 T74
1396 end
1397
1398 addr_hit[10]: begin
1399 1/1 reg_rdata_next[31:0] = ibus_remap_addr_1_qs;
Tests: T214 T301 T74
1400 end
1401
1402 addr_hit[11]: begin
1403 1/1 reg_rdata_next[0] = dbus_regwen_0_qs;
Tests: T214 T301 T74
1404 end
1405
1406 addr_hit[12]: begin
1407 1/1 reg_rdata_next[0] = dbus_regwen_1_qs;
Tests: T214 T301 T74
1408 end
1409
1410 addr_hit[13]: begin
1411 1/1 reg_rdata_next[0] = dbus_addr_en_0_qs;
Tests: T214 T301 T74
1412 end
1413
1414 addr_hit[14]: begin
1415 1/1 reg_rdata_next[0] = dbus_addr_en_1_qs;
Tests: T214 T301 T74
1416 end
1417
1418 addr_hit[15]: begin
1419 1/1 reg_rdata_next[31:0] = dbus_addr_matching_0_qs;
Tests: T214 T301 T74
1420 end
1421
1422 addr_hit[16]: begin
1423 1/1 reg_rdata_next[31:0] = dbus_addr_matching_1_qs;
Tests: T214 T301 T74
1424 end
1425
1426 addr_hit[17]: begin
1427 1/1 reg_rdata_next[31:0] = dbus_remap_addr_0_qs;
Tests: T214 T301 T74
1428 end
1429
1430 addr_hit[18]: begin
1431 1/1 reg_rdata_next[31:0] = dbus_remap_addr_1_qs;
Tests: T214 T301 T74
1432 end
1433
1434 addr_hit[19]: begin
1435 1/1 reg_rdata_next[0] = nmi_enable_alert_en_qs;
Tests: T46 T47 T87
1436 1/1 reg_rdata_next[1] = nmi_enable_wdog_en_qs;
Tests: T46 T47 T87
1437 end
1438
1439 addr_hit[20]: begin
1440 1/1 reg_rdata_next[0] = nmi_state_alert_qs;
Tests: T46 T47 T87
1441 1/1 reg_rdata_next[1] = nmi_state_wdog_qs;
Tests: T46 T47 T87
1442 end
1443
1444 addr_hit[21]: begin
1445 1/1 reg_rdata_next[0] = err_status_reg_intg_err_qs;
Tests: T47 T265 T74
1446 1/1 reg_rdata_next[8] = err_status_fatal_intg_err_qs;
Tests: T47 T265 T74
1447 1/1 reg_rdata_next[9] = err_status_fatal_core_err_qs;
Tests: T47 T265 T74
1448 1/1 reg_rdata_next[10] = err_status_recov_core_err_qs;
Tests: T47 T265 T74
1449 end
1450
1451 addr_hit[22]: begin
1452 1/1 reg_rdata_next[31:0] = rnd_data_qs;
Tests: T1 T7 T28
1453 end
1454
1455 addr_hit[23]: begin
1456 1/1 reg_rdata_next[0] = rnd_status_rnd_data_valid_qs;
Tests: T1 T7 T28
1457 1/1 reg_rdata_next[1] = rnd_status_rnd_data_fips_qs;
Tests: T1 T7 T28
1458 end
1459
1460 addr_hit[24]: begin
1461 1/1 reg_rdata_next[31:0] = fpga_info_qs;
Tests: T1 T2 T4
1462 end
1463
1464 default: begin
1465 reg_rdata_next = '1;
1466 end
1467 endcase
1468 end
1469
1470 // shadow busy
1471 logic shadow_busy;
1472 assign shadow_busy = 1'b0;
1473
1474 // register busy
1475 unreachable assign reg_busy = shadow_busy;
1476
1477 // Unused signal tieoff
1478
1479 // wdata / byte enable are not always fully used
1480 // add a blanket unused statement to handle lint waivers
1481 logic unused_wdata;
1482 logic unused_be;
1483 1/1 assign unused_wdata = ^reg_wdata;
Tests: T1 T2 T3
1484 1/1 assign unused_be = ^reg_be;
Tests: T1 T2 T3
Cond Coverage for Module :
rv_core_ibex_cfg_reg_top
| Total | Covered | Percent |
|---|
| Conditions | 311 | 310 | 99.68 |
| Logical | 311 | 310 | 99.68 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Branch Coverage for Module :
rv_core_ibex_cfg_reg_top
| Line No. | Total | Covered | Percent |
| Branches |
|
35 |
35 |
100.00 |
| TERNARY |
1202 |
2 |
2 |
100.00 |
| IF |
73 |
3 |
3 |
100.00 |
| TERNARY |
130 |
2 |
2 |
100.00 |
| IF |
136 |
2 |
2 |
100.00 |
| CASE |
1354 |
26 |
26 |
100.00 |
1202 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T4 |
| 0 |
Covered |
T1,T2,T3 |
73 if (!rst_ni) begin
-1-
74 err_q <= '0;
==>
75 end else if (intg_err || reg_we_err) begin
-2-
76 err_q <= 1'b1;
==>
77 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T306,T307,T308 |
| 0 |
0 |
Covered |
T1,T2,T3 |
130 reg_steer =
131 tl_i.a_address[AW-1:0] inside {[128:159]} ? 1'd0 :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
136 if (intg_err) begin
-1-
137 reg_steer = 1'd1;
==>
138 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T184,T309,T479 |
| 0 |
Covered |
T1,T2,T3 |
1354 unique case (1'b1)
-1-
1355 addr_hit[0]: begin
1356 reg_rdata_next[0] = '0;
==>
1357 reg_rdata_next[1] = '0;
1358 reg_rdata_next[2] = '0;
1359 reg_rdata_next[3] = '0;
1360 end
1361
1362 addr_hit[1]: begin
1363 reg_rdata_next[3:0] = sw_recov_err_qs;
==>
1364 end
1365
1366 addr_hit[2]: begin
1367 reg_rdata_next[3:0] = sw_fatal_err_qs;
==>
1368 end
1369
1370 addr_hit[3]: begin
1371 reg_rdata_next[0] = ibus_regwen_0_qs;
==>
1372 end
1373
1374 addr_hit[4]: begin
1375 reg_rdata_next[0] = ibus_regwen_1_qs;
==>
1376 end
1377
1378 addr_hit[5]: begin
1379 reg_rdata_next[0] = ibus_addr_en_0_qs;
==>
1380 end
1381
1382 addr_hit[6]: begin
1383 reg_rdata_next[0] = ibus_addr_en_1_qs;
==>
1384 end
1385
1386 addr_hit[7]: begin
1387 reg_rdata_next[31:0] = ibus_addr_matching_0_qs;
==>
1388 end
1389
1390 addr_hit[8]: begin
1391 reg_rdata_next[31:0] = ibus_addr_matching_1_qs;
==>
1392 end
1393
1394 addr_hit[9]: begin
1395 reg_rdata_next[31:0] = ibus_remap_addr_0_qs;
==>
1396 end
1397
1398 addr_hit[10]: begin
1399 reg_rdata_next[31:0] = ibus_remap_addr_1_qs;
==>
1400 end
1401
1402 addr_hit[11]: begin
1403 reg_rdata_next[0] = dbus_regwen_0_qs;
==>
1404 end
1405
1406 addr_hit[12]: begin
1407 reg_rdata_next[0] = dbus_regwen_1_qs;
==>
1408 end
1409
1410 addr_hit[13]: begin
1411 reg_rdata_next[0] = dbus_addr_en_0_qs;
==>
1412 end
1413
1414 addr_hit[14]: begin
1415 reg_rdata_next[0] = dbus_addr_en_1_qs;
==>
1416 end
1417
1418 addr_hit[15]: begin
1419 reg_rdata_next[31:0] = dbus_addr_matching_0_qs;
==>
1420 end
1421
1422 addr_hit[16]: begin
1423 reg_rdata_next[31:0] = dbus_addr_matching_1_qs;
==>
1424 end
1425
1426 addr_hit[17]: begin
1427 reg_rdata_next[31:0] = dbus_remap_addr_0_qs;
==>
1428 end
1429
1430 addr_hit[18]: begin
1431 reg_rdata_next[31:0] = dbus_remap_addr_1_qs;
==>
1432 end
1433
1434 addr_hit[19]: begin
1435 reg_rdata_next[0] = nmi_enable_alert_en_qs;
==>
1436 reg_rdata_next[1] = nmi_enable_wdog_en_qs;
1437 end
1438
1439 addr_hit[20]: begin
1440 reg_rdata_next[0] = nmi_state_alert_qs;
==>
1441 reg_rdata_next[1] = nmi_state_wdog_qs;
1442 end
1443
1444 addr_hit[21]: begin
1445 reg_rdata_next[0] = err_status_reg_intg_err_qs;
==>
1446 reg_rdata_next[8] = err_status_fatal_intg_err_qs;
1447 reg_rdata_next[9] = err_status_fatal_core_err_qs;
1448 reg_rdata_next[10] = err_status_recov_core_err_qs;
1449 end
1450
1451 addr_hit[22]: begin
1452 reg_rdata_next[31:0] = rnd_data_qs;
==>
1453 end
1454
1455 addr_hit[23]: begin
1456 reg_rdata_next[0] = rnd_status_rnd_data_valid_qs;
==>
1457 reg_rdata_next[1] = rnd_status_rnd_data_fips_qs;
1458 end
1459
1460 addr_hit[24]: begin
1461 reg_rdata_next[31:0] = fpga_info_qs;
==>
1462 end
1463
1464 default: begin
1465 reg_rdata_next = '1;
==>
Branches:
| -1- | Status | Tests |
| addr_hit[0] |
Covered |
T1,T2,T3 |
| addr_hit[1] |
Covered |
T74,T97,T103 |
| addr_hit[2] |
Covered |
T303,T304,T104 |
| addr_hit[3] |
Covered |
T214,T301,T74 |
| addr_hit[4] |
Covered |
T214,T301,T74 |
| addr_hit[5] |
Covered |
T214,T301,T74 |
| addr_hit[6] |
Covered |
T214,T301,T74 |
| addr_hit[7] |
Covered |
T214,T301,T74 |
| addr_hit[8] |
Covered |
T214,T301,T74 |
| addr_hit[9] |
Covered |
T214,T301,T74 |
| addr_hit[10] |
Covered |
T214,T301,T74 |
| addr_hit[11] |
Covered |
T214,T301,T74 |
| addr_hit[12] |
Covered |
T214,T301,T74 |
| addr_hit[13] |
Covered |
T214,T301,T74 |
| addr_hit[14] |
Covered |
T214,T301,T74 |
| addr_hit[15] |
Covered |
T214,T301,T74 |
| addr_hit[16] |
Covered |
T214,T301,T74 |
| addr_hit[17] |
Covered |
T214,T301,T74 |
| addr_hit[18] |
Covered |
T214,T301,T74 |
| addr_hit[19] |
Covered |
T46,T47,T87 |
| addr_hit[20] |
Covered |
T46,T47,T87 |
| addr_hit[21] |
Covered |
T47,T265,T74 |
| addr_hit[22] |
Covered |
T1,T7,T28 |
| addr_hit[23] |
Covered |
T1,T7,T28 |
| addr_hit[24] |
Covered |
T1,T2,T4 |
| default |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
rv_core_ibex_cfg_reg_top
Assertion Details
en2addrHit
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
575290469 |
44372 |
0 |
0 |
| T1 |
111924 |
3 |
0 |
0 |
| T2 |
78951 |
1 |
0 |
0 |
| T3 |
42255 |
0 |
0 |
0 |
| T4 |
103207 |
1 |
0 |
0 |
| T5 |
100889 |
3 |
0 |
0 |
| T6 |
100982 |
3 |
0 |
0 |
| T7 |
100472 |
3 |
0 |
0 |
| T28 |
97609 |
3 |
0 |
0 |
| T46 |
0 |
56 |
0 |
0 |
| T109 |
67839 |
1 |
0 |
0 |
| T110 |
68617 |
1 |
0 |
0 |
reAfterRv
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
575290469 |
44372 |
0 |
0 |
| T1 |
111924 |
3 |
0 |
0 |
| T2 |
78951 |
1 |
0 |
0 |
| T3 |
42255 |
0 |
0 |
0 |
| T4 |
103207 |
1 |
0 |
0 |
| T5 |
100889 |
3 |
0 |
0 |
| T6 |
100982 |
3 |
0 |
0 |
| T7 |
100472 |
3 |
0 |
0 |
| T28 |
97609 |
3 |
0 |
0 |
| T46 |
0 |
56 |
0 |
0 |
| T109 |
67839 |
1 |
0 |
0 |
| T110 |
68617 |
1 |
0 |
0 |
rePulse
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
575290469 |
37721 |
0 |
0 |
| T1 |
111924 |
3 |
0 |
0 |
| T2 |
78951 |
1 |
0 |
0 |
| T3 |
42255 |
0 |
0 |
0 |
| T4 |
103207 |
1 |
0 |
0 |
| T5 |
100889 |
3 |
0 |
0 |
| T6 |
100982 |
3 |
0 |
0 |
| T7 |
100472 |
3 |
0 |
0 |
| T28 |
97609 |
3 |
0 |
0 |
| T46 |
0 |
54 |
0 |
0 |
| T109 |
67839 |
1 |
0 |
0 |
| T110 |
68617 |
1 |
0 |
0 |
wePulse
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
575290469 |
6651 |
0 |
0 |
| T8 |
175735 |
0 |
0 |
0 |
| T9 |
199984 |
0 |
0 |
0 |
| T13 |
125246 |
0 |
0 |
0 |
| T25 |
101990 |
0 |
0 |
0 |
| T29 |
114638 |
0 |
0 |
0 |
| T32 |
221286 |
0 |
0 |
0 |
| T35 |
79467 |
0 |
0 |
0 |
| T41 |
169596 |
0 |
0 |
0 |
| T46 |
221888 |
2 |
0 |
0 |
| T47 |
0 |
2 |
0 |
0 |
| T73 |
218809 |
0 |
0 |
0 |
| T80 |
0 |
4 |
0 |
0 |
| T87 |
0 |
2 |
0 |
0 |
| T191 |
0 |
2 |
0 |
0 |
| T192 |
0 |
1 |
0 |
0 |
| T203 |
0 |
2 |
0 |
0 |
| T231 |
0 |
2 |
0 |
0 |
| T471 |
0 |
8 |
0 |
0 |
| T669 |
0 |
1 |
0 |
0 |
