Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.91	92.47		89.25			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T105,T184,T309	Yes	T97,T98,T99	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T98,T105,T184	Yes	T98,T104,T105	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T46,T242,T213	Yes	T46,T242,T213	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T46,T47,T242	Yes	T46,T47,T242	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T40,T96,T69	Yes	T40,T96,T69	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T40,T96,T69	Yes	T40,T96,T69	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T46,T47,T87	Yes	T46,T47,T87	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T46,T41,T47	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T38,T100,T93	Yes	T38,T100,T93	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T46,T41,T47	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T46,T41,T47	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T38,T100,T93	Yes	T38,T100,T93	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T46,T41,T47	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T38,T100,T93	Yes	T38,T100,T93	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T38,T100,T93	Yes	T38,T100,T93	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T38,T93,T40	Yes	T38,T93,T40	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T38,T100,T93	Yes	T38,T100,T93	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T38,*T100,*T93	Yes	T38,T100,T93	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T38,T100,T93	Yes	T38,T100,T93	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T74,T97,T98	Yes	T74,T97,T98	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T74,T97,T98	Yes	T74,T97,T98	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T74,T97,T98	Yes	T74,T97,T98	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T74,T97,T102	Yes	T74,T97,T102	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T74,T97,T102	Yes	T74,T97,T102	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T74,T97,T102	Yes	T74,T97,T102	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T97,T102,T105	Yes	T97,T102,T105	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T97,T102,T105	Yes	T97,T102,T105	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T74,T97,T98	Yes	T74,T97,T98	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T74,T105,T184	Yes	T74,T97,T98	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T102,T105,T103	Yes	T97,T102,T105	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T74,T97,T102	Yes	T74,T97,T102	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T74,T97,T102	Yes	T74,T97,T102	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T74,T97,T102	Yes	T74,T97,T105	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T97,T102,T105	Yes	T97,T102,T104	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T74,T97,T105	Yes	T74,T97,T102	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T97,T102,T105	Yes	T97,T102,T105	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T74,*T97,*T102	Yes	T74,T97,T102	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T74,T97,T98	Yes	T74,T97,T98	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T100,T58,T310	Yes	T100,T58,T310	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T414,T100,T58	Yes	T414,T100,T58	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T100,T58,T310	Yes	T100,T58,T310	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T100,T58,T310	Yes	T100,T58,T310	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T414,T100,T58	Yes	T414,T100,T58	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T100,*T58,*T310	Yes	T100,T58,T310	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T414,T100,T58	Yes	T414,T100,T58	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T46,T41,T47	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T100,T58,T310	Yes	T414,T100,T58	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T100,T58,T310	Yes	T100,T58,T310	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T46,T41,T47	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T100,*T58,*T310	Yes	T100,T58,T310	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T46,T41,T47	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T414,T100,T58	Yes	T414,T100,T58	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T3,T206,T36	Yes	T3,T206,T36	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T206,T40,T429	Yes	T206,T40,T429	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T97,*T98,*T99	Yes	T97,T98,T99	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T80,T81,T74	Yes	T80,T81,T74	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T80,T430,T320	Yes	T80,T430,T320	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T80,T430,T320	Yes	T80,T430,T320	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T80,T81,T74	Yes	T80,T81,T74	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T80,T430,T320	Yes	T80,T430,T320	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T74,T97,T102	Yes	T74,T97,T102	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T98,T102,T104	Yes	T98,T102,T104	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T80,T430,T320	Yes	T80,T430,T320	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T80,T430,T320	Yes	T80,T430,T320	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T97,T102,T104	Yes	T97,T102,T105	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T430,T320,T431	Yes	T430,T320,T431	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T74,T97,T98	Yes	T80,T81,T74	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T430,T320,T431	Yes	T80,T430,T320	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T74,T97,*T104	Yes	T74,T97,T102	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T320,*T432,*T74	Yes	T430,T320,T431	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T80,T430,T320	Yes	T80,T430,T320	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T47,T87,T677	Yes	T47,T87,T677	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T10,T11,T410	Yes	T10,T11,T410	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T10,T11,T410	Yes	T10,T11,T410	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T10,T11,T410	Yes	T10,T11,T410	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T10,T11,T410	Yes	T10,T11,T410	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T10,T11,T410	Yes	T10,T11,T410	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T10,T11,T410	Yes	T10,T11,T410	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T97,*T98,*T102	Yes	T97,T98,T102	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T10,T232,T234	Yes	T10,T232,T234	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T10,T11,T410	Yes	T10,T11,T410	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T10,T11,T410	Yes	T10,T11,T410	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T10,T11,T410	Yes	T10,T11,T410	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T10,T11,T410	Yes	T10,T11,T410	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T10,T11,T410	Yes	T10,T11,T410	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T104,*T105,*T103	Yes	T97,T98,T102	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T102	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T10,*T11,*T410	Yes	T10,T11,T410	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T10,T11,T410	Yes	T10,T11,T410	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T28,T410,T80	Yes	T28,T410,T80	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T28,T410,T80	Yes	T28,T410,T80	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T28,T410,T80	Yes	T28,T410,T80	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T28,T410,T80	Yes	T28,T410,T80	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T28,T410,T80	Yes	T28,T410,T80	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T28,T410,T80	Yes	T28,T410,T80	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T97,*T98,*T102	Yes	T97,T98,T102	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T97,T98,T104	Yes	T97,T98,T104	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T97,T98,T105	Yes	T97,T98,T105	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T28,T410,T80	Yes	T28,T410,T80	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T28,T410,T80	Yes	T28,T410,T80	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T97,T98,T99	Yes	T97,T98,T104	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T28,T410,T169	Yes	T28,T410,T169	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T28,T410,T169	Yes	T28,T410,T80	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T28,T410,T169	Yes	T28,T410,T169	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T97,T98,T104	Yes	T97,T99,T102	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T104,*T105,*T103	Yes	T97,T98,T102	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T104,T105	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T28,*T410,*T169	Yes	T28,T410,T169	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T28,T410,T80	Yes	T28,T410,T80	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T4,T35,T8	Yes	T4,T35,T8	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T4,T8,T9	Yes	T4,T8,T9	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T35,T8	Yes	T4,T35,T8	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T4,T35,T8	Yes	T4,T35,T8	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T4,T8,T9	Yes	T4,T8,T9	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T4,T35,T8	Yes	T4,T35,T8	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T4,T35,T8	Yes	T4,T35,T8	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T4,T35,T8	Yes	T4,T35,T8	INPUT
tl_usbdev_i.d_error	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T4,T8,T9	Yes	T4,T35,T8	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T35,T8	Yes	T4,T8,T9	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T4,T35,T8	Yes	T4,T8,T9	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T96,*T98,*T105	Yes	T96,T97,T98	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T4,*T8,*T9	Yes	T4,T8,T9	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T4,T35,T8	Yes	T4,T35,T8	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T96,*T98,*T102	Yes	T96,T98,T102	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T7,T46,T41	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T7,T46	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T98,T102,T104	Yes	T98,T99,T102	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T96,*T98,*T99	Yes	T96,T98,T102	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T98,T99,T102	Yes	T98,T102,T104	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T96,T97,T102	Yes	T96,T97,T102	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T97,T98,T104	Yes	T97,T98,T104	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T97,T102,T104	Yes	T97,T102,T104	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T96,T105,T184	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T105,T103,T184	Yes	T98,T104,T105	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T97,T98,T104	Yes	T97,T98,T105	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T96,T105,T103	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T97,T99,T104	Yes	T97,T98,T104	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T104	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T96,T97,T98	Yes	T96,T97,T98	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T2,T109	Yes	T1,T2,T109	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T7,T46,T41	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T97,*T98,*T99	Yes	T97,T98,T99	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_hmac_o.d_ready	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T80,T249,T671	Yes	T80,T249,T671	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T80,T249,T671	Yes	T80,T249,T671	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T80,T249,T671	Yes	T80,T249,T671	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T80,T249,T671	Yes	T80,T249,T671	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T80,T249,T671	Yes	T80,T249,T671	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T249,T671,T672	Yes	T249,T671,T672	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T80,T249,T671	Yes	T80,T249,T671	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T80,T249,T671	Yes	T80,T249,T671	INPUT
tl_hmac_i.d_error	Yes	Yes	T97,T98,T99	Yes	T97,T98,T104	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T249,T671,T672	Yes	T249,T671,T672	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T249,T671,T672	Yes	T249,T671,T672	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T80,T249,T671	Yes	T249,T671,T672	INPUT
tl_hmac_i.d_sink	Yes	Yes	T97,T98,T104	Yes	T97,T98,T102	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T102	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T80,*T249,*T671	Yes	T249,T671,T672	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T80,T249,T671	Yes	T80,T249,T671	INPUT
tl_kmac_o.d_ready	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T466,T80,T467	Yes	T466,T80,T467	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T41,T466,T274	Yes	T41,T466,T274	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T41,T466,T274	Yes	T41,T466,T274	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T466,T80,T467	Yes	T466,T80,T467	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T41,T466,T274	Yes	T41,T466,T274	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T96,*T69,*T98	Yes	T96,T69,T98	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T466,T467,T468	Yes	T466,T467,T468	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T41,T466,T274	Yes	T41,T466,T274	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T41,T466,T274	Yes	T41,T466,T274	INPUT
tl_kmac_i.d_error	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T41,T466,T274	Yes	T41,T466,T274	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T41,T466,T274	Yes	T41,T466,T274	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T41,T466,T274	Yes	T41,T466,T200	INPUT
tl_kmac_i.d_sink	Yes	Yes	T98,T102,T105	Yes	T98,T104,T105	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T96,*T69,*T98	Yes	T96,T69,T98	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T41,*T466,*T274	Yes	T41,T466,T200	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T41,T466,T274	Yes	T41,T466,T274	INPUT
tl_aes_o.d_ready	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T136,T317,T425	Yes	T136,T317,T425	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T136,T317,T425	Yes	T136,T317,T425	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T136,T317,T425	Yes	T136,T317,T425	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T136,T317,T425	Yes	T136,T317,T425	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T136,T317,T425	Yes	T136,T317,T425	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T97,*T98,*T102	Yes	T97,T98,T102	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T97,T102,T104	Yes	T97,T102,T104	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T136,T317,T425	Yes	T136,T317,T425	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T136,T317,T425	Yes	T136,T317,T425	INPUT
tl_aes_i.d_error	Yes	Yes	T97,T98,T102	Yes	T97,T102,T104	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T136,T317,T425	Yes	T136,T317,T425	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T136,T317,T425	Yes	T136,T317,T425	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T136,T317,T425	Yes	T136,T317,T425	INPUT
tl_aes_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T98,*T104,*T105	Yes	T97,T98,T102	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T136,*T317,*T425	Yes	T136,T317,T425	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T136,T317,T425	Yes	T136,T317,T425	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T98,T102,T104	Yes	T98,T102,T104	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T102,T104,T105	Yes	T97,T102,T104	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T144,T145,T141	Yes	T144,T145,T141	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T96,*T102,*T105	Yes	T96,T97,T98	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T102,T104	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T144,*T145,*T141	Yes	T144,T145,T141	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T80,T388,T144	Yes	T80,T388,T144	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T97,T98,T104	Yes	T97,T98,T104	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T388,T144,T391	Yes	T388,T144,T391	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T388,*T144,*T391	Yes	T388,T144,T391	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T80,T388,T144	Yes	T80,T388,T144	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T80,T388,T144	Yes	T80,T388,T144	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T104,T105,T103	Yes	T104,T105,T103	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T97,T104,T105	Yes	T104,T105,T103	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T388,T144,T141	Yes	T388,T144,T141	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T98,T104,T105	Yes	T98,T104,T105	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T96,*T105,*T103	Yes	T96,T97,T98	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T98,T104,T103	Yes	T97,T98,T104	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T388,*T144,*T141	Yes	T388,T144,T141	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T80,T144,T141	Yes	T80,T144,T141	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T80,T144,T141	Yes	T80,T144,T141	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T80,T144,T141	Yes	T80,T144,T141	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T80,T144,T141	Yes	T80,T144,T141	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T80,T144,T141	Yes	T80,T144,T141	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T80,T144,T141	Yes	T80,T144,T141	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T80,T144,T141	Yes	T80,T144,T141	INPUT
tl_edn1_i.d_error	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T144,T141,T251	Yes	T144,T141,T251	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T141,T251,T142	Yes	T80,T144,T141	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T141,T251,T142	Yes	T80,T144,T141	INPUT
tl_edn1_i.d_sink	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T144,*T141,*T251	Yes	T144,T141,T251	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T80,T144,T141	Yes	T80,T144,T141	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T7,T5	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T97,*T98,*T102	Yes	T97,T98,T102	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T97,T102,T104	Yes	T97,T102,T104	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T97,T102,T105	Yes	T97,T98,T102	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T105,*T103,*T184	Yes	T97,T98,T102	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T97,T102,T105	Yes	T97,T102,T104	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T1,*T5,*T6	Yes	T1,T5,T6	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T1,T5,T6	Yes	T1,T5,T6	INPUT
tl_otbn_o.d_ready	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T217,T80,T141	Yes	T217,T80,T141	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T217,T80,T141	Yes	T217,T80,T141	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T217,T80,T141	Yes	T217,T80,T141	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T217,T80,T141	Yes	T217,T80,T141	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T217,T80,T141	Yes	T217,T80,T141	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T40,*T101,*T69	Yes	T40,T101,T69	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T97,T102,T104	Yes	T97,T102,T104	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T217,T80,T141	Yes	T217,T80,T141	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T217,T80,T141	Yes	T217,T80,T141	INPUT
tl_otbn_i.d_error	Yes	Yes	T98,T105,T103	Yes	T97,T98,T105	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T217,T141,T251	Yes	T217,T141,T251	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T217,T141,T251	Yes	T217,T141,T251	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T217,T80,T141	Yes	T217,T141,T251	INPUT
tl_otbn_i.d_sink	Yes	Yes	T98,T102,T105	Yes	T98,T102,T105	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T40,*T101,*T69	Yes	T40,T101,T69	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T217,*T80,*T141	Yes	T217,T141,T251	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T217,T80,T141	Yes	T217,T80,T141	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T41,T80,T200	Yes	T41,T80,T200	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T41,T274,T80	Yes	T41,T274,T80	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T41,T274,T80	Yes	T41,T274,T80	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T41,T80,T200	Yes	T41,T80,T200	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T41,T274,T80	Yes	T41,T274,T80	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T96,*T98,*T102	Yes	T96,T98,T102	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T105,T103,T184	Yes	T105,T103,T184	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T97,T98,T104	Yes	T97,T98,T104	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T41,T274,T80	Yes	T41,T274,T80	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T41,T274,T80	Yes	T41,T274,T80	INPUT
tl_keymgr_i.d_error	Yes	Yes	T98,T104,T105	Yes	T97,T98,T102	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T41,T200,T231	Yes	T41,T200,T231	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T41,T200,T231	Yes	T41,T80,T200	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T41,T200,T231	Yes	T41,T80,T200	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T97,T98,T99	Yes	T97,T98,T102	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T96,*T98,*T105	Yes	T96,T98,T102	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T98,T99,T105	Yes	T98,T105,T103	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T41,*T200,*T231	Yes	T41,T274,T200	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T41,T274,T80	Yes	T41,T274,T80	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T58,*T310,*T74	Yes	T58,T310,T74	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T98,T104,T103	Yes	T98,T104,T103	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T74,T98,T102	Yes	T74,T97,T98	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T1,T7,T28	Yes	T1,T7,T28	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T1,T7,T28	Yes	T1,T7,T28	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T98,T104,T105	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T74,*T105,*T103	Yes	T58,T310,T74	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T98,T104,T105	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T80,T210,T213	Yes	T80,T210,T213	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T80,T210,T213	Yes	T80,T210,T213	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T80,T210,T213	Yes	T80,T210,T213	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T80,T210,T213	Yes	T80,T210,T213	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T80,T210,T213	Yes	T80,T210,T213	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T460,*T97,*T98	Yes	T460,T97,T98	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T97,T98,T104	Yes	T97,T98,T104	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T80,T210,T213	Yes	T80,T210,T213	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T80,T210,T213	Yes	T80,T210,T213	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T97,T98,T99	Yes	T97,T98,T104	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T213,T349,T350	Yes	T213,T349,T350	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T210,T213,T138	Yes	T80,T210,T213	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T210,T213,T138	Yes	T80,T210,T213	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T97,T98,T105	Yes	T97,T102,T105	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T97,*T99,*T105	Yes	T460,T97,T98	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T97,T98,T104	Yes	T97,T98,T104	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T210,*T213,*T138	Yes	T210,T213,T138	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T80,T210,T213	Yes	T80,T210,T213	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T7,T46,T41	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range