Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.91	92.47		89.25			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T47,T87,T677	Yes	T47,T87,T677	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T173,T231,T246	Yes	T173,T231,T246	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T173,T231,T246	Yes	T173,T231,T246	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T173,T80,T231	Yes	T173,T80,T231	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T173,T80,T192	Yes	T173,T80,T192	INPUT
tl_uart0_i.d_error	Yes	Yes	T98,T102,T105	Yes	T98,T102,T105	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T173,T246,T252	Yes	T173,T246,T252	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T173,T192,T246	Yes	T173,T80,T192	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T173,T192,T246	Yes	T173,T80,T192	INPUT
tl_uart0_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T98,T99,T102	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T96,*T58,*T310	Yes	T96,T58,T310	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T98,T102,T105	Yes	T97,T98,T102	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T173,*T246,*T252	Yes	T173,T246,T252	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T173,T80,T192	Yes	T173,T80,T192	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T73,T246,T96	Yes	T73,T246,T96	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T73,T246,T96	Yes	T73,T246,T96	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T73,T80,T192	Yes	T73,T80,T192	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T73,T80,T192	Yes	T73,T80,T192	INPUT
tl_uart1_i.d_error	Yes	Yes	T97,T104,T103	Yes	T97,T104,T103	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T73,T246,T96	Yes	T73,T246,T96	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T73,T192,T246	Yes	T73,T80,T192	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T73,T192,T246	Yes	T73,T80,T192	INPUT
tl_uart1_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T96,*T97,*T105	Yes	T96,T97,T98	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T73,*T246,*T96	Yes	T73,T246,T96	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T73,T80,T192	Yes	T73,T80,T192	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T32,T66,T246	Yes	T32,T66,T246	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T32,T66,T246	Yes	T32,T66,T246	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T32,T66,T80	Yes	T32,T66,T80	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T32,T66,T80	Yes	T32,T66,T80	INPUT
tl_uart2_i.d_error	Yes	Yes	T97,T98,T102	Yes	T97,T98,T184	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T32,T66,T246	Yes	T32,T66,T246	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T32,T66,T192	Yes	T32,T66,T80	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T32,T66,T192	Yes	T32,T66,T80	INPUT
tl_uart2_i.d_sink	Yes	Yes	T97,T98,T99	Yes	T97,T98,T105	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T96,*T97,*T105	Yes	T96,T97,T98	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T97,T98,T104	Yes	T97,T98,T99	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T32,*T66,*T246	Yes	T32,T66,T246	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T32,T66,T80	Yes	T32,T66,T80	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T30,T68,T246	Yes	T30,T68,T246	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T30,T68,T246	Yes	T30,T68,T246	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T30,T68,T80	Yes	T30,T68,T80	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T30,T68,T80	Yes	T30,T68,T80	INPUT
tl_uart3_i.d_error	Yes	Yes	T97,T98,T102	Yes	T98,T102,T104	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T30,T68,T246	Yes	T30,T68,T246	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T30,T68,T192	Yes	T30,T68,T80	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T30,T68,T192	Yes	T30,T68,T80	INPUT
tl_uart3_i.d_sink	Yes	Yes	T97,T98,T105	Yes	T98,T102,T104	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T96,*T105,*T103	Yes	T96,T97,T98	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T98,T99,T102	Yes	T97,T98,T102	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T30,*T68,*T246	Yes	T30,T68,T246	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T30,T68,T80	Yes	T30,T68,T80	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T410,T61,T257	Yes	T410,T61,T257	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T410,T61,T257	Yes	T410,T61,T257	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T410,T61,T80	Yes	T410,T61,T80	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T410,T61,T80	Yes	T410,T61,T80	INPUT
tl_i2c0_i.d_error	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T61,T257,T96	Yes	T61,T257,T96	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T410,T61,T192	Yes	T410,T61,T80	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T410,T61,T192	Yes	T410,T61,T80	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T97,T98,T99	Yes	T97,T102,T104	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T96,*T102,*T104	Yes	T96,T97,T98	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T102	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T410,*T61,*T257	Yes	T410,T61,T257	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T410,T61,T80	Yes	T410,T61,T80	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T33,T410,T63	Yes	T33,T410,T63	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T33,T410,T63	Yes	T33,T410,T63	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T33,T410,T63	Yes	T33,T410,T63	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T33,T410,T63	Yes	T33,T410,T63	INPUT
tl_i2c1_i.d_error	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T33,T63,T257	Yes	T33,T63,T257	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T33,T410,T63	Yes	T33,T410,T63	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T33,T410,T63	Yes	T33,T410,T63	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T97,T102,T104	Yes	T97,T98,T102	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T96,*T97,*T102	Yes	T96,T97,T98	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T33,*T410,*T63	Yes	T33,T410,T63	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T33,T410,T63	Yes	T33,T410,T63	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T64,T410,T257	Yes	T64,T410,T257	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T64,T410,T257	Yes	T64,T410,T257	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T64,T410,T80	Yes	T64,T410,T80	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T64,T410,T80	Yes	T64,T410,T80	INPUT
tl_i2c2_i.d_error	Yes	Yes	T102,T104,T105	Yes	T98,T102,T104	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T64,T257,T96	Yes	T64,T257,T96	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T64,T410,T192	Yes	T64,T410,T80	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T64,T410,T192	Yes	T64,T410,T80	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T98,T104,T105	Yes	T98,T102,T104	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T96,*T104,*T105	Yes	T96,T97,T98	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T98,T102,T104	Yes	T98,T104,T105	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T64,*T410,*T257	Yes	T64,T410,T257	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T64,T410,T80	Yes	T64,T410,T80	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T5,T169,T12	Yes	T5,T169,T12	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T5,T169,T12	Yes	T5,T169,T12	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T5,T80,T169	Yes	T5,T80,T169	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T5,T80,T169	Yes	T5,T80,T169	INPUT
tl_pattgen_i.d_error	Yes	Yes	T97,T98,T102	Yes	T97,T98,T99	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T5,T169,T12	Yes	T5,T169,T12	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T169,T12	Yes	T5,T80,T169	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T5,T169,T12	Yes	T5,T80,T169	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T97,T98,T99	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T69,T104,T105	Yes	T69,T97,T98	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T104	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T5,*T169,*T12	Yes	T5,T169,T12	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T5,T80,T169	Yes	T5,T80,T169	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T39,T75,T178	Yes	T39,T75,T178	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T39,T75,T178	Yes	T39,T75,T178	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T39,T80,T75	Yes	T39,T80,T75	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T39,T80,T75	Yes	T39,T80,T75	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T97,T99,T102	Yes	T97,T102,T104	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T39,T75,T178	Yes	T39,T75,T178	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T39,T75,T178	Yes	T39,T80,T75	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T39,T75,T178	Yes	T39,T80,T75	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T97,T102,T104	Yes	T97,T102,T104	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T74,*T105,*T103	Yes	T74,T97,T102	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T102	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T39,*T75,*T178	Yes	T39,T75,T178	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T39,T80,T75	Yes	T39,T80,T75	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_gpio_i.d_error	Yes	Yes	T97,T98,T99	Yes	T97,T98,T104	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T6,T31,T257	Yes	T6,T31,T257	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T31,T257	Yes	T6,T29,T31	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T6,T31,T257	Yes	T6,T29,T31	INPUT
tl_gpio_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T104	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T102	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T7,*T6,*T46	Yes	T1,T2,T4	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T6,T13,T10	Yes	T6,T13,T10	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T6,T13,T10	Yes	T6,T13,T10	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T6,T13,T10	Yes	T6,T13,T10	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T6,T13,T10	Yes	T6,T13,T10	INPUT
tl_spi_device_i.d_error	Yes	Yes	T102,T104,T105	Yes	T102,T104,T103	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T13,T10,T11	Yes	T13,T10,T11	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T13,T10	Yes	T6,T13,T10	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T6,T13,T10	Yes	T13,T10,T11	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T97,T98,T104	Yes	T98,T102,T104	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T104,*T105,*T103	Yes	T98,T102,T104	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T98,T102,T104	Yes	T98,T102,T104	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T6,*T13,*T10	Yes	T6,T13,T10	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T6,T13,T10	Yes	T6,T13,T10	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T168,T269,T169	Yes	T168,T269,T169	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T168,T269,T169	Yes	T168,T269,T169	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T168,T269,T80	Yes	T168,T269,T80	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T168,T269,T80	Yes	T168,T269,T80	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T98,T104,T105	Yes	T98,T102,T105	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T168,T269,T169	Yes	T168,T269,T169	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T168,T269,T169	Yes	T168,T269,T80	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T168,T269,T669	Yes	T168,T269,T80	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T97,T98,T104	Yes	T97,T98,T102	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T97,*T105,*T103	Yes	T97,T98,T102	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T98,T104,T105	Yes	T97,T98,T102	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T168,*T269,*T169	Yes	T168,T269,T169	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T168,T269,T80	Yes	T168,T269,T80	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T7,T6,T25	Yes	T7,T6,T25	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T7,T6,T25	Yes	T7,T6,T25	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T7,T6,T25	Yes	T7,T6,T25	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T7,T6,T25	Yes	T7,T6,T25	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T97,T98,T104	Yes	T97,T98,T104	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T7,T6,T25	Yes	T7,T6,T25	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T7,T6,T25	Yes	T7,T6,T25	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T7,T6,T25	Yes	T7,T6,T25	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T97,T102,T104	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T74,*T105,*T103	Yes	T74,T97,T98	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T97,T104,T105	Yes	T97,T98,T102	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T7,*T6,*T25	Yes	T7,T6,T25	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T7,T6,T25	Yes	T7,T6,T25	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T97,T102,T104	Yes	T97,T98,T102	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T46,T41,T47	Yes	T1,T2,T4	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T46,T41,T47	Yes	T1,T2,T4	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T74,*T97,*T98	Yes	T74,T97,T98	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T73,T32,T30	Yes	T73,T32,T30	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T73,T32,T30	Yes	T73,T32,T30	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T73,T32,T30	Yes	T73,T32,T30	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T46,T73,T32	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T46,T73,T32	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T97,T98,T105	Yes	T97,T98,T105	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T105,*T103,*T184	Yes	T185,T186,T675	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T97,T104,T105	Yes	T97,T102,T105	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T73,*T32,*T30	Yes	T73,T32,T30	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T97,T102,T103	Yes	T97,T98,T102	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T102,T104,T105	Yes	T98,T104,T105	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T74,*T69,*T103	Yes	T74,T69,T97	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T97,T104,T105	Yes	T97,T98,T105	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T102,T104,T103	Yes	T104,T103,T184	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T102,T104,T105	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T185,*T186,*T69	Yes	T185,T186,T69	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T98,T102,T104	Yes	T97,T104,T105	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T41,*T187,*T60	Yes	T41,T187,T188	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T69,T97,T98	Yes	T69,T97,T98	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T69,T97,T98	Yes	T69,T97,T98	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T69,T97,T98	Yes	T69,T97,T98	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T1,T2,T3	Yes	T46,T47,T59	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T69,T97,T98	Yes	T69,T97,T98	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T69,T97,T102	Yes	T69,T97,T98	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T46,T47,T59	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T97,T102,T104	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T69,T105,T103	Yes	T69,T97,T98	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T46,T47,T59	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T69,T97,T98	Yes	T69,T97,T98	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T1,T41,T30	Yes	T1,T41,T30	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T1,T41,T30	Yes	T1,T41,T30	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T1,T41,T30	Yes	T1,T41,T30	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T1,T41,T30	Yes	T1,T41,T30	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T98,T102,T104	Yes	T98,T104,T105	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T41,T187,T201	Yes	T1,T41,T187	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T201,T198,T142	Yes	T201,T80,T198	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T41,T187,T201	Yes	T1,T41,T30	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T98,T104,T105	Yes	T98,T104,T105	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T100,*T355,*T356	Yes	T100,T355,T356	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T98,T102,T104	Yes	T98,T102,T104	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T41,*T201,*T200	Yes	T1,T41,T30	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T1,T41,T30	Yes	T1,T41,T30	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T97,T98,T102	Yes	T97,T98,T99	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T131,T150,T155	Yes	T131,T150,T155	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T131,T150,T155	Yes	T80,T131,T150	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T46,T41,T47	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T97,T98,T99	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T97,*T98,*T102	Yes	T97,T98,T99	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T102	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T46,*T41,*T47	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T46,T47,T87	Yes	T46,T47,T87	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T46,T47,T87	Yes	T46,T47,T87	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T46,T47,T87	Yes	T46,T47,T87	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T46,T47,T87	Yes	T46,T47,T87	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T46,T47,T87	Yes	T46,T47,T87	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T46,T47,T87	Yes	T46,T47,T87	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T46,T47,T87	Yes	T46,T47,T87	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T102,*T105,*T103	Yes	T97,T98,T102	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T46,*T47,*T87	Yes	T46,T47,T87	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T46,T47,T87	Yes	T46,T47,T87	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T210,T138,T212	Yes	T210,T138,T212	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T210,T138,T212	Yes	T210,T138,T212	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T80,T210,T138	Yes	T80,T210,T138	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T80,T210,T138	Yes	T80,T210,T138	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T97,T98,T102	Yes	T98,T102,T105	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T210,T138,T212	Yes	T210,T138,T212	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T210,T138,T212	Yes	T80,T210,T138	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T210,T138,T212	Yes	T80,T210,T138	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T98,*T105,*T103	Yes	T97,T98,T102	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T210,*T138,*T212	Yes	T210,T138,T212	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T80,T210,T138	Yes	T80,T210,T138	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T46,T247,T47	Yes	T46,T247,T47	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T46,T41,T34	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T46,T247,T47	Yes	T46,T247,T47	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T46,T41,T247	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T46,T47,T87	Yes	T46,T47,T87	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T102,T104,T105	Yes	T97,T98,T102	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T40,*T58,*T101	Yes	T40,T58,T101	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T46,T247,T47	Yes	T46,T247,T47	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T46,T247,T47	Yes	T46,T247,T47	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T46,T247,T47	Yes	T46,T247,T47	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T46,T247,T47	Yes	T46,T247,T47	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T46,T247,T47	Yes	T46,T247,T47	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T46,T247,T47	Yes	T46,T247,T47	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T46,T247,T47	Yes	T46,T247,T47	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T99,*T102,*T105	Yes	T58,T310,T676	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T46,*T247,*T47	Yes	T46,T247,T47	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T46,T247,T47	Yes	T46,T247,T47	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T72,T14,T70	Yes	T72,T14,T70	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T72,T14,T70	Yes	T72,T14,T70	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T72,T14,T70	Yes	T72,T14,T70	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T72,T14,T70	Yes	T72,T14,T70	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T97,T98,T102	Yes	T97,T98,T104	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T72,T14,T70	Yes	T72,T14,T70	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T72,T14,T179	Yes	T72,T14,T179	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T72,T14,T70	Yes	T72,T14,T70	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T96,*T97,*T98	Yes	T96,T97,T98	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T99	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T72,*T14,*T179	Yes	T72,T14,T70	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T72,T14,T70	Yes	T72,T14,T70	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T140,T77,T90	Yes	T140,T77,T90	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T140,T77,T90	Yes	T140,T77,T90	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T80,T140,T77	Yes	T80,T140,T77	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T80,T140,T77	Yes	T80,T140,T77	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T97,T102,T104	Yes	T97,T102,T104	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T140,T77,T257	Yes	T140,T77,T90	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T140,T77,T90	Yes	T80,T140,T77	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T140,T77,T90	Yes	T80,T140,T77	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T102,*T104,*T105	Yes	T97,T98,T102	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T97,T98,T102	Yes	T97,T98,T102	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T140,*T77,*T257	Yes	T140,T77,T90	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T80,T140,T77	Yes	T80,T140,T77	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T100,*T40,*T96	Yes	T100,T40,T96	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T97,T98,T99	Yes	T97,T98,T99	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T40,T96,T101	Yes	T40,T96,T101	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	Yes	Yes	T102,T105,T103	Yes	T98,T102,T104	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T98,T102,T105	Yes	T97,T98,T102	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T7,T46,T41	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	Yes	Yes	T98,T102,T105	Yes	T97,T98,T102	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T102,*T105,*T103	Yes	T98,T102,T105	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T102,T105,T103	Yes	T98,T102,T104	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T97,*T98,*T102	Yes	T97,T102,T104	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range