Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	89.27	77.30			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	89.27	77.30			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		gen_target[0].u_target

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

	Line No.	Total	Covered	Percent
TOTAL		1258	1123	89.27
CONT_ASSIGN	72	1	0	0.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	85	0	0
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CONT_ASSIGN	85	1	1	100.00
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CONT_ASSIGN	85	1	1	100.00
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CONT_ASSIGN	85	0	0
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CONT_ASSIGN	85	0	0
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CONT_ASSIGN	85	0	0
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CONT_ASSIGN	85	0	0
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CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ROUTINE	114	0	0
ROUTINE	125	0	0
CONT_ASSIGN	138	0	0
CONT_ASSIGN	139	0	0

Click here to see the source line report.

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

	Total	Covered	Percent
Conditions	3313	2561	77.30
Logical	3313	2561	77.30
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
85	64.00
85	64.47
85	61.77
85	58.97
85	57.21
85-90	84.62
90	100.00
90-91	100.00
91	100.00
91-92	100.00
92	100.00

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

	Line No.	Total	Covered	Percent
Branches		1320	1320	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
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TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
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TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
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TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
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TERNARY	90	2	2	100.00
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TERNARY	90	1	1	100.00
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TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
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TERNARY	90	2	2	100.00
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TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
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TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T46
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T46
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T46
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T13,T33
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T13,T33
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T13,T33
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T68
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T68
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T68
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T33,T47
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T33,T47
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T33,T47
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T248,T134
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T248,T134
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T248,T134
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T73,T32,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T73,T32,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T73,T32,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T61,T257
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T61,T257
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T61,T257
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T47,T64
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T47,T64
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T47,T64
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T25,T29
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T25,T29
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T25,T29
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T272,T257,T273
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T272,T257,T273
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T272,T257,T273
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T73,T173,T246
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T73,T173,T246
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T73,T173,T246
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T30,T68
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T30,T68
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T30,T68
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T13,T61,T169
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T13,T61,T169
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T13,T61,T169
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T257,T260
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T257,T260
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T257,T260
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T64,T257,T261
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T64,T257,T261
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T64,T257,T261
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T47,T262
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T47,T262
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T47,T262
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T25,T29
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T25,T29
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T25,T29
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T251,T169,T272
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T251,T169,T272
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T251,T169,T272
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T272,T257,T273
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T272,T257,T273
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T272,T257,T273
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T173,T246,T254
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T173,T246,T254
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T173,T246,T254
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T73,T246,T174
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T73,T246,T174
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T73,T246,T174
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T66,T246
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T66,T246
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T66,T246
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T30,T68,T246
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T30,T68,T246
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T30,T68,T246
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T68
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T68
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T30,T31,T68
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T10,T31,T169
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T10,T31,T169
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T10,T31,T169
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T169,T257
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T169,T257
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T169,T257
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T257,T62
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T257,T62
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T257,T62
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T257,T260
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T257,T260
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T257,T260
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T63,T257
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T63,T257
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T63,T257
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T64,T257,T261
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T64,T257,T261
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T64,T257,T261
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T64,T257,T65
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T64,T257,T65
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T64,T257,T65
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T47,T262,T357
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T47,T262,T357
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T47,T262,T357
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T246,T189
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T246,T189
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T246,T189
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T247,T268,T269
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T247,T268,T269
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T247,T268,T269
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T248,T134
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T248,T134
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T248,T134
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T251,T169,T272
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T251,T169,T272
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T251,T169,T272
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T272,T257,T273
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T272,T257,T273
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T272,T257,T273
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T173,T246,T254
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T173,T246,T254
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T173,T246,T254
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T73,T246,T174
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T73,T246,T174
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T73,T246,T174
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T73,T32,T66
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T73,T32,T66
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T73,T32,T66
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T66,T246
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T66,T246
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T66,T246
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T66,T246
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T66,T246
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T66,T246
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T30,T68,T246
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T30,T68,T246
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T30,T68,T246
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T13,T169,T52
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T13,T169,T52
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T13,T169,T52
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T257,T62
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T257,T62
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T257,T62
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T257,T62
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T257,T62
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T257,T62
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T64,T257,T261
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T64,T257,T261
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T64,T257,T261
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T169,T176
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T169,T176
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T169,T176
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T47,T262,T357
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T47,T262,T357
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T47,T262,T357
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T46,T87,T192
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T46,T87,T192
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T46,T87,T192
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T246,T189
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T246,T189
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T246,T189
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T71,T140,T246
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T71,T140,T246
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T71,T140,T246
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T131,T169,T271
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T131,T169,T271
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T131,T169,T271
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T248,T134,T257
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T248,T134,T257
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T248,T134,T257
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T249,T250,T257
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T249,T250,T257
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T249,T250,T257
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T272,T257,T273
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T272,T257,T273
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T272,T257,T273
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T272,T257,T273
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T272,T257,T273
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T272,T257,T273
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T173,T246,T253
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T173,T246,T253
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T173,T246,T253
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T173,T246,T254
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T173,T246,T254
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T173,T246,T254
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T173,T246,T253
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T173,T246,T253
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T173,T246,T253
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T73,T246,T174
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T73,T246,T174
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T73,T246,T174
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T73,T246,T174
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T73,T246,T174
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T73,T246,T174
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T66,T246
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T66,T246
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T66,T246
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T66,T246
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T66,T246
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T66,T246
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T66,T246
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T66,T246
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T66,T246
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T30,T68,T246
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T30,T68,T246
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T30,T68,T246
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T30,T68,T246
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T30,T68,T246
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T30,T68,T246
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T257,T44
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T10,T169,T232
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T10,T169,T232
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T10,T169,T232
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T257,T62
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T257,T62
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T61,T257,T62
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T257,T260
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T257,T260
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T257,T260
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T63,T257
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T63,T257
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T63,T257
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T64,T257,T261
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T64,T257,T261
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T64,T257,T261
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T169,T189
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T169,T189
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T169,T189
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T47,T262,T357
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T47,T262,T357
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T47,T262,T357
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T265,T266
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T265,T266
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T265,T266
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T246,T255,T256
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T25,T29
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T25,T29
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T25,T29
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T140,T257,T267
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T140,T257,T267
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T140,T257,T267
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T247,T269,T357
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T247,T269,T357
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T247,T269,T357
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T248,T134
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T248,T134
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T248,T134
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T248,T134,T257
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T248,T134,T257
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T248,T134,T257
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T189,T190
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T272,T257,T273
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T272,T257,T273
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T272,T257,T273
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T257,T258,T259
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxComputationInvalid_A	491686938	489508197	0	0
MaxComputation_A	491686938	2073521	0	0
MaxIndexComputationInvalid_A	491686938	489508197	0	0
MaxIndexComputation_A	491686938	2073521	0	0
NumSources_A	1017	1017	0	0
ValidInImpliesValidOut_A	491686938	491581718	0	0

MaxComputationInvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	489508197	0	0
T1	111924	110308	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100680	0	0
T6	100982	98902	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

MaxComputation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	2073521	0	0
T1	111924	1554	0	0
T2	78951	0	0	0
T3	42255	0	0	0
T4	103207	0	0	0
T5	100889	147	0	0
T6	100982	2018	0	0
T7	100472	0	0	0
T13	0	8379	0	0
T25	0	199	0	0
T28	97609	0	0	0
T29	0	721	0	0
T30	0	1189	0	0
T32	0	1221	0	0
T46	0	513	0	0
T73	0	1195	0	0
T109	67839	0	0	0
T110	68617	0	0	0

MaxIndexComputationInvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	489508197	0	0
T1	111924	110308	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100680	0	0
T6	100982	98902	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0

MaxIndexComputation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	2073521	0	0
T1	111924	1554	0	0
T2	78951	0	0	0
T3	42255	0	0	0
T4	103207	0	0	0
T5	100889	147	0	0
T6	100982	2018	0	0
T7	100472	0	0	0
T13	0	8379	0	0
T25	0	199	0	0
T28	97609	0	0	0
T29	0	721	0	0
T30	0	1189	0	0
T32	0	1221	0	0
T46	0	513	0	0
T73	0	1195	0	0
T109	67839	0	0	0
T110	68617	0	0	0

NumSources_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017	1017	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T28	1	1	0	0
T109	1	1	0	0
T110	1	1	0	0

ValidInImpliesValidOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491686938	491581718	0	0
T1	111924	111862	0	0
T2	78951	78893	0	0
T3	42255	42193	0	0
T4	103207	103149	0	0
T5	100889	100827	0	0
T6	100982	100920	0	0
T7	100472	100417	0	0
T28	97609	97547	0	0
T109	67839	67784	0	0
T110	68617	68562	0	0