Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3812302	1			T84	73		T85	90		T86	24
values[2]	754698	1			T84	42		T85	31		T86	81
values[3]	110365	1			T86	108		T234	3		T452	2
values[4]	59916	1			T86	28		T569	106		T557	1
values[5]	39481	1			T86	5		T569	56		T568	49
values[6]	29268	1			T86	2		T569	33		T568	50
values[7]	23588	1			T86	1		T569	13		T568	42
values[8]	20021	1			T86	1		T569	4		T568	72
values[9]	17558	1			T86	1		T569	2		T568	63
values[10]	15726	1			T86	3		T569	1		T568	49
values[11]	14788	1			T86	3		T569	1		T568	49
values[12]	13489	1			T86	5		T569	3		T568	63
values[13]	13030	1			T86	8		T569	6		T568	65
values[14]	12216	1			T86	9		T569	4		T568	51
values[15]	11614	1			T86	3		T569	4		T568	47
values[16]	10891	1			T86	3		T569	1		T568	43
values[17]	10402	1			T86	4		T568	23		T563	5
values[18]	10117	1			T86	1		T568	27		T563	3
values[19]	9891	1			T86	1		T568	37		T563	2
values[20]	9647	1			T86	1		T568	51		T563	7
values[21]	9460	1			T86	1		T568	85		T563	5
values[22]	9193	1			T86	1		T568	82		T563	2
values[23]	8951	1			T86	1		T568	84		T563	2
values[24]	8423	1			T86	1		T568	65		T563	4
values[25]	8070	1			T86	1		T568	38		T563	2
values[26]	7862	1			T86	6		T568	58		T563	3
values[27]	7534	1			T86	2		T568	42		T563	3
values[28]	7263	1			T86	2		T568	32		T563	3
values[29]	6572	1			T86	1		T568	18		T563	7
values[30]	6038	1			T86	1		T568	23		T563	6
values[31]	5572	1			T86	2		T568	14		T563	4
values[32]	5076	1			T86	1		T568	20		T563	6
values[33]	4779	1			T86	1		T568	15		T563	6
values[34]	4348	1			T86	3		T568	17		T563	3
values[35]	4186	1			T86	1		T568	12		T563	4
values[36]	3946	1			T86	1		T568	14		T563	2
values[37]	3798	1			T86	2		T568	22		T563	4
values[38]	3500	1			T86	1		T568	21		T563	3
values[39]	3274	1			T86	1		T568	10		T563	4
values[40]	3252	1			T86	3		T568	14		T563	2
values[41]	3191	1			T86	1		T568	13		T563	4
values[42]	3107	1			T86	2		T568	14		T563	3
values[43]	2913	1			T86	4		T568	4		T563	6
values[44]	2944	1			T86	2		T568	7		T563	3
values[45]	2943	1			T86	2		T568	4		T563	8
values[46]	2838	1			T86	1		T568	7		T563	2
values[47]	2734	1			T86	1		T568	5		T563	2
values[48]	2774	1			T86	1		T568	2		T563	3
values[49]	2642	1			T86	1		T568	5		T563	2
values[50]	2579	1			T86	1		T568	2		T563	5
values[51]	2598	1			T86	1		T568	2		T563	3
values[52]	2579	1			T86	2		T568	4		T563	2
values[53]	2496	1			T86	1		T568	2		T563	2
values[54]	2424	1			T86	1		T563	5		T439	5
values[55]	2306	1			T86	1		T563	2		T439	1
values[56]	2381	1			T86	1		T563	2		T439	3
values[57]	2282	1			T86	3		T563	4		T474	8
values[58]	2173	1			T86	4		T563	4		T810	5
values[59]	2159	1			T86	1		T563	5		T810	9
values[60]	2231	1			T86	1		T563	5		T810	4
values[61]	2536	1			T86	1		T563	8		T810	4
values[62]	4170	1			T86	6		T563	12		T810	3
values[63]	11793	1			T86	14		T563	68		T810	30
values[64]	143813	1			T86	60		T563	212		T810	136

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4834416	1			T84	110		T85	116		T86	373
values[2]	791578	1			T84	29		T85	30		T86	77
values[3]	77403	1			T84	1		T85	4		T86	8
values[4]	12794	1			T91	1		T234	1		T451	1
values[5]	4950	1			T566	1		T821	2		T563	1
values[6]	3257	1			T566	1		T563	2		T634	1
values[7]	2773	1			T563	4		T634	1		T659	22
values[8]	2388	1			T563	5		T659	9		T662	3
values[9]	2089	1			T563	2		T659	4		T662	6
values[10]	1841	1			T563	1		T659	7		T662	8
values[11]	1607	1			T563	5		T659	11		T662	19
values[12]	1468	1			T563	2		T659	18		T662	7
values[13]	1409	1			T563	1		T659	14		T662	10
values[14]	1280	1			T563	1		T659	12		T662	25
values[15]	1111	1			T563	2		T659	8		T662	11
values[16]	982	1			T563	7		T659	11		T662	5
values[17]	847	1			T563	1		T659	16		T662	5
values[18]	882	1			T563	1		T659	6		T662	10
values[19]	800	1			T563	1		T659	13		T662	7
values[20]	852	1			T563	1		T659	18		T662	9
values[21]	822	1			T563	2		T659	22		T662	4
values[22]	749	1			T563	1		T659	7		T662	2
values[23]	720	1			T563	1		T659	4		T662	2
values[24]	699	1			T563	1		T659	7		T662	9
values[25]	680	1			T563	1		T659	6		T662	15
values[26]	710	1			T563	1		T659	11		T662	22
values[27]	622	1			T563	1		T659	11		T662	15
values[28]	526	1			T563	1		T659	11		T662	7
values[29]	549	1			T563	1		T659	16		T662	10
values[30]	460	1			T563	1		T659	10		T662	2
values[31]	471	1			T563	1		T659	12		T662	2
values[32]	507	1			T563	1		T659	10		T662	1
values[33]	485	1			T563	1		T659	10		T662	3
values[34]	503	1			T563	1		T659	5		T662	3
values[35]	462	1			T563	1		T659	9		T662	3
values[36]	463	1			T563	2		T659	5		T662	1
values[37]	454	1			T563	1		T659	10		T662	1
values[38]	506	1			T563	1		T659	9		T662	3
values[39]	433	1			T563	1		T659	4		T662	1
values[40]	426	1			T563	2		T659	2		T662	2
values[41]	367	1			T563	3		T659	1		T662	4
values[42]	417	1			T563	1		T659	1		T662	2
values[43]	392	1			T563	4		T662	2		T475	7
values[44]	385	1			T563	2		T662	5		T475	11
values[45]	386	1			T563	5		T662	2		T475	9
values[46]	403	1			T563	2		T662	1		T475	13
values[47]	363	1			T563	1		T662	2		T475	13
values[48]	369	1			T563	1		T662	2		T475	9
values[49]	371	1			T563	1		T662	2		T475	12
values[50]	360	1			T563	1		T662	2		T475	10
values[51]	371	1			T563	1		T662	1		T475	10
values[52]	362	1			T563	1		T662	1		T475	10
values[53]	368	1			T563	1		T662	1		T475	13
values[54]	321	1			T563	1		T662	2		T475	9
values[55]	327	1			T563	1		T662	1		T475	6
values[56]	315	1			T563	2		T662	1		T475	4
values[57]	324	1			T563	2		T662	2		T475	11
values[58]	308	1			T563	1		T662	2		T475	9
values[59]	297	1			T563	1		T662	2		T475	9
values[60]	304	1			T563	1		T662	1		T475	12
values[61]	333	1			T563	2		T662	1		T475	12
values[62]	637	1			T563	5		T662	5		T475	12
values[63]	2501	1			T563	27		T662	40		T475	62
values[64]	18154	1			T563	91		T662	105		T475	184

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	619020	1			T84	1		T85	2		T86	2
values[2]	2672446	1			T84	103		T85	81		T86	9
values[3]	1187698	1			T84	45		T85	59		T86	17
values[4]	156032	1			T85	1		T86	25		T234	18
values[5]	85092	1			T86	35		T569	107		T460	1
values[6]	55452	1			T86	52		T569	77		T568	62
values[7]	39460	1			T86	46		T569	44		T568	68
values[8]	30179	1			T86	28		T569	36		T568	44
values[9]	25086	1			T86	13		T569	39		T568	73
values[10]	21942	1			T86	2		T569	32		T568	61
values[11]	20120	1			T86	4		T569	16		T568	52
values[12]	18574	1			T86	1		T569	5		T568	39
values[13]	17251	1			T86	3		T569	3		T568	47
values[14]	15913	1			T86	2		T568	36		T563	3
values[15]	14848	1			T86	2		T568	61		T563	4
values[16]	14191	1			T86	2		T568	80		T563	4
values[17]	13592	1			T86	4		T568	68		T563	3
values[18]	12890	1			T86	1		T568	50		T563	5
values[19]	12105	1			T86	7		T568	44		T563	7
values[20]	11570	1			T86	12		T568	20		T563	3
values[21]	11126	1			T86	8		T568	37		T563	3
values[22]	10639	1			T86	2		T568	45		T563	2
values[23]	10162	1			T86	2		T568	61		T563	4
values[24]	9743	1			T86	3		T568	60		T563	4
values[25]	9389	1			T86	1		T568	49		T563	4
values[26]	9120	1			T86	2		T568	23		T563	7
values[27]	8370	1			T86	3		T568	19		T563	6
values[28]	7869	1			T86	4		T568	32		T563	3
values[29]	7455	1			T86	3		T568	39		T563	5
values[30]	7001	1			T86	3		T568	23		T563	2
values[31]	6578	1			T86	3		T568	20		T563	3
values[32]	6153	1			T86	2		T568	15		T563	5
values[33]	5832	1			T86	2		T568	45		T563	10
values[34]	5403	1			T86	1		T568	28		T563	7
values[35]	4979	1			T86	1		T568	39		T563	5
values[36]	4601	1			T86	3		T568	28		T563	7
values[37]	4349	1			T86	3		T568	10		T563	3
values[38]	4157	1			T86	6		T568	7		T563	6
values[39]	3943	1			T86	11		T568	1		T563	4
values[40]	3700	1			T86	2		T568	4		T563	4
values[41]	3548	1			T86	2		T568	1		T563	6
values[42]	3433	1			T86	4		T568	1		T563	3
values[43]	3381	1			T86	1		T568	1		T563	4
values[44]	3363	1			T86	2		T568	3		T563	4
values[45]	3236	1			T86	2		T568	4		T563	3
values[46]	3172	1			T86	2		T568	1		T563	2
values[47]	3059	1			T86	2		T568	6		T563	2
values[48]	3035	1			T86	3		T568	2		T563	4
values[49]	3087	1			T86	4		T563	4		T439	3
values[50]	2982	1			T86	1		T563	2		T439	2
values[51]	2835	1			T86	2		T563	2		T439	3
values[52]	2788	1			T86	2		T563	6		T439	5
values[53]	2746	1			T86	2		T563	7		T439	4
values[54]	2664	1			T86	2		T563	3		T439	1
values[55]	2654	1			T86	2		T563	2		T439	2
values[56]	2687	1			T86	3		T563	3		T439	4
values[57]	2552	1			T86	7		T563	6		T439	2
values[58]	2551	1			T86	6		T563	5		T439	1
values[59]	2481	1			T86	4		T563	4		T439	4
values[60]	2492	1			T86	9		T563	4		T439	2
values[61]	2596	1			T86	3		T563	6		T810	6
values[62]	3630	1			T86	2		T563	10		T810	11
values[63]	9488	1			T86	6		T563	57		T810	15
values[64]	130639	1			T86	39		T563	159		T810	53