Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1480562	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

33885106

1

T1

6662

T2

4871

T3

2860

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	23881130	1			T1	2843		T2	1748		T3	362
values[0x0]	10123812	1			T1	3819		T2	3123		T3	2498
values[0x1]	1360726	1			T1	391		T2	373		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	331848	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

35033820

1

T1

7053

T2

5244

T3

2882

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16954381	1			T1	3527		T2	2622		T3	1441
valid_sources[0x01]	16953536	1			T1	3526		T2	2622		T3	1441
valid_sources[0x02]	23590	1			T58	1		T163	195		T412	31
valid_sources[0x03]	23102	1			T220	7		T411	2		T163	159
valid_sources[0x04]	23267	1			T219	5		T163	107		T412	17
valid_sources[0x05]	23586	1			T221	1		T163	106		T412	11
valid_sources[0x06]	23164	1			T219	1		T411	6		T163	139
valid_sources[0x07]	23703	1			T41	1		T163	105		T412	14
valid_sources[0x08]	23552	1			T221	1		T163	134		T412	14
valid_sources[0x09]	23212	1			T220	4		T411	1		T163	73
valid_sources[0x0a]	23192	1			T58	1		T221	8		T411	41
valid_sources[0x0b]	22885	1			T219	1		T221	2		T411	2
valid_sources[0x0c]	24135	1			T411	1		T163	168		T412	28
valid_sources[0x0d]	23362	1			T58	3		T219	2		T163	137
valid_sources[0x0e]	22787	1			T163	138		T412	15		T561	15
valid_sources[0x0f]	22927	1			T58	1		T411	1		T163	119
valid_sources[0x10]	23787	1			T219	1		T163	165		T412	45
valid_sources[0x11]	23262	1			T411	5		T163	169		T412	20
valid_sources[0x12]	24241	1			T411	3		T163	146		T412	15
valid_sources[0x13]	23355	1			T58	1		T221	1		T163	169
valid_sources[0x14]	25845	1			T58	2		T219	1		T163	185
valid_sources[0x15]	23416	1			T58	1		T41	9		T221	4
valid_sources[0x16]	23488	1			T58	2		T219	4		T220	2
valid_sources[0x17]	23719	1			T58	1		T219	3		T411	5
valid_sources[0x18]	22928	1			T219	3		T221	1		T411	4
valid_sources[0x19]	23473	1			T58	1		T221	4		T411	2
valid_sources[0x1a]	24109	1			T58	1		T411	2		T163	187
valid_sources[0x1b]	24120	1			T41	1		T220	1		T163	159
valid_sources[0x1c]	23753	1			T163	172		T412	26		T561	14
valid_sources[0x1d]	23509	1			T58	1		T219	1		T163	130
valid_sources[0x1e]	23448	1			T58	2		T41	8		T219	4
valid_sources[0x1f]	23382	1			T163	104		T412	12		T561	9
valid_sources[0x20]	23708	1			T58	2		T41	1		T220	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23570582

1

T1

2843

T2

1748

T3

362

values[0x0]

all_enables

biggest_size

10074419

1

T1

3819

T2

3123

T3

2498

values[0x1]

all_enables

biggest_size

240105

1

T58

19

T88

25

T41

17

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2691446	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

424670

1

T84

18

T85

16

T86

57

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1058289	1			T84	37		T85	38		T86	142
values[0x0]	1000212	1			T84	35		T85	40		T86	148
values[0x1]	1057615	1			T84	43		T85	43		T86	148

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2081823	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1034293

1

T84

37

T85

41

T86

141

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	48622	1			T86	3		T91	4		T89	5
valid_sources[0x01]	48236	1			T84	4		T86	3		T91	4
valid_sources[0x02]	47870	1			T85	3		T86	9		T91	7
valid_sources[0x03]	48046	1			T84	1		T85	2		T86	4
valid_sources[0x04]	49413	1			T84	4		T85	1		T86	7
valid_sources[0x05]	49150	1			T85	8		T86	14		T91	3
valid_sources[0x06]	49139	1			T85	2		T86	1		T91	2
valid_sources[0x07]	48876	1			T84	4		T85	2		T86	8
valid_sources[0x08]	48116	1			T85	4		T86	8		T91	2
valid_sources[0x09]	48156	1			T86	4		T91	5		T89	15
valid_sources[0x0a]	48959	1			T84	3		T86	6		T91	3
valid_sources[0x0b]	48225	1			T86	2		T91	11		T89	7
valid_sources[0x0c]	48088	1			T85	1		T86	3		T91	3
valid_sources[0x0d]	49451	1			T84	4		T85	7		T86	9
valid_sources[0x0e]	49440	1			T85	4		T86	4		T91	2
valid_sources[0x0f]	49303	1			T84	6		T86	5		T91	1
valid_sources[0x10]	48080	1			T84	4		T85	4		T86	14
valid_sources[0x11]	48660	1			T84	3		T85	2		T86	7
valid_sources[0x12]	49775	1			T85	2		T86	9		T91	3
valid_sources[0x13]	49014	1			T84	7		T86	6		T91	6
valid_sources[0x14]	48839	1			T85	7		T86	7		T89	4
valid_sources[0x15]	49627	1			T86	9		T91	4		T89	9
valid_sources[0x16]	48497	1			T84	1		T85	1		T86	7
valid_sources[0x17]	48270	1			T84	2		T86	9		T89	6
valid_sources[0x18]	50886	1			T84	5		T86	4		T91	1
valid_sources[0x19]	48707	1			T84	6		T86	5		T91	2
valid_sources[0x1a]	48275	1			T84	1		T85	1		T86	5
valid_sources[0x1b]	48924	1			T85	2		T86	3		T91	1
valid_sources[0x1c]	48666	1			T86	5		T91	2		T89	6
valid_sources[0x1d]	48186	1			T86	10		T91	3		T89	8
valid_sources[0x1e]	48111	1			T84	7		T86	11		T91	4
valid_sources[0x1f]	48494	1			T85	6		T86	4		T91	1
valid_sources[0x20]	49285	1			T84	1		T85	2		T86	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45133

1

T84

3

T85

3

T86

6

values[0x0]

all_enables

biggest_size

334466

1

T84

13

T85

13

T86

43

values[0x1]

all_enables

biggest_size

45071

1

T84

2

T86

8

T89

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2892572	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

469536

1

T84

18

T85

19

T86

57

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1153059	1			T84	52		T85	49		T86	160
values[0x0]	1055284	1			T84	42		T85	48		T86	136
values[0x1]	1153765	1			T84	46		T85	53		T86	162

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2217589	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1144519

1

T84

46

T85

44

T86

147

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52634	1			T86	7		T89	27		T155	1
valid_sources[0x01]	53323	1			T84	5		T85	21		T86	9
valid_sources[0x02]	52065	1			T86	3		T234	19		T452	1
valid_sources[0x03]	52420	1			T86	5		T89	41		T234	20
valid_sources[0x04]	52833	1			T85	15		T86	9		T91	2
valid_sources[0x05]	52785	1			T86	6		T91	9		T234	11
valid_sources[0x06]	52427	1			T86	7		T91	1		T89	15
valid_sources[0x07]	52039	1			T86	3		T91	9		T155	1
valid_sources[0x08]	51379	1			T85	3		T86	5		T91	9
valid_sources[0x09]	51648	1			T86	9		T89	1		T155	1
valid_sources[0x0a]	52070	1			T85	5		T86	8		T91	6
valid_sources[0x0b]	51853	1			T85	4		T86	10		T91	1
valid_sources[0x0c]	52242	1			T85	2		T86	5		T91	6
valid_sources[0x0d]	52713	1			T86	7		T91	3		T89	34
valid_sources[0x0e]	52987	1			T84	9		T85	1		T86	13
valid_sources[0x0f]	53504	1			T86	7		T91	2		T155	2
valid_sources[0x10]	52599	1			T85	6		T86	5		T91	5
valid_sources[0x11]	52886	1			T84	7		T86	6		T91	3
valid_sources[0x12]	53992	1			T84	19		T85	2		T86	8
valid_sources[0x13]	53495	1			T85	1		T86	7		T91	6
valid_sources[0x14]	53218	1			T84	3		T85	12		T86	9
valid_sources[0x15]	52253	1			T86	13		T91	8		T89	2
valid_sources[0x16]	51653	1			T85	1		T86	5		T89	15
valid_sources[0x17]	52526	1			T85	4		T86	7		T91	3
valid_sources[0x18]	52632	1			T84	3		T85	5		T86	12
valid_sources[0x19]	51659	1			T85	9		T86	3		T90	5
valid_sources[0x1a]	52586	1			T85	5		T86	8		T91	3
valid_sources[0x1b]	51939	1			T86	7		T91	6		T89	13
valid_sources[0x1c]	52725	1			T86	8		T234	16		T452	5
valid_sources[0x1d]	53281	1			T85	5		T86	9		T155	2
valid_sources[0x1e]	52065	1			T85	2		T86	4		T91	5
valid_sources[0x1f]	53318	1			T84	36		T85	5		T86	10
valid_sources[0x20]	52374	1			T84	5		T85	1		T86	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49744

1

T84

2

T86

4

T91

2

values[0x0]

all_enables

biggest_size

370276

1

T84

13

T85

15

T86

47

values[0x1]

all_enables

biggest_size

49516

1

T84

3

T85

4

T86

6

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2716460	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

428377

1

T84

33

T85

23

T86

49

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1067084	1			T84	49		T85	47		T86	149
values[0x0]	1009637	1			T84	55		T85	38		T86	139
values[0x1]	1068116	1			T84	45		T85	58		T86	156

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2100433	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1044404

1

T84

70

T85

51

T86

143

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	49641	1			T85	5		T86	3		T89	9
valid_sources[0x01]	48998	1			T84	8		T86	4		T89	11
valid_sources[0x02]	48899	1			T84	3		T85	2		T86	11
valid_sources[0x03]	49828	1			T84	3		T86	3		T91	8
valid_sources[0x04]	49444	1			T84	1		T85	2		T86	6
valid_sources[0x05]	49489	1			T84	1		T86	9		T89	7
valid_sources[0x06]	48671	1			T84	3		T85	1		T86	10
valid_sources[0x07]	48290	1			T84	6		T86	8		T91	12
valid_sources[0x08]	49403	1			T84	1		T85	8		T86	7
valid_sources[0x09]	48760	1			T84	2		T86	11		T91	2
valid_sources[0x0a]	49225	1			T84	1		T86	8		T89	12
valid_sources[0x0b]	48327	1			T84	4		T86	7		T89	8
valid_sources[0x0c]	48910	1			T84	2		T85	2		T86	5
valid_sources[0x0d]	48999	1			T84	1		T85	9		T86	5
valid_sources[0x0e]	49212	1			T84	1		T85	1		T86	9
valid_sources[0x0f]	48981	1			T85	1		T86	4		T89	9
valid_sources[0x10]	48867	1			T84	1		T86	4		T91	3
valid_sources[0x11]	49073	1			T84	1		T86	8		T91	18
valid_sources[0x12]	50230	1			T84	2		T86	8		T89	11
valid_sources[0x13]	49710	1			T84	1		T85	5		T86	8
valid_sources[0x14]	49749	1			T84	5		T85	1		T86	7
valid_sources[0x15]	49436	1			T84	4		T85	4		T86	10
valid_sources[0x16]	48805	1			T85	6		T86	7		T89	8
valid_sources[0x17]	49387	1			T84	3		T85	2		T86	9
valid_sources[0x18]	49673	1			T85	4		T86	4		T89	9
valid_sources[0x19]	49666	1			T84	3		T85	3		T86	5
valid_sources[0x1a]	47952	1			T84	4		T86	10		T91	4
valid_sources[0x1b]	48657	1			T86	6		T89	6		T90	5
valid_sources[0x1c]	48338	1			T84	3		T86	9		T91	10
valid_sources[0x1d]	48845	1			T84	2		T85	3		T86	10
valid_sources[0x1e]	48950	1			T84	2		T85	3		T86	9
valid_sources[0x1f]	48870	1			T86	5		T89	12		T90	2
valid_sources[0x20]	48888	1			T84	5		T85	9		T86	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45461

1

T84

1

T85

3

T86

5

values[0x0]

all_enables

biggest_size

337791

1

T84

30

T85

17

T86

43

values[0x1]

all_enables

biggest_size

45125

1

T84

2

T85

3

T86

1