Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.18			93.18

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_i2c0	93.10			93.10
tb.dut.top_earlgrey.u_i2c1	93.14			93.14
tb.dut.top_earlgrey.u_i2c2	93.14			93.14

---

Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.10			93.10

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.10			93.10

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.14			93.14

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.14			93.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.14			93.14

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.14			93.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	54	48	88.89
Total Bits	352	328	93.18
Total Bits 0->1	176	164	93.18
Total Bits 1->0	176	164	93.18

Ports	54	48	88.89
Port Bits	352	328	93.18
Port Bits 0->1	176	164	93.18
Port Bits 1->0	176	164	93.18

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T35,T404,T36	Yes	T35,T404,T36	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T35,T404,T36	Yes	T35,T404,T36	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	INPUT
tl_i.a_valid	Yes	Yes	T35,T404,T36	Yes	T35,T404,T36	INPUT
tl_o.a_ready	Yes	Yes	T35,T404,T36	Yes	T35,T404,T36	OUTPUT
tl_o.d_error	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T35,T36,T31	Yes	T35,T36,T31	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T35,T404,T36	Yes	T35,T404,T36	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T35,T404,T36	Yes	T35,T404,T36	OUTPUT
tl_o.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T84,*T85,*T89	Yes	T84,T85,T91	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T35,*T404,*T36	Yes	T35,T404,T36	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T35,T404,T36	Yes	T35,T404,T36	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T68,T92,T181	Yes	T68,T92,T181	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T92,T93,T226	Yes	T92,T93,T226	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T92,T93,T226	Yes	T92,T93,T226	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T68,T92,T181	Yes	T68,T92,T181	OUTPUT
cio_scl_i	Yes	Yes	T35,T36,T31	Yes	T35,T36,T31	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T36,T31,T33	Yes	T36,T31,T33	OUTPUT
cio_sda_i	Yes	Yes	T35,T36,T31	Yes	T35,T36,T31	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T35,T36,T31	Yes	T35,T36,T31	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T36,T31,T33	Yes	T36,T31,T33	OUTPUT
intr_rx_threshold_o	Yes	Yes	T36,T31,T33	Yes	T36,T31,T33	OUTPUT
intr_acq_threshold_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_rx_overflow_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_controller_halt_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_scl_interference_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_sda_interference_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_sda_unstable_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_cmd_complete_o	Yes	Yes	T35,T36,T31	Yes	T35,T36,T31	OUTPUT
intr_tx_stretch_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_tx_threshold_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_acq_stretch_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_unexp_stop_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_host_timeout_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0

	Total	Covered	Percent
Totals	54	48	88.89
Total Bits	348	324	93.10
Total Bits 0->1	174	162	93.10
Total Bits 1->0	174	162	93.10

Ports	54	48	88.89
Port Bits	348	324	93.10
Port Bits 0->1	174	162	93.10
Port Bits 1->0	174	162	93.10

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T404,T31,T325	Yes	T404,T31,T325	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T404,T31,T325	Yes	T404,T31,T325	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	INPUT
tl_i.a_valid	Yes	Yes	T404,T31,T68	Yes	T404,T31,T68	INPUT
tl_o.a_ready	Yes	Yes	T404,T31,T68	Yes	T404,T31,T68	OUTPUT
tl_o.d_error	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T31,T325,T10	Yes	T31,T325,T10	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T404,T31,T181	Yes	T404,T31,T68	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T404,T31,T181	Yes	T404,T31,T68	OUTPUT
tl_o.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T89,*T90,*T155	Yes	T84,T85,T91	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T89	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T404,*T31,*T325	Yes	T404,T31,T325	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T404,T31,T68	Yes	T404,T31,T68	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T68,T92,T181	Yes	T68,T92,T181	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T92,T93,T226	Yes	T92,T93,T226	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T92,T93,T226	Yes	T92,T93,T226	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T68,T92,T181	Yes	T68,T92,T181	OUTPUT
cio_scl_i	Yes	Yes	T31,T10,T32	Yes	T31,T10,T32	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T31,T10,T32	Yes	T31,T10,T32	OUTPUT
cio_sda_i	Yes	Yes	T31,T10,T32	Yes	T31,T10,T32	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T31,T10,T32	Yes	T31,T10,T32	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T31,T325,T32	Yes	T31,T325,T32	OUTPUT
intr_rx_threshold_o	Yes	Yes	T31,T325,T32	Yes	T31,T325,T32	OUTPUT
intr_acq_threshold_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_rx_overflow_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_controller_halt_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_scl_interference_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_sda_interference_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_sda_unstable_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_cmd_complete_o	Yes	Yes	T31,T325,T32	Yes	T31,T325,T32	OUTPUT
intr_tx_stretch_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_tx_threshold_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_acq_stretch_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_unexp_stop_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_host_timeout_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1

	Total	Covered	Percent
Totals	54	48	88.89
Total Bits	350	326	93.14
Total Bits 0->1	175	163	93.14
Total Bits 1->0	175	163	93.14

Ports	54	48	88.89
Port Bits	350	326	93.14
Port Bits 0->1	175	163	93.14
Port Bits 1->0	175	163	93.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T404,T33,T325	Yes	T404,T33,T325	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T404,T33,T325	Yes	T404,T33,T325	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	INPUT
tl_i.a_valid	Yes	Yes	T404,T33,T68	Yes	T404,T33,T68	INPUT
tl_o.a_ready	Yes	Yes	T404,T33,T68	Yes	T404,T33,T68	OUTPUT
tl_o.d_error	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T33,T325,T10	Yes	T33,T325,T10	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T404,T33,T181	Yes	T404,T33,T68	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T404,T33,T181	Yes	T404,T33,T68	OUTPUT
tl_o.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T84,*T89,*T155	Yes	T84,T85,T91	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T404,*T33,*T325	Yes	T404,T33,T325	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T404,T33,T68	Yes	T404,T33,T68	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T68,T92,T181	Yes	T68,T92,T181	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T92,T93,T226	Yes	T93,T226,T94	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T93,T226,T94	Yes	T92,T93,T226	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T68,T92,T181	Yes	T68,T92,T181	OUTPUT
cio_scl_i	Yes	Yes	T33,T10,T34	Yes	T33,T10,T34	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T33,T10,T34	Yes	T33,T10,T34	OUTPUT
cio_sda_i	Yes	Yes	T33,T10,T34	Yes	T33,T10,T34	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T33,T10,T34	Yes	T33,T10,T34	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T33,T325,T34	Yes	T33,T325,T34	OUTPUT
intr_rx_threshold_o	Yes	Yes	T33,T325,T34	Yes	T33,T325,T34	OUTPUT
intr_acq_threshold_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_rx_overflow_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_controller_halt_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_scl_interference_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_sda_interference_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_sda_unstable_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_cmd_complete_o	Yes	Yes	T33,T325,T34	Yes	T33,T325,T34	OUTPUT
intr_tx_stretch_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_tx_threshold_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_acq_stretch_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_unexp_stop_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_host_timeout_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2

	Total	Covered	Percent
Totals	54	48	88.89
Total Bits	350	326	93.14
Total Bits 0->1	175	163	93.14
Total Bits 1->0	175	163	93.14

Ports	54	48	88.89
Port Bits	350	326	93.14
Port Bits 0->1	175	163	93.14
Port Bits 1->0	175	163	93.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T35,T404,T36	Yes	T35,T404,T36	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T35,T404,T36	Yes	T35,T404,T36	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	INPUT
tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	INPUT
tl_i.a_valid	Yes	Yes	T35,T404,T36	Yes	T35,T404,T36	INPUT
tl_o.a_ready	Yes	Yes	T35,T404,T36	Yes	T35,T404,T36	OUTPUT
tl_o.d_error	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T35,T36,T325	Yes	T35,T36,T325	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T35,T404,T36	Yes	T35,T404,T36	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T35,T404,T36	Yes	T35,T404,T36	OUTPUT
tl_o.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T85,*T89,*T90	Yes	T84,T85,T91	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T35,*T404,*T36	Yes	T35,T404,T36	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T35,T404,T36	Yes	T35,T404,T36	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T68,T92,T181	Yes	T68,T92,T181	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T92,T93,T226	Yes	T92,T93,T226	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T92,T93,T226	Yes	T92,T93,T226	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T68,T92,T181	Yes	T68,T92,T181	OUTPUT
cio_scl_i	Yes	Yes	T35,T36,T10	Yes	T35,T36,T10	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T36,T10,T133	Yes	T36,T10,T133	OUTPUT
cio_sda_i	Yes	Yes	T35,T36,T10	Yes	T35,T36,T10	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T35,T36,T10	Yes	T35,T36,T10	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T36,T325,T133	Yes	T36,T325,T133	OUTPUT
intr_rx_threshold_o	Yes	Yes	T36,T325,T133	Yes	T36,T325,T133	OUTPUT
intr_acq_threshold_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_rx_overflow_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_controller_halt_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_scl_interference_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_sda_interference_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_sda_unstable_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_cmd_complete_o	Yes	Yes	T35,T36,T325	Yes	T35,T36,T325	OUTPUT
intr_tx_stretch_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_tx_threshold_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_acq_stretch_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_unexp_stop_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT
intr_host_timeout_o	Yes	Yes	T325,T326,T327	Yes	T325,T326,T327	OUTPUT

*Tests covering at least one bit in the range