Unified Coverage Report :: Module :: spi_host

Module : spi_host

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.21			97.21

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_spi_host_1.0/rtl/spi_host.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_spi_host0	96.59			96.59
tb.dut.top_earlgrey.u_spi_host1	98.77			98.77

---

Module Instance : tb.dut.top_earlgrey.u_spi_host0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59			96.59

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59			96.59

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_spi_host1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.77			98.77

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.77			98.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : spi_host

	Total	Covered	Percent
Totals	46	43	93.48
Total Bits	358	348	97.21
Total Bits 0->1	179	174	97.21
Total Bits 1->0	179	174	97.21

Ports	46	43	93.48
Port Bits	358	348	97.21
Port Bits 0->1	179	174	97.21
Port Bits 1->0	179	174	97.21

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T84,*T85,*T91	Yes	T84,T85,T91	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T7,*T404,*T68	Yes	T7,T404,T68	INPUT
tl_i.a_address[19:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T7,*T8,*T9	Yes	T7,T8,T9	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T84,*T85,*T91	Yes	T84,T85,T91	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T8,T215,T217	Yes	T8,T215,T217	INPUT
tl_i.a_valid	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	INPUT
tl_o.a_ready	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
tl_o.d_error	Yes	Yes	T84,T91,T89	Yes	T84,T91,T89	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
tl_o.d_sink	Yes	Yes	T84,T91,T89	Yes	T84,T85,T86	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T91,*T89,*T90	Yes	T84,T85,T91	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T91	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T7,*T8,*T9	Yes	T7,T8,T9	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T68,T92,T181	Yes	T68,T92,T181	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T92,T93,T226	Yes	T92,T93,T226	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T92,T93,T226	Yes	T92,T93,T226	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T68,T92,T181	Yes	T68,T92,T181	OUTPUT
cio_sck_o	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
cio_sck_en_o	Yes	Yes	T8,T9,T10	Yes	T7,T8,T9	OUTPUT
cio_csb_o	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
cio_csb_en_o	Yes	Yes	T8,T9,T10	Yes	T7,T8,T9	OUTPUT
cio_sd_o[3:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T7,T8,T9	Yes	T7,T8,T9	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T7,T8,T9	Yes	T25,T7,T8	INPUT
passthrough_i.s_en[0]	Yes	Yes	*T8,*T9,*T10	Yes	T8,T9,T10	INPUT
passthrough_i.s_en[3:1]	No	No		No		INPUT
passthrough_i.s[3:0]	Yes	Yes	T26,T8,T19	Yes	T26,T8,T19	INPUT
passthrough_i.csb_en	No	No		No		INPUT
passthrough_i.csb	Yes	Yes	T25,T4,T26	Yes	T25,T26,T8	INPUT
passthrough_i.sck_en	No	No		No		INPUT
passthrough_i.sck	Yes	Yes	T26,T8,T19	Yes	T26,T8,T19	INPUT
passthrough_i.passthrough_en	Yes	Yes	T8,T215,T217	Yes	T8,T9,T10	INPUT
passthrough_o.s[3:0]	Yes	Yes	T7,T8,T9	Yes	T25,T7,T8	OUTPUT
intr_error_o	Yes	Yes	T122,T178,T179	Yes	T122,T178,T179	OUTPUT
intr_spi_event_o	Yes	Yes	T122,T178,T179	Yes	T122,T178,T179	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host0

	Total	Covered	Percent
Totals	44	42	95.45
Total Bits	352	340	96.59
Total Bits 0->1	176	170	96.59
Total Bits 1->0	176	170	96.59

Ports	44	42	95.45
Port Bits	352	340	96.59
Port Bits 0->1	176	170	96.59
Port Bits 1->0	176	170	96.59

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T85,*T91,*T89	Yes	T85,T91,T89	INPUT
tl_i.a_address[19:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T8,*T9,*T404	Yes	T8,T9,T404	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T84,*T85,*T91	Yes	T84,T85,T91	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T84,T85,T89	Yes	T84,T85,T89	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T8,T215,T217	Yes	T8,T215,T217	INPUT
tl_i.a_valid	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	INPUT
tl_o.a_ready	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	OUTPUT
tl_o.d_error	Yes	Yes	T91,T89,T90	Yes	T91,T89,T90	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	OUTPUT
tl_o.d_sink	Yes	Yes	T84,T91,T89	Yes	T84,T85,T91	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T91,*T90,*T155	Yes	T84,T85,T91	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T8,*T9,*T404	Yes	T8,T9,T404	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T68,T92,T181	Yes	T68,T92,T181	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T92,T93,T226	Yes	T92,T93,T226	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T92,T93,T226	Yes	T92,T93,T226	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T68,T92,T181	Yes	T68,T92,T181	OUTPUT
cio_sck_o	Yes	Yes	T8,T9,T10	Yes	T8,T9,T10	OUTPUT
cio_sck_en_o	Yes	Yes	T8,T9,T10	Yes	T8,T9,T10	OUTPUT
cio_csb_o	Yes	Yes	T8,T9,T10	Yes	T8,T9,T10	OUTPUT
cio_csb_en_o	Yes	Yes	T8,T9,T10	Yes	T8,T9,T10	OUTPUT
cio_sd_o[3:0]	Yes	Yes	T8,T9,T10	Yes	T8,T9,T10	OUTPUT
cio_sd_en_o[0]	Yes	Yes	*T8,*T9,*T10	Yes	T8,T9,T10	OUTPUT
cio_sd_en_o[3:1]	No	No		No		OUTPUT
cio_sd_i[3:0]	Yes	Yes	T8,T9,T10	Yes	T25,T8,T9	INPUT
passthrough_i.s_en[0]	Yes	Yes	*T8,*T9,*T10	Yes	T8,T9,T10	INPUT
passthrough_i.s_en[3:1]	No	No		No		INPUT
passthrough_i.s[3:0]	Yes	Yes	T26,T8,T19	Yes	T26,T8,T19	INPUT
passthrough_i.csb_en[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off.
passthrough_i.csb	Yes	Yes	T25,T4,T26	Yes	T25,T26,T8	INPUT
passthrough_i.sck_en[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off.
passthrough_i.sck	Yes	Yes	T26,T8,T19	Yes	T26,T8,T19	INPUT
passthrough_i.passthrough_en	Yes	Yes	T8,T215,T217	Yes	T8,T9,T10	INPUT
passthrough_o.s[3:0]	Yes	Yes	T8,T9,T10	Yes	T25,T8,T9	OUTPUT
intr_error_o	Yes	Yes	T122,T178,T179	Yes	T122,T178,T179	OUTPUT
intr_spi_event_o	Yes	Yes	T122,T178,T179	Yes	T122,T178,T179	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host1

	Total	Covered	Percent
Totals	38	37	97.37
Total Bits	324	320	98.77
Total Bits 0->1	162	161	99.38
Total Bits 1->0	162	159	98.15

Ports	38	37	97.37
Port Bits	324	320	98.77
Port Bits 0->1	162	161	99.38
Port Bits 1->0	162	159	98.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T7,T404,T68	Yes	T7,T404,T68	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T7,T404,T68	Yes	T7,T404,T68	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T7,T404,T68	Yes	T7,T404,T68	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T7,T404,T68	Yes	T7,T404,T68	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T7,T404,T68	Yes	T7,T404,T68	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T7,T404,T68	Yes	T7,T404,T68	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T84,*T89,*T90	Yes	T84,T89,T90	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T7,*T404,*T68	Yes	T7,T404,T68	INPUT
tl_i.a_address[19:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T7,T404,T68	Yes	T7,T404,T68	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T7,*T404,*T68	Yes	T7,T404,T68	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T84,*T91,*T89	Yes	T84,T91,T89	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T84,T91,T89	Yes	T84,T91,T89	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T84,T91,T89	Yes	T84,T91,T89	INPUT
tl_i.a_valid	Yes	Yes	T7,T404,T68	Yes	T7,T404,T68	INPUT
tl_o.a_ready	Yes	Yes	T7,T404,T68	Yes	T7,T404,T68	OUTPUT
tl_o.d_error	Yes	Yes	T84,T91,T89	Yes	T84,T91,T89	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T7,T404,T122	Yes	T7,T404,T122	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T7,T404,T122	Yes	T7,T404,T68	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T7,T404,T122	Yes	T7,T404,T122	OUTPUT
tl_o.d_sink	Yes	Yes	T84,T91,T89	Yes	T84,T86,T91	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T89,*T90,*T155	Yes	T84,T91,T89	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T84,T86,T91	Yes	T84,T91,T89	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T7,*T404,*T122	Yes	T7,T404,T122	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T7,T404,T68	Yes	T7,T404,T68	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T68,T92,T93	Yes	T68,T92,T93	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T92,T93,T226	Yes	T92,T93,T226	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T92,T93,T226	Yes	T92,T93,T226	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T68,T92,T93	Yes	T68,T92,T93	OUTPUT
cio_sck_o	Yes	Yes	T7,T10,T50	Yes	T7,T10,T50	OUTPUT
cio_sck_en_o	Yes	Yes	T163,T398,T399	Yes	T7,T10,T50	OUTPUT
cio_csb_o	Yes	Yes	T7,T10,T50	Yes	T7,T10,T50	OUTPUT
cio_csb_en_o	Yes	Yes	T163,T398,T399	Yes	T7,T10,T50	OUTPUT
cio_sd_o[0]	Yes	Yes	*T7	Yes	T7	OUTPUT
cio_sd_o[1]	No	No		Yes	T10,T50,T51	OUTPUT
cio_sd_o[2]	No	No		No		OUTPUT
cio_sd_o[3]	No	No		Yes	T10,T50,T51	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T7,T10,T50	Yes	T7,T10,T50	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T7,T10,T50	Yes	T7,T10,T17	INPUT
passthrough_i.s_en[3:0]	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.s[3:0]	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.csb_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.csb	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.sck_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.sck	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.passthrough_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_o.s[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
intr_error_o	Yes	Yes	T122,T178,T179	Yes	T122,T178,T179	OUTPUT
intr_spi_event_o	Yes	Yes	T122,T178,T179	Yes	T122,T178,T179	OUTPUT

*Tests covering at least one bit in the range