Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	482982954	57858522	0	0
DataKnown_AKnownEnable	482982954	482878349	0	0
DepthKnown_A	482982954	482878349	0	0
RvalidKnown_A	482982954	482878349	0	0
WreadyKnown_A	482982954	482878349	0	0
gen_passthru_fifo.paramCheckPass	1007	1007	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	57858522	0	0
T1	90199	10906	0	0
T2	96900	10944	0	0
T3	57421	5274	0	0
T4	81721	11129	0	0
T7	91544	11141	0	0
T25	94967	10383	0	0
T46	65559	6918	0	0
T99	66193	6440	0	0
T100	42210	3485	0	0
T101	94759	11591	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	482878349	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	482878349	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	482878349	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	482878349	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         0/1     ==>      assign wready_o = rready_i;
49         0/1     ==>      assign full_o = rready_i;
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	482982954	43246005	0	0
DataKnown_AKnownEnable	482982954	482878349	0	0
DepthKnown_A	482982954	482878349	0	0
RvalidKnown_A	482982954	482878349	0	0
WreadyKnown_A	482982954	482878349	0	0
gen_passthru_fifo.paramCheckPass	1007	1007	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	43246005	0	0
T1	90199	8367	0	0
T2	96900	8514	0	0
T3	57421	3599	0	0
T4	81721	7485	0	0
T7	91544	8296	0	0
T25	94967	7694	0	0
T46	65559	4811	0	0
T99	66193	4765	0	0
T100	42210	1880	0	0
T101	94759	8852	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	482878349	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	482878349	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	482878349	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	482878349	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	482982954	40929004	0	0
DataKnown_AKnownEnable	482982954	482878349	0	0
DepthKnown_A	482982954	482878349	0	0
RvalidKnown_A	482982954	482878349	0	0
WreadyKnown_A	482982954	482878349	0	0
gen_passthru_fifo.paramCheckPass	1007	1007	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	40929004	0	0
T1	90199	7228	0	0
T2	96900	5383	0	0
T3	57421	2995	0	0
T4	81721	4858	0	0
T7	91544	5998	0	0
T25	94967	8076	0	0
T46	65559	3563	0	0
T99	66193	3843	0	0
T100	42210	461	0	0
T101	94759	8170	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	482878349	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	482878349	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	482878349	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	482878349	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T58 T88 T41 
49         1/1              assign full_o = rready_i;
           Tests:       T58 T88 T41 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	482982954	33950770	0	0
DataKnown_AKnownEnable	482982954	482878349	0	0
DepthKnown_A	482982954	482878349	0	0
RvalidKnown_A	482982954	482878349	0	0
WreadyKnown_A	482982954	482878349	0	0
gen_passthru_fifo.paramCheckPass	1007	1007	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	33950770	0	0
T1	90199	7053	0	0
T2	96900	5244	0	0
T3	57421	2882	0	0
T4	81721	4679	0	0
T7	91544	5819	0	0
T25	94967	7618	0	0
T46	65559	3435	0	0
T99	66193	3730	0	0
T100	42210	353	0	0
T101	94759	7574	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	482878349	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	482878349	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	482878349	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	482878349	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	540148186	93365	0	0
DataKnown_AKnownEnable	540148186	540028123	0	0
DepthKnown_A	540148186	540028123	0	0
RvalidKnown_A	540148186	540028123	0	0
WreadyKnown_A	540148186	540028123	0	0
gen_passthru_fifo.paramCheckPass	2913	2913	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	93365	0	0
T1	90199	24	0	0
T2	96900	13	0	0
T3	57421	13	0	0
T4	81721	24	0	0
T7	91544	22	0	0
T25	94967	208	0	0
T46	65559	13	0	0
T99	66193	13	0	0
T100	42210	8	0	0
T101	94759	34	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2913	2913	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	540148186	95589	0	0
DataKnown_AKnownEnable	540148186	540028123	0	0
DepthKnown_A	540148186	540028123	0	0
RvalidKnown_A	540148186	540028123	0	0
WreadyKnown_A	540148186	540028123	0	0
gen_passthru_fifo.paramCheckPass	2913	2913	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	95589	0	0
T1	90199	24	0	0
T2	96900	13	0	0
T3	57421	13	0	0
T4	81721	24	0	0
T7	91544	22	0	0
T25	94967	208	0	0
T46	65559	13	0	0
T99	66193	13	0	0
T100	42210	8	0	0
T101	94759	34	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2913	2913	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	540148186	51383	0	0
DataKnown_AKnownEnable	540148186	540028123	0	0
DepthKnown_A	540148186	540028123	0	0
RvalidKnown_A	540148186	540028123	0	0
WreadyKnown_A	540148186	540028123	0	0
gen_passthru_fifo.paramCheckPass	2913	2913	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	51383	0	0
T1	90199	23	0	0
T2	96900	12	0	0
T3	57421	12	0	0
T4	81721	21	0	0
T7	91544	19	0	0
T25	94967	205	0	0
T46	65559	12	0	0
T99	66193	12	0	0
T100	42210	8	0	0
T101	94759	33	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2913	2913	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	540148186	51383	0	0
DataKnown_AKnownEnable	540148186	540028123	0	0
DepthKnown_A	540148186	540028123	0	0
RvalidKnown_A	540148186	540028123	0	0
WreadyKnown_A	540148186	540028123	0	0
gen_passthru_fifo.paramCheckPass	2913	2913	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	51383	0	0
T1	90199	23	0	0
T2	96900	12	0	0
T3	57421	12	0	0
T4	81721	21	0	0
T7	91544	19	0	0
T25	94967	205	0	0
T46	65559	12	0	0
T99	66193	12	0	0
T100	42210	8	0	0
T101	94759	33	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2913	2913	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	540148186	41982	0	0
DataKnown_AKnownEnable	540148186	540028123	0	0
DepthKnown_A	540148186	540028123	0	0
RvalidKnown_A	540148186	540028123	0	0
WreadyKnown_A	540148186	540028123	0	0
gen_passthru_fifo.paramCheckPass	2913	2913	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	41982	0	0
T1	90199	1	0	0
T2	96900	1	0	0
T3	57421	1	0	0
T4	81721	3	0	0
T5	0	3	0	0
T7	91544	3	0	0
T25	94967	3	0	0
T46	65559	1	0	0
T99	66193	1	0	0
T100	42210	0	0	0
T101	94759	1	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2913	2913	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	540148186	44206	0	0
DataKnown_AKnownEnable	540148186	540028123	0	0
DepthKnown_A	540148186	540028123	0	0
RvalidKnown_A	540148186	540028123	0	0
WreadyKnown_A	540148186	540028123	0	0
gen_passthru_fifo.paramCheckPass	2913	2913	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	44206	0	0
T1	90199	1	0	0
T2	96900	1	0	0
T3	57421	1	0	0
T4	81721	3	0	0
T5	0	3	0	0
T7	91544	3	0	0
T25	94967	3	0	0
T46	65559	1	0	0
T99	66193	1	0	0
T100	42210	0	0	0
T101	94759	1	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540148186	540028123	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2913	2913	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0