Module Definition
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Module : tlul_adapter_host
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.09 91.11 75.79 89.44 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex 87.26 90.91 69.23 88.89 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex 90.91 91.30 82.35 90.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.26 90.91 69.23 88.89 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.90 90.48 72.22 88.89 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.27 94.12 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cmd_intg_gen 94.12 88.24 100.00
u_rsp_chk 93.33 100.00 80.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.91 91.30 82.35 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.79 95.35 81.82 90.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.27 94.12 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cmd_intg_gen 100.00 100.00 100.00
u_rsp_chk 93.33 100.00 80.00 100.00

Line Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Line Coverage for Module self-instances :
SCORELINE
90.91 91.30
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

Line No.TotalCoveredPercent
TOTAL232191.30
ALWAYS7133100.00
ALWAYS7955100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN9511100.00
CONT_ASSIGN9711100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12111100.00
ALWAYS1334375.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN150100.00
CONT_ASSIGN15411100.00
ALWAYS16900
ALWAYS17900


70                          always_ff @(posedge clk_i or negedge rst_ni) begin
71         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
72         1/1                  source_q <= '0;
           Tests:       T1 T2 T3 
73                            end else begin
74         1/1                  source_q <= source_d;
           Tests:       T1 T2 T3 
75                            end
76                          end
77                      
78                          always_comb begin
79         1/1                source_d = source_q;
           Tests:       T1 T2 T3 
80                      
81         1/1                if (req_i && gnt_o) begin
           Tests:       T1 T2 T3 
82         1/1                  if (source_q == MaxSource[ReqNumW-1:0]) begin
           Tests:       T1 T2 T3 
83         1/1                    source_d = '0;
           Tests:       T1 T2 T3 
84                              end else  begin
85         1/1                    source_d = source_q + ReqNumOne;
           Tests:       T1 T2 T3 
86                              end
87                            end
                        MISSING_ELSE
88                          end
89                      
90         1/1              assign tl_source = top_pkg::TL_AIW'(source_q);
           Tests:       T1 T2 T3 
91                        end
92                      
93                        // For TL-UL Get opcode all active bytes must have their mask bit set, so all reads get all tl_be
94                        // bits set. For writes the supplied be_i is used as the mask.
95         1/1            assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
           Tests:       T1 T2 T3 
96                      
97         1/1            assign tl_out = '{
           Tests:       T1 T2 T3 
98                          a_valid:   req_i,
99                          a_opcode:  (~we_i) ? Get           :
100                                    (&be_i) ? PutFullData   :
101                                              PutPartialData,
102                         a_param:   3'h0,
103                         a_size:    top_pkg::TL_SZW'(WordSize),
104                         a_mask:    tl_be,
105                         a_source:  tl_source,
106                         a_address: {addr_i[31:WordSize], {WordSize{1'b0}}},
107                         a_data:    wdata_i,
108                         a_user:    '{default: '0, data_intg: wdata_intg_i, instr_type: instr_type_i, rsvd: user_rsvd_i},
109                         d_ready:   1'b1
110                       };
111                     
112                       tlul_cmd_intg_gen #(.EnableDataIntgGen (EnableDataIntgGen)) u_cmd_intg_gen (
113                         .tl_i(tl_out),
114                         .tl_o(tl_o)
115                       );
116                     
117        1/1            assign gnt_o        = tl_i.a_ready;
           Tests:       T1 T2 T3 
118                     
119        1/1            assign valid_o      = tl_i.d_valid;
           Tests:       T1 T2 T3 
120        1/1            assign rdata_o      = tl_i.d_data;
           Tests:       T1 T2 T3 
121        1/1            assign rdata_intg_o = tl_i.d_user.data_intg;
           Tests:       T1 T2 T3 
122                     
123                       logic intg_err;
124                       tlul_rsp_intg_chk #(
125                         .EnableRspDataIntgCheck(EnableRspDataIntgCheck)
126                       ) u_rsp_chk (
127                         .tl_i,
128                         .err_o(intg_err)
129                       );
130                     
131                       logic intg_err_q;
132                       always_ff @(posedge clk_i or negedge rst_ni) begin
133        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
134        1/1                intg_err_q <= '0;
           Tests:       T1 T2 T3 
135        1/1              end else if (intg_err) begin
           Tests:       T1 T2 T3 
136        0/1     ==>        intg_err_q <= 1'b1;
137                         end
                        MISSING_ELSE
138                       end
139                     
140                       // err_o is transactional.  This allows the host to continue
141                       // debug without receiving an endless stream of errors.
142        1/1            assign err_o   = tl_i.d_error | intg_err;
           Tests:       T1 T2 T3 
143                     
144                       // intg_err_o is permanent once detected, and should be used
145                       // to trigger alerts
146        1/1            assign intg_err_o = intg_err_q | intg_err;
           Tests:       T1 T2 T3 
147                     
148                       // Addresses are assumed to be word-aligned, and the bottom bits are ignored
149                       logic unused_addr_bottom_bits;
150        0/1     ==>    assign unused_addr_bottom_bits = ^addr_i[WordSize-1:0];
151                     
152                       // Explicitly ignore unused fields of tl_i
153                       logic unused_tl_i_fields;
154        1/1            assign unused_tl_i_fields = ^{tl_i.d_opcode, tl_i.d_param,
           Tests:       T1 T2 T3 
155                                                     tl_i.d_size, tl_i.d_source, tl_i.d_sink,
156                                                     tl_i.d_user};
157                     
158                     `ifdef INC_ASSERT
159                       //VCS coverage off
160                       // pragma coverage off
161                       localparam int OutstandingReqCntW =
162                         (MAX_REQS == 2 ** $clog2(MAX_REQS)) ? $clog2(MAX_REQS) + 1 : $clog2(MAX_REQS);
163                       localparam logic [OutstandingReqCntW-1:0] OutstandingReqCntOne = OutstandingReqCntW'(1'b1);
164                     
165                       logic [OutstandingReqCntW-1:0] outstanding_reqs_q;
166                       logic [OutstandingReqCntW-1:0] outstanding_reqs_d;
167                     
168                       always_comb begin
169        unreachable      outstanding_reqs_d = outstanding_reqs_q;
170                     
171        unreachable      if ((req_i && gnt_o) && !valid_o) begin
172        unreachable        outstanding_reqs_d = outstanding_reqs_q + OutstandingReqCntOne;
173        unreachable      end else if (!(req_i && gnt_o) && valid_o) begin
174        unreachable        outstanding_reqs_d = outstanding_reqs_q - OutstandingReqCntOne;
175                         end
                   ==>  MISSING_ELSE
176                       end
177                     
178                       always_ff @(posedge clk_i or negedge rst_ni) begin
179        unreachable      if (!rst_ni) begin
180        unreachable        outstanding_reqs_q <= '0;
181                         end else begin
182        unreachable        outstanding_reqs_q <= outstanding_reqs_d;
Line Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Line Coverage for Module self-instances :
SCORELINE
87.26 90.91
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

Line No.TotalCoveredPercent
TOTAL222090.91
ALWAYS7133100.00
ALWAYS7955100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN9500
CONT_ASSIGN9711100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12111100.00
ALWAYS1334375.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN150100.00
CONT_ASSIGN15411100.00
ALWAYS16900
ALWAYS17900


70                          always_ff @(posedge clk_i or negedge rst_ni) begin
71         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
72         1/1                  source_q <= '0;
           Tests:       T1 T2 T3 
73                            end else begin
74         1/1                  source_q <= source_d;
           Tests:       T1 T2 T3 
75                            end
76                          end
77                      
78                          always_comb begin
79         1/1                source_d = source_q;
           Tests:       T1 T2 T3 
80                      
81         1/1                if (req_i && gnt_o) begin
           Tests:       T1 T2 T3 
82         1/1                  if (source_q == MaxSource[ReqNumW-1:0]) begin
           Tests:       T1 T2 T3 
83         1/1                    source_d = '0;
           Tests:       T1 T2 T3 
84                              end else  begin
85         1/1                    source_d = source_q + ReqNumOne;
           Tests:       T1 T2 T3 
86                              end
87                            end
                        MISSING_ELSE
88                          end
89                      
90         1/1              assign tl_source = top_pkg::TL_AIW'(source_q);
           Tests:       T1 T2 T3 
91                        end
92                      
93                        // For TL-UL Get opcode all active bytes must have their mask bit set, so all reads get all tl_be
94                        // bits set. For writes the supplied be_i is used as the mask.
95         unreachable    assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
96                      
97         1/1            assign tl_out = '{
           Tests:       T1 T2 T3 
98                          a_valid:   req_i,
99                          a_opcode:  (~we_i) ? Get           :
100                                    (&be_i) ? PutFullData   :
101                                              PutPartialData,
102                         a_param:   3'h0,
103                         a_size:    top_pkg::TL_SZW'(WordSize),
104                         a_mask:    tl_be,
105                         a_source:  tl_source,
106                         a_address: {addr_i[31:WordSize], {WordSize{1'b0}}},
107                         a_data:    wdata_i,
108                         a_user:    '{default: '0, data_intg: wdata_intg_i, instr_type: instr_type_i, rsvd: user_rsvd_i},
109                         d_ready:   1'b1
110                       };
111                     
112                       tlul_cmd_intg_gen #(.EnableDataIntgGen (EnableDataIntgGen)) u_cmd_intg_gen (
113                         .tl_i(tl_out),
114                         .tl_o(tl_o)
115                       );
116                     
117        1/1            assign gnt_o        = tl_i.a_ready;
           Tests:       T1 T2 T3 
118                     
119        1/1            assign valid_o      = tl_i.d_valid;
           Tests:       T1 T2 T3 
120        1/1            assign rdata_o      = tl_i.d_data;
           Tests:       T1 T2 T3 
121        1/1            assign rdata_intg_o = tl_i.d_user.data_intg;
           Tests:       T1 T2 T3 
122                     
123                       logic intg_err;
124                       tlul_rsp_intg_chk #(
125                         .EnableRspDataIntgCheck(EnableRspDataIntgCheck)
126                       ) u_rsp_chk (
127                         .tl_i,
128                         .err_o(intg_err)
129                       );
130                     
131                       logic intg_err_q;
132                       always_ff @(posedge clk_i or negedge rst_ni) begin
133        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
134        1/1                intg_err_q <= '0;
           Tests:       T1 T2 T3 
135        1/1              end else if (intg_err) begin
           Tests:       T1 T2 T3 
136        0/1     ==>        intg_err_q <= 1'b1;
137                         end
                        MISSING_ELSE
138                       end
139                     
140                       // err_o is transactional.  This allows the host to continue
141                       // debug without receiving an endless stream of errors.
142        1/1            assign err_o   = tl_i.d_error | intg_err;
           Tests:       T1 T2 T3 
143                     
144                       // intg_err_o is permanent once detected, and should be used
145                       // to trigger alerts
146        1/1            assign intg_err_o = intg_err_q | intg_err;
           Tests:       T1 T2 T3 
147                     
148                       // Addresses are assumed to be word-aligned, and the bottom bits are ignored
149                       logic unused_addr_bottom_bits;
150        0/1     ==>    assign unused_addr_bottom_bits = ^addr_i[WordSize-1:0];
151                     
152                       // Explicitly ignore unused fields of tl_i
153                       logic unused_tl_i_fields;
154        1/1            assign unused_tl_i_fields = ^{tl_i.d_opcode, tl_i.d_param,
           Tests:       T1 T2 T3 
155                                                     tl_i.d_size, tl_i.d_source, tl_i.d_sink,
156                                                     tl_i.d_user};
157                     
158                     `ifdef INC_ASSERT
159                       //VCS coverage off
160                       // pragma coverage off
161                       localparam int OutstandingReqCntW =
162                         (MAX_REQS == 2 ** $clog2(MAX_REQS)) ? $clog2(MAX_REQS) + 1 : $clog2(MAX_REQS);
163                       localparam logic [OutstandingReqCntW-1:0] OutstandingReqCntOne = OutstandingReqCntW'(1'b1);
164                     
165                       logic [OutstandingReqCntW-1:0] outstanding_reqs_q;
166                       logic [OutstandingReqCntW-1:0] outstanding_reqs_d;
167                     
168                       always_comb begin
169        unreachable      outstanding_reqs_d = outstanding_reqs_q;
170                     
171        unreachable      if ((req_i && gnt_o) && !valid_o) begin
172        unreachable        outstanding_reqs_d = outstanding_reqs_q + OutstandingReqCntOne;
173        unreachable      end else if (!(req_i && gnt_o) && valid_o) begin
174        unreachable        outstanding_reqs_d = outstanding_reqs_q - OutstandingReqCntOne;
175                         end
                   ==>  MISSING_ELSE
176                       end
177                     
178                       always_ff @(posedge clk_i or negedge rst_ni) begin
179        unreachable      if (!rst_ni) begin
180        unreachable        outstanding_reqs_q <= '0;
181                         end else begin
182        unreachable        outstanding_reqs_q <= outstanding_reqs_d;
Cond Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Cond Coverage for Module self-instances :
SCORECOND
87.26 69.23
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

TotalCoveredPercent
Conditions13969.23
Logical13969.23
Non-Logical00
Event00

 LINE       81
 EXPRESSION (req_i && gnt_o)
             --1--    --2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       82
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0])
            --------------------------------------------1-------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       95
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3 

 LINE       97
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3 

 LINE       97
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----
-1-StatusTests
0Unreachable
1Unreachable 

 LINE       142
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT75,T214,T231 

 LINE       146
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered
Cond Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Cond Coverage for Module self-instances :
SCORECOND
90.91 82.35
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

TotalCoveredPercent
Conditions171482.35
Logical171482.35
Non-Logical00
Event00

 LINE       81
 EXPRESSION (req_i && gnt_o)
             --1--    --2--
-1--2-StatusTests
01CoveredT58,T88,T41
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       82
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       95
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       97
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       97
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       142
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT73,T75,T232 

 LINE       146
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered
Branch Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
90.91 90.00
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

Line No.TotalCoveredPercent
Branches 10 9 90.00
TERNARY 95 2 2 100.00
IF 133 3 2 66.67
IF 71 2 2 100.00
IF 81 3 3 100.00 



95           assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
                                  -1-  
                                  ==>  
                                  ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



133            if (!rst_ni) begin
               -1-  
134              intg_err_q <= '0;
                 ==>
135            end else if (intg_err) begin
                        -2-  
136              intg_err_q <= 1'b1;
                 ==>
137            end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3 



71               if (!rst_ni) begin
                 -1-  
72                 source_q <= '0;
                   ==>
73               end else begin
74                 source_q <= source_d;
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



81               if (req_i && gnt_o) begin
                 -1-  
82                 if (source_q == MaxSource[ReqNumW-1:0]) begin
                   -2-  
83                   source_d = '0;
                     ==>
84                 end else  begin
85                   source_d = source_q + ReqNumOne;
                     ==>
86                 end
87               end
                 MISSING_ELSE
                 ==>

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3

Branch Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Branch Coverage for Module self-instances :
SCOREBRANCH
87.26 88.89
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

Line No.TotalCoveredPercent
Branches 9 8 88.89
TERNARY 95 1 1 100.00
IF 133 3 2 66.67
IF 71 2 2 100.00
IF 81 3 3 100.00 



95           assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
                                  -1-  
                                  ==>  
                                  ==> (Unreachable)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable 



133            if (!rst_ni) begin
               -1-  
134              intg_err_q <= '0;
                 ==>
135            end else if (intg_err) begin
                        -2-  
136              intg_err_q <= 1'b1;
                 ==>
137            end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3 



71               if (!rst_ni) begin
                 -1-  
72                 source_q <= '0;
                   ==>
73               end else begin
74                 source_q <= source_d;
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



81               if (req_i && gnt_o) begin
                 -1-  
82                 if (source_q == MaxSource[ReqNumW-1:0]) begin
                   -2-  
83                   source_d = '0;
                     ==>
84                 end else  begin
85                   source_d = source_q + ReqNumOne;
                     ==>
86                 end
87               end
                 MISSING_ELSE
                 ==>

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3

Assert Coverage for Module : tlul_adapter_host
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DontExceeedMaxReqs 965965908 98741274 0 0


DontExceeedMaxReqs
NameAttemptsReal SuccessesFailuresIncomplete
Total 965965908 98741274 0 0
T1 180398 18134 0 0
T2 193800 16327 0 0
T3 114842 8269 0 0
T4 163442 15987 0 0
T7 183088 17139 0 0
T25 189934 18459 0 0
T46 131118 10481 0 0
T99 132386 10283 0 0
T100 84420 3946 0 0
T101 189518 19761 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
Line No.TotalCoveredPercent
TOTAL222090.91
ALWAYS7133100.00
ALWAYS7955100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN9500
CONT_ASSIGN9711100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12111100.00
ALWAYS1334375.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN150100.00
CONT_ASSIGN15411100.00
ALWAYS16900
ALWAYS17900


70                          always_ff @(posedge clk_i or negedge rst_ni) begin
71         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
72         1/1                  source_q <= '0;
           Tests:       T1 T2 T3 
73                            end else begin
74         1/1                  source_q <= source_d;
           Tests:       T1 T2 T3 
75                            end
76                          end
77                      
78                          always_comb begin
79         1/1                source_d = source_q;
           Tests:       T1 T2 T3 
80                      
81         1/1                if (req_i && gnt_o) begin
           Tests:       T1 T2 T3 
82         1/1                  if (source_q == MaxSource[ReqNumW-1:0]) begin
           Tests:       T1 T2 T3 
83         1/1                    source_d = '0;
           Tests:       T1 T2 T3 
84                              end else  begin
85         1/1                    source_d = source_q + ReqNumOne;
           Tests:       T1 T2 T3 
86                              end
87                            end
                        MISSING_ELSE
88                          end
89                      
90         1/1              assign tl_source = top_pkg::TL_AIW'(source_q);
           Tests:       T1 T2 T3 
91                        end
92                      
93                        // For TL-UL Get opcode all active bytes must have their mask bit set, so all reads get all tl_be
94                        // bits set. For writes the supplied be_i is used as the mask.
95         unreachable    assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
96                      
97         1/1            assign tl_out = '{
           Tests:       T1 T2 T3 
98                          a_valid:   req_i,
99                          a_opcode:  (~we_i) ? Get           :
100                                    (&be_i) ? PutFullData   :
101                                              PutPartialData,
102                         a_param:   3'h0,
103                         a_size:    top_pkg::TL_SZW'(WordSize),
104                         a_mask:    tl_be,
105                         a_source:  tl_source,
106                         a_address: {addr_i[31:WordSize], {WordSize{1'b0}}},
107                         a_data:    wdata_i,
108                         a_user:    '{default: '0, data_intg: wdata_intg_i, instr_type: instr_type_i, rsvd: user_rsvd_i},
109                         d_ready:   1'b1
110                       };
111                     
112                       tlul_cmd_intg_gen #(.EnableDataIntgGen (EnableDataIntgGen)) u_cmd_intg_gen (
113                         .tl_i(tl_out),
114                         .tl_o(tl_o)
115                       );
116                     
117        1/1            assign gnt_o        = tl_i.a_ready;
           Tests:       T1 T2 T3 
118                     
119        1/1            assign valid_o      = tl_i.d_valid;
           Tests:       T1 T2 T3 
120        1/1            assign rdata_o      = tl_i.d_data;
           Tests:       T1 T2 T3 
121        1/1            assign rdata_intg_o = tl_i.d_user.data_intg;
           Tests:       T1 T2 T3 
122                     
123                       logic intg_err;
124                       tlul_rsp_intg_chk #(
125                         .EnableRspDataIntgCheck(EnableRspDataIntgCheck)
126                       ) u_rsp_chk (
127                         .tl_i,
128                         .err_o(intg_err)
129                       );
130                     
131                       logic intg_err_q;
132                       always_ff @(posedge clk_i or negedge rst_ni) begin
133        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
134        1/1                intg_err_q <= '0;
           Tests:       T1 T2 T3 
135        1/1              end else if (intg_err) begin
           Tests:       T1 T2 T3 
136        0/1     ==>        intg_err_q <= 1'b1;
137                         end
                        MISSING_ELSE
138                       end
139                     
140                       // err_o is transactional.  This allows the host to continue
141                       // debug without receiving an endless stream of errors.
142        1/1            assign err_o   = tl_i.d_error | intg_err;
           Tests:       T1 T2 T3 
143                     
144                       // intg_err_o is permanent once detected, and should be used
145                       // to trigger alerts
146        1/1            assign intg_err_o = intg_err_q | intg_err;
           Tests:       T1 T2 T3 
147                     
148                       // Addresses are assumed to be word-aligned, and the bottom bits are ignored
149                       logic unused_addr_bottom_bits;
150        0/1     ==>    assign unused_addr_bottom_bits = ^addr_i[WordSize-1:0];
151                     
152                       // Explicitly ignore unused fields of tl_i
153                       logic unused_tl_i_fields;
154        1/1            assign unused_tl_i_fields = ^{tl_i.d_opcode, tl_i.d_param,
           Tests:       T1 T2 T3 
155                                                     tl_i.d_size, tl_i.d_source, tl_i.d_sink,
156                                                     tl_i.d_user};
157                     
158                     `ifdef INC_ASSERT
159                       //VCS coverage off
160                       // pragma coverage off
161                       localparam int OutstandingReqCntW =
162                         (MAX_REQS == 2 ** $clog2(MAX_REQS)) ? $clog2(MAX_REQS) + 1 : $clog2(MAX_REQS);
163                       localparam logic [OutstandingReqCntW-1:0] OutstandingReqCntOne = OutstandingReqCntW'(1'b1);
164                     
165                       logic [OutstandingReqCntW-1:0] outstanding_reqs_q;
166                       logic [OutstandingReqCntW-1:0] outstanding_reqs_d;
167                     
168                       always_comb begin
169        unreachable      outstanding_reqs_d = outstanding_reqs_q;
170                     
171        unreachable      if ((req_i && gnt_o) && !valid_o) begin
172        unreachable        outstanding_reqs_d = outstanding_reqs_q + OutstandingReqCntOne;
173        unreachable      end else if (!(req_i && gnt_o) && valid_o) begin
174        unreachable        outstanding_reqs_d = outstanding_reqs_q - OutstandingReqCntOne;
175                         end
                   ==>  MISSING_ELSE
176                       end
177                     
178                       always_ff @(posedge clk_i or negedge rst_ni) begin
179        unreachable      if (!rst_ni) begin
180        unreachable        outstanding_reqs_q <= '0;
181                         end else begin
182        unreachable        outstanding_reqs_q <= outstanding_reqs_d;
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
TotalCoveredPercent
Conditions13969.23
Logical13969.23
Non-Logical00
Event00

 LINE       81
 EXPRESSION (req_i && gnt_o)
             --1--    --2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       82
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0])
            --------------------------------------------1-------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       95
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3 

 LINE       97
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3 

 LINE       97
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----
-1-StatusTests
0Unreachable
1Unreachable 

 LINE       142
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT75,T214,T231 

 LINE       146
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
Line No.TotalCoveredPercent
Branches 9 8 88.89
TERNARY 95 1 1 100.00
IF 133 3 2 66.67
IF 71 2 2 100.00
IF 81 3 3 100.00 



95           assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
                                  -1-  
                                  ==>  
                                  ==> (Unreachable)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable 



133            if (!rst_ni) begin
               -1-  
134              intg_err_q <= '0;
                 ==>
135            end else if (intg_err) begin
                        -2-  
136              intg_err_q <= 1'b1;
                 ==>
137            end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3 



71               if (!rst_ni) begin
                 -1-  
72                 source_q <= '0;
                   ==>
73               end else begin
74                 source_q <= source_d;
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



81               if (req_i && gnt_o) begin
                 -1-  
82                 if (source_q == MaxSource[ReqNumW-1:0]) begin
                   -2-  
83                   source_d = '0;
                     ==>
84                 end else  begin
85                   source_d = source_q + ReqNumOne;
                     ==>
86                 end
87               end
                 MISSING_ELSE
                 ==>

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DontExceeedMaxReqs 482982954 57858522 0 0


DontExceeedMaxReqs
NameAttemptsReal SuccessesFailuresIncomplete
Total 482982954 57858522 0 0
T1 90199 10906 0 0
T2 96900 10944 0 0
T3 57421 5274 0 0
T4 81721 11129 0 0
T7 91544 11141 0 0
T25 94967 10383 0 0
T46 65559 6918 0 0
T99 66193 6440 0 0
T100 42210 3485 0 0
T101 94759 11591 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
Line No.TotalCoveredPercent
TOTAL232191.30
ALWAYS7133100.00
ALWAYS7955100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN9511100.00
CONT_ASSIGN9711100.00
CONT_ASSIGN11711100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12111100.00
ALWAYS1334375.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN150100.00
CONT_ASSIGN15411100.00
ALWAYS16900
ALWAYS17900


70                          always_ff @(posedge clk_i or negedge rst_ni) begin
71         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
72         1/1                  source_q <= '0;
           Tests:       T1 T2 T3 
73                            end else begin
74         1/1                  source_q <= source_d;
           Tests:       T1 T2 T3 
75                            end
76                          end
77                      
78                          always_comb begin
79         1/1                source_d = source_q;
           Tests:       T1 T2 T3 
80                      
81         1/1                if (req_i && gnt_o) begin
           Tests:       T1 T2 T3 
82         1/1                  if (source_q == MaxSource[ReqNumW-1:0]) begin
           Tests:       T1 T2 T3 
83         1/1                    source_d = '0;
           Tests:       T1 T2 T3 
84                              end else  begin
85         1/1                    source_d = source_q + ReqNumOne;
           Tests:       T1 T2 T3 
86                              end
87                            end
                        MISSING_ELSE
88                          end
89                      
90         1/1              assign tl_source = top_pkg::TL_AIW'(source_q);
           Tests:       T1 T2 T3 
91                        end
92                      
93                        // For TL-UL Get opcode all active bytes must have their mask bit set, so all reads get all tl_be
94                        // bits set. For writes the supplied be_i is used as the mask.
95         1/1            assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
           Tests:       T1 T2 T3 
96                      
97         1/1            assign tl_out = '{
           Tests:       T1 T2 T3 
98                          a_valid:   req_i,
99                          a_opcode:  (~we_i) ? Get           :
100                                    (&be_i) ? PutFullData   :
101                                              PutPartialData,
102                         a_param:   3'h0,
103                         a_size:    top_pkg::TL_SZW'(WordSize),
104                         a_mask:    tl_be,
105                         a_source:  tl_source,
106                         a_address: {addr_i[31:WordSize], {WordSize{1'b0}}},
107                         a_data:    wdata_i,
108                         a_user:    '{default: '0, data_intg: wdata_intg_i, instr_type: instr_type_i, rsvd: user_rsvd_i},
109                         d_ready:   1'b1
110                       };
111                     
112                       tlul_cmd_intg_gen #(.EnableDataIntgGen (EnableDataIntgGen)) u_cmd_intg_gen (
113                         .tl_i(tl_out),
114                         .tl_o(tl_o)
115                       );
116                     
117        1/1            assign gnt_o        = tl_i.a_ready;
           Tests:       T1 T2 T3 
118                     
119        1/1            assign valid_o      = tl_i.d_valid;
           Tests:       T1 T2 T3 
120        1/1            assign rdata_o      = tl_i.d_data;
           Tests:       T1 T2 T3 
121        1/1            assign rdata_intg_o = tl_i.d_user.data_intg;
           Tests:       T1 T2 T3 
122                     
123                       logic intg_err;
124                       tlul_rsp_intg_chk #(
125                         .EnableRspDataIntgCheck(EnableRspDataIntgCheck)
126                       ) u_rsp_chk (
127                         .tl_i,
128                         .err_o(intg_err)
129                       );
130                     
131                       logic intg_err_q;
132                       always_ff @(posedge clk_i or negedge rst_ni) begin
133        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
134        1/1                intg_err_q <= '0;
           Tests:       T1 T2 T3 
135        1/1              end else if (intg_err) begin
           Tests:       T1 T2 T3 
136        0/1     ==>        intg_err_q <= 1'b1;
137                         end
                        MISSING_ELSE
138                       end
139                     
140                       // err_o is transactional.  This allows the host to continue
141                       // debug without receiving an endless stream of errors.
142        1/1            assign err_o   = tl_i.d_error | intg_err;
           Tests:       T1 T2 T3 
143                     
144                       // intg_err_o is permanent once detected, and should be used
145                       // to trigger alerts
146        1/1            assign intg_err_o = intg_err_q | intg_err;
           Tests:       T1 T2 T3 
147                     
148                       // Addresses are assumed to be word-aligned, and the bottom bits are ignored
149                       logic unused_addr_bottom_bits;
150        0/1     ==>    assign unused_addr_bottom_bits = ^addr_i[WordSize-1:0];
151                     
152                       // Explicitly ignore unused fields of tl_i
153                       logic unused_tl_i_fields;
154        1/1            assign unused_tl_i_fields = ^{tl_i.d_opcode, tl_i.d_param,
           Tests:       T1 T2 T3 
155                                                     tl_i.d_size, tl_i.d_source, tl_i.d_sink,
156                                                     tl_i.d_user};
157                     
158                     `ifdef INC_ASSERT
159                       //VCS coverage off
160                       // pragma coverage off
161                       localparam int OutstandingReqCntW =
162                         (MAX_REQS == 2 ** $clog2(MAX_REQS)) ? $clog2(MAX_REQS) + 1 : $clog2(MAX_REQS);
163                       localparam logic [OutstandingReqCntW-1:0] OutstandingReqCntOne = OutstandingReqCntW'(1'b1);
164                     
165                       logic [OutstandingReqCntW-1:0] outstanding_reqs_q;
166                       logic [OutstandingReqCntW-1:0] outstanding_reqs_d;
167                     
168                       always_comb begin
169        unreachable      outstanding_reqs_d = outstanding_reqs_q;
170                     
171        unreachable      if ((req_i && gnt_o) && !valid_o) begin
172        unreachable        outstanding_reqs_d = outstanding_reqs_q + OutstandingReqCntOne;
173        unreachable      end else if (!(req_i && gnt_o) && valid_o) begin
174        unreachable        outstanding_reqs_d = outstanding_reqs_q - OutstandingReqCntOne;
175                         end
                   ==>  MISSING_ELSE
176                       end
177                     
178                       always_ff @(posedge clk_i or negedge rst_ni) begin
179        unreachable      if (!rst_ni) begin
180        unreachable        outstanding_reqs_q <= '0;
181                         end else begin
182        unreachable        outstanding_reqs_q <= outstanding_reqs_d;
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
TotalCoveredPercent
Conditions171482.35
Logical171482.35
Non-Logical00
Event00

 LINE       81
 EXPRESSION (req_i && gnt_o)
             --1--    --2--
-1--2-StatusTests
01CoveredT58,T88,T41
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       82
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       95
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       97
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       97
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       142
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT73,T75,T232 

 LINE       146
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
Line No.TotalCoveredPercent
Branches 10 9 90.00
TERNARY 95 2 2 100.00
IF 133 3 2 66.67
IF 71 2 2 100.00
IF 81 3 3 100.00 



95           assign tl_be = ~we_i ? {top_pkg::TL_DBW{1'b1}} : be_i;
                                  -1-  
                                  ==>  
                                  ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



133            if (!rst_ni) begin
               -1-  
134              intg_err_q <= '0;
                 ==>
135            end else if (intg_err) begin
                        -2-  
136              intg_err_q <= 1'b1;
                 ==>
137            end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3 



71               if (!rst_ni) begin
                 -1-  
72                 source_q <= '0;
                   ==>
73               end else begin
74                 source_q <= source_d;
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



81               if (req_i && gnt_o) begin
                 -1-  
82                 if (source_q == MaxSource[ReqNumW-1:0]) begin
                   -2-  
83                   source_d = '0;
                     ==>
84                 end else  begin
85                   source_d = source_q + ReqNumOne;
                     ==>
86                 end
87               end
                 MISSING_ELSE
                 ==>

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DontExceeedMaxReqs 482982954 40882752 0 0


DontExceeedMaxReqs
NameAttemptsReal SuccessesFailuresIncomplete
Total 482982954 40882752 0 0
T1 90199 7228 0 0
T2 96900 5383 0 0
T3 57421 2995 0 0
T4 81721 4858 0 0
T7 91544 5998 0 0
T25 94967 8076 0 0
T46 65559 3563 0 0
T99 66193 3843 0 0
T100 42210 461 0 0
T101 94759 8170 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%