Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : pattgen
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_pattgen_0.1/rtl/pattgen.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pattgen 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pattgen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 92.47 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : pattgen
TotalCoveredPercent
Totals 35 35 100.00
Total Bits 300 300 100.00
Total Bits 0->1 150 150 100.00
Total Bits 1->0 150 150 100.00

Ports 35 35 100.00
Port Bits 300 300 100.00
Port Bits 0->1 150 150 100.00
Port Bits 1->0 150 150 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T59,T60,T72 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T5,T122,T10 Yes T5,T122,T10 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T5,T122,T10 Yes T5,T122,T10 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[5:0] Yes Yes *T84,*T85,*T86 Yes T84,T85,T86 INPUT
tl_i.a_address[16:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19:17] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T87,*T58,*T88 Yes T87,T58,T88 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T84,T85,T86 Yes T84,T85,T86 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T58,T88,T41 Yes T58,T88,T41 INPUT
tl_i.a_valid Yes Yes T5,T68,T122 Yes T5,T68,T122 INPUT
tl_o.a_ready Yes Yes T5,T68,T122 Yes T5,T68,T122 OUTPUT
tl_o.d_error Yes Yes T84,T85,T91 Yes T84,T85,T91 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T5,T122,T10 Yes T5,T122,T10 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T5,T122,T10 Yes T5,T68,T122 OUTPUT
tl_o.d_data[31:0] Yes Yes T5,T122,T10 Yes T5,T68,T122 OUTPUT
tl_o.d_sink Yes Yes T84,T85,T91 Yes T84,T91,T89 OUTPUT
tl_o.d_source[5:0] Yes Yes *T41,T91,T89 Yes T41,T84,T85 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T84,T91,T89 Yes T84,T85,T91 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T5,*T122,*T10 Yes T5,T122,T10 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T5,T68,T122 Yes T5,T68,T122 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T68,T92,T93 Yes T68,T92,T93 INPUT
alert_rx_i[0].ping_n Yes Yes T92,T93,T52 Yes T92,T93,T52 INPUT
alert_rx_i[0].ping_p Yes Yes T92,T93,T52 Yes T92,T93,T52 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T68,T92,T93 Yes T68,T92,T93 OUTPUT
cio_pda0_tx_o Yes Yes T10,T41,T50 Yes T10,T41,T50 OUTPUT
cio_pcl0_tx_o Yes Yes T10,T50,T51 Yes T10,T50,T51 OUTPUT
cio_pda1_tx_o Yes Yes T5,T10,T130 Yes T5,T10,T130 OUTPUT
cio_pcl1_tx_o Yes Yes T5,T10,T130 Yes T5,T10,T130 OUTPUT
cio_pda0_tx_en_o Unreachable Unreachable Unreachable OUTPUT
cio_pcl0_tx_en_o Unreachable Unreachable Unreachable OUTPUT
cio_pda1_tx_en_o Unreachable Unreachable Unreachable OUTPUT
cio_pcl1_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_done_ch0_o Yes Yes T122,T178,T179 Yes T122,T178,T179 OUTPUT
intr_done_ch1_o Yes Yes T5,T122,T130 Yes T5,T122,T130 OUTPUT

*Tests covering at least one bit in the range