Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T126,T124,T37	Yes	T126,T124,T37	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T126,T124,T37	Yes	T126,T124,T37	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	INPUT
tl_i.a_valid	Yes	Yes	T126,T124,T37	Yes	T126,T124,T37	INPUT
tl_o.a_ready	Yes	Yes	T126,T124,T37	Yes	T126,T124,T37	OUTPUT
tl_o.d_error	Yes	Yes	T84,T85,T91	Yes	T84,T85,T86	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T126,T124,T37	Yes	T126,T124,T37	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T126,T124,T37	Yes	T126,T124,T37	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T126,T124,T37	Yes	T126,T124,T37	OUTPUT
tl_o.d_sink	Yes	Yes	T84,T85,T86	Yes	T84,T85,T91	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T58,*T23,*T268	Yes	T58,T23,T268	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T86	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T126,*T124,*T37	Yes	T126,T124,T37	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T126,T124,T37	Yes	T126,T124,T37	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T68,T92,T181	Yes	T68,T92,T181	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T92,T181,T93	Yes	T92,T181,T93	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T92,T181,T93	Yes	T92,T181,T93	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T68,T92,T181	Yes	T68,T92,T181	OUTPUT
cio_rx_i	Yes	Yes	T25,T7,T72	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T126,T124,T37	Yes	T126,T124,T37	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T126,T124,T37	Yes	T126,T124,T37	OUTPUT
intr_tx_empty_o	Yes	Yes	T126,T124,T37	Yes	T126,T124,T37	OUTPUT
intr_rx_watermark_o	Yes	Yes	T126,T124,T37	Yes	T126,T124,T37	OUTPUT
intr_tx_done_o	Yes	Yes	T126,T124,T37	Yes	T126,T124,T37	OUTPUT
intr_rx_overflow_o	Yes	Yes	T126,T124,T37	Yes	T126,T124,T37	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T319,T323,T324	Yes	T319,T323,T324	OUTPUT
intr_rx_break_err_o	Yes	Yes	T319,T323,T324	Yes	T319,T323,T324	OUTPUT
intr_rx_timeout_o	Yes	Yes	T319,T323,T324	Yes	T319,T323,T324	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T319,T323,T324	Yes	T319,T323,T324	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T124,T125,T213	Yes	T124,T125,T213	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T124,T125,T213	Yes	T124,T125,T213	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	INPUT
tl_i.a_valid	Yes	Yes	T124,T68,T125	Yes	T124,T68,T125	INPUT
tl_o.a_ready	Yes	Yes	T124,T68,T125	Yes	T124,T68,T125	OUTPUT
tl_o.d_error	Yes	Yes	T84,T91,T89	Yes	T84,T85,T91	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T124,T125,T319	Yes	T124,T125,T319	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T124,T125,T181	Yes	T124,T68,T125	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T124,T125,T181	Yes	T124,T68,T125	OUTPUT
tl_o.d_sink	Yes	Yes	T84,T91,T89	Yes	T84,T91,T89	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T58,*T23,*T268	Yes	T58,T23,T268	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T84,T91,T90	Yes	T84,T85,T91	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T124,*T125,*T319	Yes	T124,T125,T319	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T124,T68,T125	Yes	T124,T68,T125	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T68,T92,T181	Yes	T68,T92,T181	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T92,T181,T93	Yes	T92,T181,T93	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T92,T181,T93	Yes	T92,T181,T93	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T68,T92,T181	Yes	T68,T92,T181	OUTPUT
cio_rx_i	Yes	Yes	T25,T72,T73	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T124,T125,T58	Yes	T124,T125,T58	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T124,T125,T319	Yes	T124,T125,T319	OUTPUT
intr_tx_empty_o	Yes	Yes	T124,T125,T319	Yes	T124,T125,T319	OUTPUT
intr_rx_watermark_o	Yes	Yes	T124,T125,T319	Yes	T124,T125,T319	OUTPUT
intr_tx_done_o	Yes	Yes	T124,T125,T319	Yes	T124,T125,T319	OUTPUT
intr_rx_overflow_o	Yes	Yes	T124,T125,T319	Yes	T124,T125,T319	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T319,T323,T324	Yes	T319,T323,T324	OUTPUT
intr_rx_break_err_o	Yes	Yes	T319,T323,T324	Yes	T319,T323,T324	OUTPUT
intr_rx_timeout_o	Yes	Yes	T319,T323,T324	Yes	T319,T323,T324	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T319,T323,T324	Yes	T319,T323,T324	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T126,T127,T128	Yes	T126,T127,T128	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T126,T127,T128	Yes	T126,T127,T128	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	INPUT
tl_i.a_valid	Yes	Yes	T126,T127,T68	Yes	T126,T127,T68	INPUT
tl_o.a_ready	Yes	Yes	T126,T127,T68	Yes	T126,T127,T68	OUTPUT
tl_o.d_error	Yes	Yes	T84,T85,T89	Yes	T84,T86,T89	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T126,T127,T128	Yes	T126,T127,T128	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T126,T127,T128	Yes	T126,T127,T68	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T126,T127,T128	Yes	T126,T127,T68	OUTPUT
tl_o.d_sink	Yes	Yes	T84,T85,T86	Yes	T84,T85,T91	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T58,*T41,*T89	Yes	T58,T41,T85	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T86	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T126,*T127,*T128	Yes	T126,T127,T128	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T126,T127,T68	Yes	T126,T127,T68	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T68,T92,T181	Yes	T68,T92,T181	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T92,T93,T94	Yes	T92,T93,T180	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T92,T93,T180	Yes	T92,T93,T94	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T68,T92,T181	Yes	T68,T92,T181	OUTPUT
cio_rx_i	Yes	Yes	T7,T126,T127	Yes	T25,T7,T126	INPUT
cio_tx_o	Yes	Yes	T126,T127,T128	Yes	T126,T127,T128	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T126,T127,T128	Yes	T126,T127,T128	OUTPUT
intr_tx_empty_o	Yes	Yes	T126,T127,T128	Yes	T126,T127,T128	OUTPUT
intr_rx_watermark_o	Yes	Yes	T126,T127,T128	Yes	T126,T127,T128	OUTPUT
intr_tx_done_o	Yes	Yes	T126,T127,T128	Yes	T126,T127,T128	OUTPUT
intr_rx_overflow_o	Yes	Yes	T126,T127,T128	Yes	T126,T127,T128	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T319,T323,T324	Yes	T319,T323,T324	OUTPUT
intr_rx_break_err_o	Yes	Yes	T319,T323,T324	Yes	T319,T323,T324	OUTPUT
intr_rx_timeout_o	Yes	Yes	T319,T323,T324	Yes	T319,T323,T324	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T319,T323,T324	Yes	T319,T323,T324	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T37,T319,T58	Yes	T37,T319,T58	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T37,T319,T58	Yes	T37,T319,T58	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	INPUT
tl_i.a_valid	Yes	Yes	T37,T68,T181	Yes	T37,T68,T181	INPUT
tl_o.a_ready	Yes	Yes	T37,T68,T181	Yes	T37,T68,T181	OUTPUT
tl_o.d_error	Yes	Yes	T84,T85,T89	Yes	T85,T89,T90	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T37,T319,T58	Yes	T37,T319,T58	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T37,T181,T319	Yes	T37,T68,T181	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T37,T181,T319	Yes	T37,T68,T181	OUTPUT
tl_o.d_sink	Yes	Yes	T84,T85,T91	Yes	T85,T91,T89	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T58,*T41,*T89	Yes	T58,T41,T85	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T85,T89,T90	Yes	T85,T89,T90	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T37,*T319,*T58	Yes	T37,T319,T58	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T37,T68,T181	Yes	T37,T68,T181	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T68,T92,T181	Yes	T68,T92,T181	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T92,T93,T94	Yes	T92,T93,T94	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T68,T92,T181	Yes	T68,T92,T181	OUTPUT
cio_rx_i	Yes	Yes	T37,T38,T129	Yes	T37,T38,T129	INPUT
cio_tx_o	Yes	Yes	T37,T38,T129	Yes	T37,T38,T129	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T37,T319,T38	Yes	T37,T319,T38	OUTPUT
intr_tx_empty_o	Yes	Yes	T37,T319,T38	Yes	T37,T319,T38	OUTPUT
intr_rx_watermark_o	Yes	Yes	T37,T319,T38	Yes	T37,T319,T38	OUTPUT
intr_tx_done_o	Yes	Yes	T37,T319,T38	Yes	T37,T319,T38	OUTPUT
intr_rx_overflow_o	Yes	Yes	T37,T319,T38	Yes	T37,T319,T38	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T319,T323,T324	Yes	T319,T323,T324	OUTPUT
intr_rx_break_err_o	Yes	Yes	T319,T323,T324	Yes	T319,T323,T324	OUTPUT
intr_rx_timeout_o	Yes	Yes	T319,T323,T324	Yes	T319,T323,T324	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T319,T323,T324	Yes	T319,T323,T324	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T39,T319,T58	Yes	T39,T319,T58	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T39,T319,T58	Yes	T39,T319,T58	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	INPUT
tl_i.a_valid	Yes	Yes	T39,T68,T181	Yes	T39,T68,T181	INPUT
tl_o.a_ready	Yes	Yes	T39,T68,T181	Yes	T39,T68,T181	OUTPUT
tl_o.d_error	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T39,T319,T58	Yes	T39,T319,T58	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T39,T181,T319	Yes	T39,T68,T181	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T39,T181,T319	Yes	T39,T68,T181	OUTPUT
tl_o.d_sink	Yes	Yes	T84,T85,T89	Yes	T84,T85,T91	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T58,*T41,*T89	Yes	T58,T41,T84	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T84,T89,T90	Yes	T84,T85,T91	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T39,*T319,*T58	Yes	T39,T319,T58	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T39,T68,T181	Yes	T39,T68,T181	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T68,T92,T181	Yes	T68,T92,T181	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T92,T93,T94	Yes	T92,T93,T180	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T92,T93,T180	Yes	T92,T93,T94	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T68,T92,T181	Yes	T68,T92,T181	OUTPUT
cio_rx_i	Yes	Yes	T39,T40,T349	Yes	T39,T40,T349	INPUT
cio_tx_o	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T39,T319,T58	Yes	T39,T319,T58	OUTPUT
intr_tx_empty_o	Yes	Yes	T39,T319,T58	Yes	T39,T319,T58	OUTPUT
intr_rx_watermark_o	Yes	Yes	T39,T319,T40	Yes	T39,T319,T40	OUTPUT
intr_tx_done_o	Yes	Yes	T39,T319,T40	Yes	T39,T319,T40	OUTPUT
intr_rx_overflow_o	Yes	Yes	T39,T319,T40	Yes	T39,T319,T40	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T319,T323,T324	Yes	T319,T323,T324	OUTPUT
intr_rx_break_err_o	Yes	Yes	T319,T323,T324	Yes	T319,T323,T324	OUTPUT
intr_rx_timeout_o	Yes	Yes	T319,T323,T324	Yes	T319,T323,T324	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T319,T323,T324	Yes	T319,T323,T324	OUTPUT

*Tests covering at least one bit in the range