Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T85,T86,T89	Yes	T84,T85,T86	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T86,T89,T155	Yes	T84,T86,T89	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T75,T214,T231	Yes	T75,T214,T231	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T73,T75,T214	Yes	T73,T75,T214	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T88,T220,T86	Yes	T88,T220,T86	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T88,T220,T84	Yes	T88,T220,T84	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T73,T75,T232	Yes	T73,T75,T232	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T72,T73,T74	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T61,T62,T440	Yes	T61,T62,T440	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T72,T73,T74	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T61,T62,T440	Yes	T61,T62,T440	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T72,T73,T74	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T61,T62,T440	Yes	T61,T62,T440	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T61,T62,T440	Yes	T61,T62,T440	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T61,T62,T440	Yes	T61,T62,T440	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T61,T62,T440	Yes	T61,T62,T440	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T61,*T62,*T440	Yes	T61,T62,T440	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T61,T62,T440	Yes	T61,T62,T440	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T84,T85,T89	Yes	T84,T85,T89	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T85,T91,T89	Yes	T85,T91,T89	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T84,T85,T89	Yes	T84,T85,T89	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T84,T85,*T91	Yes	T84,T85,T91	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T85,T91,T89	Yes	T85,T91,T89	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T85,T86,T89	Yes	T84,T85,T86	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T85,T89,T90	Yes	T85,T89,T90	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T85,T91,T89	Yes	T84,T85,T89	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T85,T89,T90	Yes	T84,T85,T89	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T84,T85,T89	Yes	T84,T85,T89	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T84,T85,T89	Yes	T84,T85,T89	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T85,T89,T155	Yes	T84,T85,T91	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T84,T85,T89	Yes	T84,T85,T91	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T84,*T85,*T89	Yes	T85,T89,T90	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T87,T23,T268	Yes	T87,T23,T268	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T87,T23,T268	Yes	T87,T23,T268	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T87,T23,T268	Yes	T87,T23,T268	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T87,T23,T268	Yes	T87,T23,T268	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T87,T23,T268	Yes	T87,T23,T268	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T87,*T23,*T268	Yes	T87,T23,T268	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T87,T23,T268	Yes	T87,T23,T268	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T72,T73,T74	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T87,T23,T268	Yes	T87,T23,T268	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T87,T23,T268	Yes	T87,T23,T268	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T72,T73,T74	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T87,*T23,*T268	Yes	T87,T23,T268	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T72,T73,T74	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T87,T23,T268	Yes	T87,T23,T268	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T100,T194,T61	Yes	T100,T194,T61	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T194,T418,T88	Yes	T194,T418,T88	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T68,T69,T262	Yes	T68,T69,T262	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T68,T419,T277	Yes	T68,T419,T277	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T68,T419,T277	Yes	T68,T419,T277	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T68,T69,T262	Yes	T68,T69,T262	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T68,T419,T277	Yes	T68,T419,T277	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T85,T91,T89	Yes	T85,T91,T89	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T84,T85,T89	Yes	T84,T85,T89	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T68,T419,T277	Yes	T68,T419,T277	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T68,T419,T277	Yes	T68,T419,T277	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T84,T85,T89	Yes	T84,T85,T89	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T419,T277,T420	Yes	T419,T277,T420	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T84,T85,T91	Yes	T68,T69,T262	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T419,T277,T420	Yes	T68,T419,T277	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T85,T89,T90	Yes	T84,T85,T91	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T85,T91,T89	Yes	T85,T91,T89	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T277,*T421,*T422	Yes	T419,T277,T420	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T68,T419,T277	Yes	T68,T419,T277	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T330,T329,T692	Yes	T330,T329,T692	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T91	Yes	T84,T85,T91	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T84,T85,T89	Yes	T84,T85,T89	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T8,T215,T217	Yes	T8,T215,T217	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T91,T89,T90	Yes	T91,T89,T90	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T84,T91,T89	Yes	T84,T85,T91	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T91,*T90,*T155	Yes	T84,T85,T91	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T8,*T9,*T404	Yes	T8,T9,T404	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T8,T9,T404	Yes	T8,T9,T404	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T7,T404,T68	Yes	T7,T404,T68	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T7,T404,T68	Yes	T7,T404,T68	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T7,T404,T68	Yes	T7,T404,T68	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T7,T404,T68	Yes	T7,T404,T68	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T7,T404,T68	Yes	T7,T404,T68	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T7,T404,T68	Yes	T7,T404,T68	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T84,*T91,*T89	Yes	T84,T91,T89	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T84,T91,T89	Yes	T84,T91,T89	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T84,T91,T89	Yes	T84,T91,T89	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T7,T404,T68	Yes	T7,T404,T68	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T7,T404,T68	Yes	T7,T404,T68	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T84,T91,T89	Yes	T84,T91,T89	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T7,T404,T122	Yes	T7,T404,T122	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T7,T404,T122	Yes	T7,T404,T68	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T7,T404,T122	Yes	T7,T404,T122	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T84,T91,T89	Yes	T84,T86,T91	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T89,*T90,*T155	Yes	T84,T91,T89	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T84,T86,T91	Yes	T84,T91,T89	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T7,*T404,*T122	Yes	T7,T404,T122	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T7,T404,T68	Yes	T7,T404,T68	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T2,T46,T47	Yes	T2,T46,T47	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T2,T47,T55	Yes	T2,T47,T55	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T46,T47	Yes	T2,T46,T47	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T2,T46,T47	Yes	T2,T46,T47	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T2,T47,T55	Yes	T2,T47,T55	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T2,T46,T47	Yes	T2,T46,T47	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T58,*T41,*T84	Yes	T58,T41,T84	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T2,T46,T47	Yes	T2,T46,T47	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T2,T46,T47	Yes	T2,T46,T47	INPUT
tl_usbdev_i.d_error	Yes	Yes	T84,T85,T91	Yes	T85,T86,T91	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T2,T47,T55	Yes	T2,T46,T47	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T46,T47	Yes	T2,T47,T55	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T2,T46,T47	Yes	T2,T47,T55	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T58,*T41,*T89	Yes	T58,T41,T84	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T85,T91,T89	Yes	T84,T85,T86	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T2,*T47,*T55	Yes	T2,T47,T55	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T2,T46,T47	Yes	T2,T46,T47	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T84,*T91,*T89	Yes	T84,T91,T89	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T89,T90,T155	Yes	T89,T90,T155	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T91,T89,T155	Yes	T91,T89,T155	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T59,T60,T72	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T4,T118,T72	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T85,T86,T91	Yes	T85,T89,T90	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T85,*T89,*T155	Yes	T85,T86,T91	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T85,T86,T89	Yes	T89,T90,T155	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T84,T86,T91	Yes	T84,T86,T91	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T85,T86,T91	Yes	T85,T86,T91	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T85,T86,T89	Yes	T84,T85,T86	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T85,T86,T91	Yes	T85,T86,T91	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T85,T86,T91	Yes	T84,T85,T86	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T86,T91,T89	Yes	T84,T85,T86	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T84,T85,T86	Yes	T85,T86,T91	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T85,T86,T91	Yes	T85,T86,T91	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T85,T86,T89	Yes	T85,T86,T91	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T86,T91,T89	Yes	T85,T86,T91	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T85,*T86,*T91	Yes	T84,T85,T86	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T3,T25	Yes	T1,T3,T25	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T59,T60,T72	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T84,*T85,*T86	Yes	T84,T85,T86	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T68,T321,T686	Yes	T68,T321,T686	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T68,T321,T686	Yes	T68,T321,T686	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T68,T321,T686	Yes	T68,T321,T686	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T68,T321,T686	Yes	T68,T321,T686	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T68,T321,T686	Yes	T68,T321,T686	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T91	Yes	T84,T85,T91	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T84,T91,T89	Yes	T84,T91,T89	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T321,T686,T687	Yes	T321,T686,T687	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T68,T321,T686	Yes	T68,T321,T686	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T68,T321,T686	Yes	T68,T321,T686	INPUT
tl_hmac_i.d_error	Yes	Yes	T84,T91,T89	Yes	T84,T85,T89	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T321,T686,T687	Yes	T321,T686,T687	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T321,T686,T687	Yes	T321,T686,T687	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T68,T321,T686	Yes	T321,T686,T687	INPUT
tl_hmac_i.d_sink	Yes	Yes	T84,T91,T89	Yes	T84,T85,T91	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T89,*T155,*T234	Yes	T84,T85,T91	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T84,T91,T89	Yes	T84,T91,T89	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T68,*T321,*T686	Yes	T321,T686,T687	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T68,T321,T686	Yes	T68,T321,T686	INPUT
tl_kmac_o.d_ready	Yes	Yes	T101,T59,T60	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T101,T68,T445	Yes	T101,T68,T445	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T101,T177,T193	Yes	T101,T177,T193	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T101,T177,T193	Yes	T101,T177,T193	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T101,T68,T445	Yes	T101,T68,T445	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T101,T177,T193	Yes	T101,T177,T193	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T41,*T84,*T85	Yes	T41,T84,T85	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T101,T445,T446	Yes	T101,T445,T446	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T101,T177,T193	Yes	T101,T177,T193	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T101,T177,T193	Yes	T101,T177,T193	INPUT
tl_kmac_i.d_error	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T101,T177,T193	Yes	T101,T177,T193	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T101,T177,T193	Yes	T101,T177,T193	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T101,T177,T193	Yes	T101,T193,T188	INPUT
tl_kmac_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T41,*T89,*T155	Yes	T41,T84,T85	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T101,*T177,*T193	Yes	T101,T193,T188	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T101,T177,T193	Yes	T101,T177,T193	INPUT
tl_aes_o.d_ready	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T415,T416,T654	Yes	T415,T416,T654	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T415,T416,T654	Yes	T415,T416,T654	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T415,T416,T654	Yes	T415,T416,T654	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T415,T416,T654	Yes	T415,T416,T654	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T415,T416,T654	Yes	T415,T416,T654	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T58,*T220,*T84	Yes	T58,T220,T84	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T85,T91,T89	Yes	T85,T91,T89	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T415,T416,T654	Yes	T415,T416,T654	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T415,T416,T654	Yes	T415,T416,T654	INPUT
tl_aes_i.d_error	Yes	Yes	T85,T86,T91	Yes	T85,T91,T89	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T415,T416,T654	Yes	T415,T416,T654	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T415,T416,T654	Yes	T415,T416,T654	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T415,T416,T654	Yes	T415,T416,T654	INPUT
tl_aes_i.d_sink	Yes	Yes	T85,T86,T91	Yes	T84,T85,T91	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T58,*T220,*T85	Yes	T58,T220,T85	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T85,T91,T89	Yes	T84,T85,T86	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T415,*T416,*T654	Yes	T415,T416,T654	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T415,T416,T654	Yes	T415,T416,T654	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T91	Yes	T84,T85,T91	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T84,T91,T89	Yes	T84,T91,T89	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T84,T91,T89	Yes	T84,T91,T89	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T84,T89,T155	Yes	T84,T89,T155	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T84,T91,T89	Yes	T91,T89,T90	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T89,*T155,*T234	Yes	T84,T91,T89	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T84,T89,T90	Yes	T84,T91,T89	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T152,*T153,*T154	Yes	T152,T153,T154	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T654,T68,T152	Yes	T654,T68,T152	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T58,*T220,*T84	Yes	T58,T220,T84	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T91,T89,T90	Yes	T91,T89,T90	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T84,T91,T89	Yes	T84,T91,T89	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T654,T152,T154	Yes	T654,T152,T154	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T91,T89	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T58,*T220,*T89	Yes	T58,T220,T84	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T91,T89,T90	Yes	T91,T89,T90	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T654,*T152,*T154	Yes	T654,T152,T154	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T654,T68,T152	Yes	T654,T68,T152	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T654,T68,T152	Yes	T654,T68,T152	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T91	Yes	T84,T85,T91	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T85,T91,T89	Yes	T85,T91,T89	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T654,T152,T154	Yes	T654,T152,T154	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T84,*T91,*T89	Yes	T84,T85,T91	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T654,*T152,*T154	Yes	T654,T152,T154	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T68,T152,T154	Yes	T68,T152,T154	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T68,T152,T154	Yes	T68,T152,T154	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T68,T152,T154	Yes	T68,T152,T154	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T68,T152,T154	Yes	T68,T152,T154	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T68,T152,T154	Yes	T68,T152,T154	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T91	Yes	T84,T85,T91	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T68,T152,T154	Yes	T68,T152,T154	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T68,T152,T154	Yes	T68,T152,T154	INPUT
tl_edn1_i.d_error	Yes	Yes	T84,T85,T89	Yes	T84,T85,T89	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T152,T154,T149	Yes	T152,T154,T149	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T154,T149,T260	Yes	T68,T152,T154	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T154,T149,T260	Yes	T68,T152,T154	INPUT
tl_edn1_i.d_sink	Yes	Yes	T84,T85,T86	Yes	T84,T85,T91	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T89,*T90,*T155	Yes	T84,T85,T86	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T152,*T154,*T149	Yes	T152,T154,T149	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T68,T152,T154	Yes	T68,T152,T154	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T25,T4,T5	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T25,T4,T5	Yes	T25,T4,T5	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T25,T4,T5	Yes	T25,T4,T5	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T25,T4,T5	Yes	T25,T4,T5	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T25,T4,T5	Yes	T25,T4,T5	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T25,T4,T5	Yes	T25,T4,T5	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T91	Yes	T84,T85,T91	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T85,T91,T89	Yes	T85,T91,T89	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T25,T4,T5	Yes	T25,T4,T5	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T25,T4,T5	Yes	T25,T4,T5	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T84,T85,T91	Yes	T85,T91,T89	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T25,T4,T5	Yes	T25,T4,T5	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T25,T4,T5	Yes	T25,T4,T5	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T85,T91,T89	Yes	T85,T91,T89	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T85,*T89,*T155	Yes	T85,T86,T91	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T85,T91,T89	Yes	T84,T85,T86	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T25,*T4,*T5	Yes	T25,T4,T5	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T25,T4,T5	Yes	T25,T4,T5	INPUT
tl_otbn_o.d_ready	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T68,T203,T154	Yes	T68,T203,T154	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T68,T203,T154	Yes	T68,T203,T154	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T68,T203,T154	Yes	T68,T203,T154	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T68,T203,T154	Yes	T68,T203,T154	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T68,T203,T154	Yes	T68,T203,T154	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T88,*T41,*T219	Yes	T88,T41,T219	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T68,T203,T154	Yes	T68,T203,T154	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T68,T203,T154	Yes	T68,T203,T154	INPUT
tl_otbn_i.d_error	Yes	Yes	T85,T91,T89	Yes	T85,T91,T89	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T203,T154,T149	Yes	T203,T154,T149	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T203,T154,T149	Yes	T203,T154,T149	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T68,T203,T154	Yes	T203,T154,T149	INPUT
tl_otbn_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T88,*T41,*T219	Yes	T88,T41,T219	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T68,*T203,*T154	Yes	T203,T154,T149	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T68,T203,T154	Yes	T68,T203,T154	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T193,T188,T233	Yes	T193,T188,T233	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T177,T193,T188	Yes	T177,T193,T188	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T177,T193,T188	Yes	T177,T193,T188	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T193,T188,T233	Yes	T193,T188,T233	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T177,T193,T188	Yes	T177,T193,T188	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T89	Yes	T84,T85,T89	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T84,T85,T89	Yes	T84,T85,T89	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T177,T193,T188	Yes	T177,T193,T188	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T177,T193,T188	Yes	T177,T193,T188	INPUT
tl_keymgr_i.d_error	Yes	Yes	T84,T85,T89	Yes	T84,T85,T90	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T193,T188,T233	Yes	T193,T188,T233	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T193,T188,T233	Yes	T193,T188,T233	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T193,T188,T233	Yes	T193,T188,T233	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T84,T85,T89	Yes	T84,T85,T89	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T90,*T155,*T234	Yes	T85,T89,T90	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T84,T85,T89	Yes	T85,T89,T90	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T193,*T188,*T233	Yes	T177,T193,T188	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T177,T193,T188	Yes	T177,T193,T188	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T84,*T85,*T91	Yes	T84,T85,T91	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T85,T89,T155	Yes	T85,T89,T155	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T91,T89,T90	Yes	T91,T89,T90	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T85,T91,T89	Yes	T85,T91,T89	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T25,T7,T4	Yes	T25,T7,T4	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T25,T7,T4	Yes	T25,T7,T4	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T85,T89,T155	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T89,*T90,*T155	Yes	T84,T85,T91	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T85,T89,T90	Yes	T84,T85,T89	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T68,T143,T197	Yes	T68,T143,T197	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T68,T143,T197	Yes	T68,T143,T197	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T68,T143,T197	Yes	T68,T143,T197	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T68,T143,T197	Yes	T68,T143,T197	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T68,T143,T197	Yes	T68,T143,T197	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T441,*T442,*T85	Yes	T441,T442,T85	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T85,T91,T89	Yes	T85,T91,T89	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T85,T91,T89	Yes	T85,T91,T89	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T68,T143,T197	Yes	T68,T143,T197	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T68,T143,T197	Yes	T68,T143,T197	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T85,T89,T90	Yes	T85,T89,T90	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T199,T311,T312	Yes	T199,T311,T312	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T143,T197,T199	Yes	T68,T143,T197	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T143,T197,T199	Yes	T68,T143,T197	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T85,T91,T89	Yes	T85,T91,T89	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T89,*T90,*T155	Yes	T441,T442,T85	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T85,T91,T89	Yes	T85,T91,T89	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T143,*T197,*T199	Yes	T143,T197,T199	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T68,T143,T197	Yes	T68,T143,T197	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T59,T60,T72	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range