Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T330,T329,T692	Yes	T330,T329,T692	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T124,T125,T213	Yes	T124,T125,T213	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T124,T125,T213	Yes	T124,T125,T213	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T124,T68,T125	Yes	T124,T68,T125	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T124,T68,T125	Yes	T124,T68,T125	INPUT
tl_uart0_i.d_error	Yes	Yes	T84,T91,T89	Yes	T84,T85,T91	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T124,T125,T319	Yes	T124,T125,T319	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T124,T125,T181	Yes	T124,T68,T125	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T124,T125,T181	Yes	T124,T68,T125	INPUT
tl_uart0_i.d_sink	Yes	Yes	T84,T91,T89	Yes	T84,T91,T89	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T58,*T23,*T268	Yes	T58,T23,T268	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T84,T91,T90	Yes	T84,T85,T91	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T124,*T125,*T319	Yes	T124,T125,T319	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T124,T68,T125	Yes	T124,T68,T125	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T126,T127,T128	Yes	T126,T127,T128	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T126,T127,T128	Yes	T126,T127,T128	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T126,T127,T68	Yes	T126,T127,T68	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T126,T127,T68	Yes	T126,T127,T68	INPUT
tl_uart1_i.d_error	Yes	Yes	T84,T85,T89	Yes	T84,T86,T89	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T126,T127,T128	Yes	T126,T127,T128	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T126,T127,T128	Yes	T126,T127,T68	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T126,T127,T128	Yes	T126,T127,T68	INPUT
tl_uart1_i.d_sink	Yes	Yes	T84,T85,T86	Yes	T84,T85,T91	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T58,*T41,*T89	Yes	T58,T41,T85	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T86	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T126,*T127,*T128	Yes	T126,T127,T128	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T126,T127,T68	Yes	T126,T127,T68	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T37,T319,T58	Yes	T37,T319,T58	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T37,T319,T58	Yes	T37,T319,T58	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T37,T68,T181	Yes	T37,T68,T181	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T37,T68,T181	Yes	T37,T68,T181	INPUT
tl_uart2_i.d_error	Yes	Yes	T84,T85,T89	Yes	T85,T89,T90	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T37,T319,T58	Yes	T37,T319,T58	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T37,T181,T319	Yes	T37,T68,T181	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T37,T181,T319	Yes	T37,T68,T181	INPUT
tl_uart2_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T85,T91,T89	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T58,*T41,*T89	Yes	T58,T41,T85	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T85,T89,T90	Yes	T85,T89,T90	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T37,*T319,*T58	Yes	T37,T319,T58	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T37,T68,T181	Yes	T37,T68,T181	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T39,T319,T58	Yes	T39,T319,T58	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T39,T319,T58	Yes	T39,T319,T58	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T39,T68,T181	Yes	T39,T68,T181	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T39,T68,T181	Yes	T39,T68,T181	INPUT
tl_uart3_i.d_error	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T39,T319,T58	Yes	T39,T319,T58	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T39,T181,T319	Yes	T39,T68,T181	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T39,T181,T319	Yes	T39,T68,T181	INPUT
tl_uart3_i.d_sink	Yes	Yes	T84,T85,T89	Yes	T84,T85,T91	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T58,*T41,*T89	Yes	T58,T41,T84	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T84,T89,T90	Yes	T84,T85,T91	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T39,*T319,*T58	Yes	T39,T319,T58	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T39,T68,T181	Yes	T39,T68,T181	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T404,T31,T325	Yes	T404,T31,T325	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T404,T31,T325	Yes	T404,T31,T325	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T404,T31,T68	Yes	T404,T31,T68	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T404,T31,T68	Yes	T404,T31,T68	INPUT
tl_i2c0_i.d_error	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T31,T325,T10	Yes	T31,T325,T10	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T404,T31,T181	Yes	T404,T31,T68	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T404,T31,T181	Yes	T404,T31,T68	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T89,*T90,*T155	Yes	T84,T85,T91	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T89	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T404,*T31,*T325	Yes	T404,T31,T325	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T404,T31,T68	Yes	T404,T31,T68	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T404,T33,T325	Yes	T404,T33,T325	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T404,T33,T325	Yes	T404,T33,T325	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T404,T33,T68	Yes	T404,T33,T68	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T404,T33,T68	Yes	T404,T33,T68	INPUT
tl_i2c1_i.d_error	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T33,T325,T10	Yes	T33,T325,T10	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T404,T33,T181	Yes	T404,T33,T68	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T404,T33,T181	Yes	T404,T33,T68	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T84,*T89,*T155	Yes	T84,T85,T91	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T404,*T33,*T325	Yes	T404,T33,T325	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T404,T33,T68	Yes	T404,T33,T68	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T35,T404,T36	Yes	T35,T404,T36	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T35,T404,T36	Yes	T35,T404,T36	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T35,T404,T36	Yes	T35,T404,T36	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T35,T404,T36	Yes	T35,T404,T36	INPUT
tl_i2c2_i.d_error	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T35,T36,T325	Yes	T35,T36,T325	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T35,T404,T36	Yes	T35,T404,T36	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T35,T404,T36	Yes	T35,T404,T36	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T85,*T89,*T90	Yes	T84,T85,T91	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T35,*T404,*T36	Yes	T35,T404,T36	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T35,T404,T36	Yes	T35,T404,T36	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T5,T122,T10	Yes	T5,T122,T10	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T5,T122,T10	Yes	T5,T122,T10	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T5,T68,T122	Yes	T5,T68,T122	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T5,T68,T122	Yes	T5,T68,T122	INPUT
tl_pattgen_i.d_error	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T5,T122,T10	Yes	T5,T122,T10	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T122,T10	Yes	T5,T68,T122	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T5,T122,T10	Yes	T5,T68,T122	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T91,T89	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T41,T91,T89	Yes	T41,T84,T85	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T84,T91,T89	Yes	T84,T85,T91	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T5,*T122,*T10	Yes	T5,T122,T10	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T5,T68,T122	Yes	T5,T68,T122	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T49,T52,T131	Yes	T49,T52,T131	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T49,T52,T131	Yes	T49,T52,T131	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T49,T68,T52	Yes	T49,T68,T52	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T49,T68,T52	Yes	T49,T68,T52	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T85,T91,T89	Yes	T85,T91,T89	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T49,T52,T131	Yes	T49,T52,T131	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T49,T52,T131	Yes	T49,T68,T52	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T49,T52,T131	Yes	T49,T68,T52	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T85,T91,T89	Yes	T85,T91,T89	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T89,*T90,*T155	Yes	T84,T85,T91	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T91,T89,T90	Yes	T91,T89,T90	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T49,*T52,*T131	Yes	T49,T52,T131	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T49,T68,T52	Yes	T49,T68,T52	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_error	Yes	Yes	T85,T91,T89	Yes	T85,T91,T89	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T26,T28,T325	Yes	T26,T28,T325	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T26,T28,T325	Yes	T6,T26,T28	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T26,T28,T325	Yes	T6,T26,T28	INPUT
tl_gpio_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T85,T91,T89	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T91,*T89,*T155	Yes	T84,T85,T91	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T6,*T26,*T28	Yes	T1,T2,T3	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T26,T8,T19	Yes	T26,T8,T19	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T26,T8,T19	Yes	T26,T8,T19	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T26,T8,T19	Yes	T26,T8,T19	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T26,T8,T19	Yes	T26,T8,T19	INPUT
tl_spi_device_i.d_error	Yes	Yes	T84,T91,T89	Yes	T84,T85,T89	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T8,T19,T9	Yes	T8,T19,T9	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T26,T8,T19	Yes	T26,T8,T19	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T26,T8,T19	Yes	T8,T19,T9	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T91,T89	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T89,*T90,*T155	Yes	T84,T91,T89	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T91,T89,T90	Yes	T85,T91,T89	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T26,*T8,*T19	Yes	T26,T8,T19	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T26,T8,T19	Yes	T26,T8,T19	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T121,T254,T122	Yes	T121,T254,T122	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T121,T254,T122	Yes	T121,T254,T122	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T121,T254,T68	Yes	T121,T254,T68	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T121,T254,T68	Yes	T121,T254,T68	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T85,T91,T89	Yes	T85,T91,T89	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T121,T254,T122	Yes	T121,T254,T122	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T121,T254,T122	Yes	T121,T254,T68	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T121,T254,T313	Yes	T121,T254,T68	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T91,*T89,*T90	Yes	T84,T85,T91	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T121,*T254,*T122	Yes	T121,T254,T122	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T121,T254,T68	Yes	T121,T254,T68	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T25,T4,T6	Yes	T25,T4,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T25,T4,T6	Yes	T25,T4,T6	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T25,T4,T6	Yes	T25,T4,T6	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T25,T4,T6	Yes	T25,T4,T6	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T84,T85,T91	Yes	T84,T91,T89	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T25,T4,T6	Yes	T25,T4,T6	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T25,T4,T6	Yes	T25,T4,T6	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T25,T4,T6	Yes	T25,T4,T6	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T84,T85,T86	Yes	T84,T91,T89	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T89,*T155,*T234	Yes	T84,T85,T91	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T84,T91,T89	Yes	T84,T86,T91	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T25,*T4,*T6	Yes	T25,T4,T6	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T25,T4,T6	Yes	T25,T4,T6	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T84,T89,T155	Yes	T84,T89,T155	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T84,*T89,*T155	Yes	T84,T85,T91	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T39,T126,T124	Yes	T39,T126,T124	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T39,T140,T126	Yes	T39,T140,T126	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T39,T126,T124	Yes	T39,T126,T124	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T72,T73,T39	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T72,T73,T39	Yes	T1,T2,T3	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T58,*T220,*T84	Yes	T58,T173,T174	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T84,T86,T91	Yes	T84,T86,T91	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T39,*T126,*T124	Yes	T39,T126,T124	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T84,T89,T90	Yes	T84,T89,T90	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T91,T89	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T41,*T84,*T89	Yes	T41,T84,T85	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T91,T89	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T85,T91,T89	Yes	T85,T91,T89	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T85,T91,T89	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T173,*T174,*T41	Yes	T173,T174,T41	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T63,*T175,*T176	Yes	T175,T176,T177	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T41,T84,T85	Yes	T41,T84,T85	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T41,T84,T85	Yes	T41,T84,T85	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T41,T84,T85	Yes	T41,T84,T85	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T1,T2,T3	Yes	T72,T73,T74	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T41,T84,T85	Yes	T41,T84,T85	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T41,T85,T91	Yes	T41,T84,T85	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T72,T73,T74	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T84,T85,T89	Yes	T84,T91,T89	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T41,T89,T90	Yes	T41,T84,T85	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T89	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T72,T73,T74	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T41,T84,T85	Yes	T41,T84,T85	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T118,T176,T74	Yes	T118,T176,T74	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T118,T176,T74	Yes	T118,T176,T74	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T118,T176,T74	Yes	T118,T176,T74	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T118,T176,T74	Yes	T118,T176,T74	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T176,T74,T193	Yes	T118,T176,T74	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T74,T186,T151	Yes	T74,T186,T68	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T176,T74,T193	Yes	T118,T176,T74	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T87,*T345,*T41	Yes	T87,T345,T41	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T74,*T193,*T188	Yes	T118,T176,T74	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T118,T176,T74	Yes	T118,T176,T74	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T84,T91,T155	Yes	T84,T85,T91	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T169,T157,T122	Yes	T169,T157,T122	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T169,T157,T122	Yes	T68,T169,T157	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T84,*T89,*T155	Yes	T84,T91,T89	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T72,*T73,*T74	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T73,T75,T76	Yes	T73,T75,T76	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T73,T75,T76	Yes	T73,T75,T76	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T73,T75,T76	Yes	T73,T75,T76	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T73,T75,T76	Yes	T73,T75,T76	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T85,T91,T89	Yes	T85,T91,T89	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T73,T75,T76	Yes	T73,T75,T76	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T73,T75,T76	Yes	T73,T75,T76	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T73,T75,T76	Yes	T73,T75,T76	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T85,T91,T89	Yes	T85,T91,T89	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T58,*T220,*T85	Yes	T58,T220,T85	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T85,T89,T90	Yes	T85,T91,T89	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T73,*T75,*T76	Yes	T73,T75,T76	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T73,T75,T76	Yes	T73,T75,T76	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T143,T197,T198	Yes	T143,T197,T198	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T143,T197,T198	Yes	T143,T197,T198	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T68,T143,T197	Yes	T68,T143,T197	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T68,T143,T197	Yes	T68,T143,T197	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T84,T89,T90	Yes	T84,T85,T89	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T143,T197,T198	Yes	T143,T197,T198	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T143,T197,T198	Yes	T68,T143,T197	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T143,T197,T198	Yes	T68,T143,T197	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T84,T91,T89	Yes	T84,T85,T89	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T84,*T89,*T155	Yes	T84,T85,T89	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T84,T89,T155	Yes	T84,T85,T89	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T143,*T197,*T198	Yes	T143,T197,T198	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T68,T143,T197	Yes	T68,T143,T197	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T73,T253,T177	Yes	T73,T253,T177	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T59,T60,T72	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T73,T253,T177	Yes	T73,T253,T177	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T59,T60,T72	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T73,T75,T76	Yes	T73,T75,T76	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T85,T89	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T88,*T219,*T221	Yes	T88,T219,T221	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T89	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T73,T253,T75	Yes	T73,T253,T75	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T73,T253,T75	Yes	T73,T253,T75	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T73,T253,T75	Yes	T73,T253,T75	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T73,T253,T75	Yes	T73,T253,T75	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T73,T253,T75	Yes	T73,T253,T75	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T73,T253,T75	Yes	T73,T253,T75	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T73,T253,T75	Yes	T73,T253,T75	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T58,*T220,*T84	Yes	T58,T23,T268	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T91,T89	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T73,*T253,*T75	Yes	T73,T253,T75	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T73,T253,T75	Yes	T73,T253,T75	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T42,T11,T44	Yes	T42,T11,T44	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T42,T11,T44	Yes	T42,T11,T44	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T42,T11,T44	Yes	T42,T11,T44	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T42,T11,T44	Yes	T42,T11,T44	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T84,T85,T91	Yes	T85,T91,T89	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T42,T11,T44	Yes	T42,T11,T44	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T11,T44,T45	Yes	T11,T44,T45	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T42,T11,T44	Yes	T42,T11,T44	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T58,*T41,*T91	Yes	T58,T41,T84	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T11,*T44,*T45	Yes	T42,T11,T44	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T42,T11,T44	Yes	T42,T11,T44	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T134,T325,T79	Yes	T134,T325,T79	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T134,T325,T79	Yes	T134,T325,T79	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T68,T134,T325	Yes	T68,T134,T325	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T68,T134,T325	Yes	T68,T134,T325	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T89,T90,T155	Yes	T84,T90,T155	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T134,T325,T65	Yes	T134,T325,T79	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T134,T325,T79	Yes	T68,T134,T325	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T134,T79,T65	Yes	T68,T134,T325	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T91,T90,T155	Yes	T91,T90,T155	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T58,*T220,*T89	Yes	T58,T220,T84	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T85,T91,T89	Yes	T91,T90,T155	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T134,*T325,*T65	Yes	T134,T325,T79	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T68,T134,T325	Yes	T68,T134,T325	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T87,*T58,*T88	Yes	T87,T58,T88	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T58,T88,T41	Yes	T58,T88,T41	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	Yes	Yes	T84,T91,T89	Yes	T84,T91,T89	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T84,T91,T89	Yes	T84,T85,T91	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T1,T2,T3	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	Yes	Yes	T84,T85,T91	Yes	T84,T85,T91	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T91,*T89,*T155	Yes	T84,T85,T91	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T84,T85,T91	Yes	T84,T91,T89	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T84,*T91,*T89	Yes	T84,T85,T91	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range