Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1007	1007	0	0
OutputsKnown_A	120293070	119621917	0	0
gen_no_flops.OutputDelay_A	120293070	119621917	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120293070	119621917	0	0
T1	22688	22016	0	0
T2	24102	23625	0	0
T3	14689	14148	0	0
T4	22449	22090	0	0
T7	22940	22339	0	0
T25	25024	24333	0	0
T46	16516	16104	0	0
T99	16620	16255	0	0
T100	11040	10497	0	0
T101	23528	23110	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120293070	119621917	0	0
T1	22688	22016	0	0
T2	24102	23625	0	0
T3	14689	14148	0	0
T4	22449	22090	0	0
T7	22940	22339	0	0
T25	25024	24333	0	0
T46	16516	16104	0	0
T99	16620	16255	0	0
T100	11040	10497	0	0
T101	23528	23110	0	0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1007	1007	0	0
OutputsKnown_A	120293070	119621917	0	0
gen_no_flops.OutputDelay_A	120293070	119621917	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120293070	119621917	0	0
T1	22688	22016	0	0
T2	24102	23625	0	0
T3	14689	14148	0	0
T4	22449	22090	0	0
T7	22940	22339	0	0
T25	25024	24333	0	0
T46	16516	16104	0	0
T99	16620	16255	0	0
T100	11040	10497	0	0
T101	23528	23110	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120293070	119621917	0	0
T1	22688	22016	0	0
T2	24102	23625	0	0
T3	14689	14148	0	0
T4	22449	22090	0	0
T7	22940	22339	0	0
T25	25024	24333	0	0
T46	16516	16104	0	0
T99	16620	16255	0	0
T100	11040	10497	0	0
T101	23528	23110	0	0