Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.72	97.23			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.72	97.23			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.72	97.23			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.72	97.23			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.72	97.23			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.72	97.23			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.68	96.99	84.51			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.24	99.72	97.23			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T84 T85 T86 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T163 T167 T83 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T163 T167 T83 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T163 T167 T83 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T163 T167 T83 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T163 T167 T83 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T163 T167 T83 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T163 T167 T83 
135        1/1                txn_bits_q <= '0;
           Tests:       T163 T167 T83 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T163 T167 T83 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T163 T167 T83 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T163 T167 T83 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T163,T167,T83

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T163,T167,T83
1	1	Covered	T163,T167,T83

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T163,T167,T83

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T163,T167,T83
1	1	Covered	T163,T167,T83

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T163,T167,T83
0	0	1	Covered	T163,T167,T83
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T163,T167,T83
0	0	1	Covered	T163,T167,T83
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	134674239	65714	0	0
DstReqKnown_A	1631218	1409612	0	0
SrcAckBusyChk_A	134674239	172	0	0
SrcBusyKnown_A	134674239	133878317	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134674239	65714	0	0
T398	53318	460	0	0
T399	66592	345	0	0
T400	44385	251	0	0
T403	67912	263	0	0
T424	87763	853	0	0
T425	70214	399	0	0
T426	86301	692	0	0
T427	46021	315	0	0
T428	58868	260	0	0
T429	52480	440	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1631218	1409612	0	0
T1	385	211	0	0
T2	439	267	0	0
T3	347	173	0	0
T4	535	361	0	0
T7	400	226	0	0
T25	405	231	0	0
T46	400	228	0	0
T99	426	254	0	0
T100	314	140	0	0
T101	462	288	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134674239	172	0	0
T398	53318	1	0	0
T399	66592	1	0	0
T400	44385	1	0	0
T403	67912	1	0	0
T424	87763	2	0	0
T425	70214	1	0	0
T426	86301	2	0	0
T427	46021	1	0	0
T428	58868	1	0	0
T429	52480	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134674239	133878317	0	0
T1	22688	22016	0	0
T2	24102	23625	0	0
T3	14689	14148	0	0
T4	22449	22090	0	0
T7	22940	22339	0	0
T25	25024	24333	0	0
T46	16516	16104	0	0
T99	16620	16255	0	0
T100	11040	10497	0	0
T101	23528	23110	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T84 T85 T86 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T163 T167 T83 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T163 T167 T83 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T163 T167 T83 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T163 T167 T83 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T163 T167 T83 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T163 T167 T83 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T163 T167 T83 
135        1/1                txn_bits_q <= '0;
           Tests:       T163 T167 T83 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T163 T167 T83 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T163 T167 T83 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T163 T167 T83 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T163,T167,T83

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T163,T167,T83
1	1	Covered	T163,T167,T83

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T163,T167,T83

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T163,T167,T83
1	1	Covered	T163,T167,T83

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T163,T167,T83
0	0	1	Covered	T163,T167,T83
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T163,T167,T83
0	0	1	Covered	T163,T167,T83
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	134674239	70252	0	0
DstReqKnown_A	1631218	1409612	0	0
SrcAckBusyChk_A	134674239	183	0	0
SrcBusyKnown_A	134674239	133878317	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134674239	70252	0	0
T398	53318	459	0	0
T399	66592	341	0	0
T400	44385	284	0	0
T403	67912	309	0	0
T424	87763	896	0	0
T425	70214	387	0	0
T426	86301	751	0	0
T427	46021	311	0	0
T428	58868	273	0	0
T429	52480	400	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1631218	1409612	0	0
T1	385	211	0	0
T2	439	267	0	0
T3	347	173	0	0
T4	535	361	0	0
T7	400	226	0	0
T25	405	231	0	0
T46	400	228	0	0
T99	426	254	0	0
T100	314	140	0	0
T101	462	288	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134674239	183	0	0
T398	53318	1	0	0
T399	66592	1	0	0
T400	44385	1	0	0
T403	67912	1	0	0
T424	87763	2	0	0
T425	70214	1	0	0
T426	86301	2	0	0
T427	46021	1	0	0
T428	58868	1	0	0
T429	52480	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134674239	133878317	0	0
T1	22688	22016	0	0
T2	24102	23625	0	0
T3	14689	14148	0	0
T4	22449	22090	0	0
T7	22940	22339	0	0
T25	25024	24333	0	0
T46	16516	16104	0	0
T99	16620	16255	0	0
T100	11040	10497	0	0
T101	23528	23110	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T84 T85 T86 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T163 T167 T83 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T163 T167 T83 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T163 T167 T83 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T163 T167 T83 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T163 T167 T83 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T163 T167 T83 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T163 T167 T83 
135        1/1                txn_bits_q <= '0;
           Tests:       T163 T167 T83 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T163 T167 T83 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T163 T167 T83 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T163 T167 T83 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T163,T167,T83

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T163,T167,T83
1	1	Covered	T163,T167,T83

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T163,T167,T83

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T163,T167,T83
1	1	Covered	T163,T167,T83

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T163,T167,T83
0	0	1	Covered	T163,T167,T83
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T163,T167,T83
0	0	1	Covered	T163,T167,T83
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	134674239	90854	0	0
DstReqKnown_A	1631218	1409612	0	0
SrcAckBusyChk_A	134674239	233	0	0
SrcBusyKnown_A	134674239	133878317	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134674239	90854	0	0
T398	53318	414	0	0
T399	66592	297	0	0
T400	44385	326	0	0
T403	67912	321	0	0
T424	87763	805	0	0
T425	70214	471	0	0
T426	86301	629	0	0
T427	46021	310	0	0
T428	58868	292	0	0
T429	52480	410	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1631218	1409612	0	0
T1	385	211	0	0
T2	439	267	0	0
T3	347	173	0	0
T4	535	361	0	0
T7	400	226	0	0
T25	405	231	0	0
T46	400	228	0	0
T99	426	254	0	0
T100	314	140	0	0
T101	462	288	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134674239	233	0	0
T398	53318	1	0	0
T399	66592	1	0	0
T400	44385	1	0	0
T403	67912	1	0	0
T424	87763	2	0	0
T425	70214	1	0	0
T426	86301	2	0	0
T427	46021	1	0	0
T428	58868	1	0	0
T429	52480	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134674239	133878317	0	0
T1	22688	22016	0	0
T2	24102	23625	0	0
T3	14689	14148	0	0
T4	22449	22090	0	0
T7	22940	22339	0	0
T25	25024	24333	0	0
T46	16516	16104	0	0
T99	16620	16255	0	0
T100	11040	10497	0	0
T101	23528	23110	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T84 T85 T86 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T163 T167 T83 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T163 T167 T83 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T163 T167 T83 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T163 T167 T83 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T163 T167 T83 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T163 T167 T83 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T163 T167 T83 
135        1/1                txn_bits_q <= '0;
           Tests:       T163 T167 T83 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T163 T167 T83 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T163 T167 T83 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T163 T167 T83 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T163,T167,T83

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T163,T167,T83
1	1	Covered	T163,T167,T83

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T163,T167,T83

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T163,T167,T83
1	1	Covered	T163,T167,T83

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T163,T167,T83
0	0	1	Covered	T163,T167,T83
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T163,T167,T83
0	0	1	Covered	T163,T167,T83
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	134674239	69325	0	0
DstReqKnown_A	1631218	1409612	0	0
SrcAckBusyChk_A	134674239	181	0	0
SrcBusyKnown_A	134674239	133878317	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134674239	69325	0	0
T398	53318	443	0	0
T399	66592	318	0	0
T400	44385	300	0	0
T403	67912	353	0	0
T424	87763	751	0	0
T425	70214	438	0	0
T426	86301	719	0	0
T427	46021	310	0	0
T428	58868	352	0	0
T429	52480	461	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1631218	1409612	0	0
T1	385	211	0	0
T2	439	267	0	0
T3	347	173	0	0
T4	535	361	0	0
T7	400	226	0	0
T25	405	231	0	0
T46	400	228	0	0
T99	426	254	0	0
T100	314	140	0	0
T101	462	288	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134674239	181	0	0
T398	53318	1	0	0
T399	66592	1	0	0
T400	44385	1	0	0
T403	67912	1	0	0
T424	87763	2	0	0
T425	70214	1	0	0
T426	86301	2	0	0
T427	46021	1	0	0
T428	58868	1	0	0
T429	52480	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134674239	133878317	0	0
T1	22688	22016	0	0
T2	24102	23625	0	0
T3	14689	14148	0	0
T4	22449	22090	0	0
T7	22940	22339	0	0
T25	25024	24333	0	0
T46	16516	16104	0	0
T99	16620	16255	0	0
T100	11040	10497	0	0
T101	23528	23110	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T84 T85 T86 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T163 T167 T83 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T163 T167 T83 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T163 T167 T83 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T163 T167 T83 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T163 T167 T83 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T163 T167 T83 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T163 T167 T83 
135        1/1                txn_bits_q <= '0;
           Tests:       T163 T167 T83 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T163 T167 T83 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T163 T167 T83 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T163 T167 T83 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T163,T167,T83

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T163,T167,T83
1	1	Covered	T163,T167,T83

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T163,T167,T83

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T163,T167,T83
1	1	Covered	T163,T167,T83

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T163,T167,T83
0	0	1	Covered	T163,T167,T83
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T163,T167,T83
0	0	1	Covered	T163,T167,T83
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	134674239	84427	0	0
DstReqKnown_A	1631218	1409612	0	0
SrcAckBusyChk_A	134674239	216	0	0
SrcBusyKnown_A	134674239	133878317	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134674239	84427	0	0
T398	53318	395	0	0
T399	66592	317	0	0
T400	44385	338	0	0
T403	67912	362	0	0
T424	87763	857	0	0
T425	70214	382	0	0
T426	86301	760	0	0
T427	46021	358	0	0
T428	58868	248	0	0
T429	52480	444	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1631218	1409612	0	0
T1	385	211	0	0
T2	439	267	0	0
T3	347	173	0	0
T4	535	361	0	0
T7	400	226	0	0
T25	405	231	0	0
T46	400	228	0	0
T99	426	254	0	0
T100	314	140	0	0
T101	462	288	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134674239	216	0	0
T398	53318	1	0	0
T399	66592	1	0	0
T400	44385	1	0	0
T403	67912	1	0	0
T424	87763	2	0	0
T425	70214	1	0	0
T426	86301	2	0	0
T427	46021	1	0	0
T428	58868	1	0	0
T429	52480	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134674239	133878317	0	0
T1	22688	22016	0	0
T2	24102	23625	0	0
T3	14689	14148	0	0
T4	22449	22090	0	0
T7	22940	22339	0	0
T25	25024	24333	0	0
T46	16516	16104	0	0
T99	16620	16255	0	0
T100	11040	10497	0	0
T101	23528	23110	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T84 T85 T86 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T163 T167 T83 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T163 T167 T83 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T163 T167 T83 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T163 T167 T83 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T163 T167 T83 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T163 T167 T83 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T163 T167 T83 
135        1/1                txn_bits_q <= '0;
           Tests:       T163 T167 T83 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T163 T167 T83 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T163 T167 T83 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T163 T167 T83 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T163,T167,T83

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T163,T167,T83
1	1	Covered	T163,T167,T83

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T163,T167,T83

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T163,T167,T83
1	1	Covered	T163,T167,T83

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T163,T167,T83
0	0	1	Covered	T163,T167,T83
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T163,T167,T83
0	0	1	Covered	T163,T167,T83
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	134674239	74723	0	0
DstReqKnown_A	1631218	1409612	0	0
SrcAckBusyChk_A	134674239	194	0	0
SrcBusyKnown_A	134674239	133878317	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134674239	74723	0	0
T398	53318	380	0	0
T399	66592	303	0	0
T400	44385	345	0	0
T403	67912	351	0	0
T424	87763	754	0	0
T425	70214	468	0	0
T426	86301	683	0	0
T427	46021	253	0	0
T428	58868	260	0	0
T429	52480	393	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1631218	1409612	0	0
T1	385	211	0	0
T2	439	267	0	0
T3	347	173	0	0
T4	535	361	0	0
T7	400	226	0	0
T25	405	231	0	0
T46	400	228	0	0
T99	426	254	0	0
T100	314	140	0	0
T101	462	288	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134674239	194	0	0
T398	53318	1	0	0
T399	66592	1	0	0
T400	44385	1	0	0
T403	67912	1	0	0
T424	87763	2	0	0
T425	70214	1	0	0
T426	86301	2	0	0
T427	46021	1	0	0
T428	58868	1	0	0
T429	52480	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134674239	133878317	0	0
T1	22688	22016	0	0
T2	24102	23625	0	0
T3	14689	14148	0	0
T4	22449	22090	0	0
T7	22940	22339	0	0
T25	25024	24333	0	0
T46	16516	16104	0	0
T99	16620	16255	0	0
T100	11040	10497	0	0
T101	23528	23110	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T6 T26 T65 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T2 T3 
73         1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T6 T26 T65 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T2 T3 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T6 T26 T65 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T6 T26 T65 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T6 T26 T65 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T2 T3 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T2 T3 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
118        1/1              end else if (src_req) begin
           Tests:       T1 T2 T3 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T6 T26 T65 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T6 T26 T65 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T2 T3 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T4 T6 T26 
135        1/1                txn_bits_q <= '0;
           Tests:       T4 T6 T26 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T2 T3 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T4 T6 T26 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T4 T6 T26 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T6 T26 T65 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T6,T26,T65

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T26,T65
1	1	Covered	T6,T26,T65

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T26
1	0	Covered	T6,T26,T65

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T26,T65
1	1	Covered	T6,T26,T65

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T6,T26

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T26,T65
0	0	1	Covered	T6,T26,T65
0	0	0	Covered	T1,T2,T3

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T26,T65
0	0	1	Covered	T4,T6,T26
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	134674239	103020	0	0
DstReqKnown_A	1631218	1409612	0	0
SrcAckBusyChk_A	134674239	236	0	0
SrcBusyKnown_A	134674239	133878317	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134674239	103020	0	0
T6	43797	2062	0	0
T26	38278	924	0	0
T27	0	924	0	0
T28	49683	0	0	0
T53	0	1362	0	0
T59	15016	0	0	0
T60	15073	0	0	0
T63	23264	0	0	0
T65	0	793	0	0
T66	0	939	0	0
T67	0	1459	0	0
T72	20508	0	0	0
T73	61337	0	0	0
T117	0	907	0	0
T118	23961	0	0	0
T119	0	1443	0	0
T184	10243	0	0	0
T423	0	798	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1631218	1409612	0	0
T1	385	211	0	0
T2	439	267	0	0
T3	347	173	0	0
T4	535	361	0	0
T7	400	226	0	0
T25	405	231	0	0
T46	400	228	0	0
T99	426	254	0	0
T100	314	140	0	0
T101	462	288	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134674239	236	0	0
T6	43797	5	0	0
T26	38278	3	0	0
T27	0	3	0	0
T28	49683	0	0	0
T53	0	3	0	0
T59	15016	0	0	0
T60	15073	0	0	0
T63	23264	0	0	0
T65	0	2	0	0
T66	0	2	0	0
T67	0	4	0	0
T72	20508	0	0	0
T73	61337	0	0	0
T117	0	2	0	0
T118	23961	0	0	0
T119	0	4	0	0
T184	10243	0	0	0
T423	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134674239	133878317	0	0
T1	22688	22016	0	0
T2	24102	23625	0	0
T3	14689	14148	0	0
T4	22449	22090	0	0
T7	22940	22339	0	0
T25	25024	24333	0	0
T46	16516	16104	0	0
T99	16620	16255	0	0
T100	11040	10497	0	0
T101	23528	23110	0	0