Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.55	89.27	76.94			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.55	89.27	76.94			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		gen_target[0].u_target

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

	Line No.	Total	Covered	Percent
TOTAL		1258	1123	89.27
CONT_ASSIGN	72	1	0	0.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
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CONT_ASSIGN	85	0	0
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CONT_ASSIGN	85	1	1	100.00
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CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	0	0
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CONT_ASSIGN	85	0	0
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CONT_ASSIGN	85	0	0
CONT_ASSIGN	85	0	0
CONT_ASSIGN	85	0	0
CONT_ASSIGN	85	0	0
CONT_ASSIGN	85	0	0
CONT_ASSIGN	85	0	0
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CONT_ASSIGN	85	0	0
CONT_ASSIGN	85	0	0
CONT_ASSIGN	85	0	0
CONT_ASSIGN	85	0	0
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CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ROUTINE	114	0	0
ROUTINE	125	0	0
CONT_ASSIGN	138	0	0
CONT_ASSIGN	139	0	0

Click here to see the source line report.

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

	Total	Covered	Percent
Conditions	3313	2549	76.94
Logical	3313	2549	76.94
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
85	64.00
85	64.20
85	62.39
85	57.55
85	55.95
85-90	86.57
90	100.00
90-91	100.00
91	100.00
91-92	100.00
92	100.00

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

	Line No.	Total	Covered	Percent
Branches		1320	1320	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
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TERNARY	91	2	2	100.00
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TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
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TERNARY	90	2	2	100.00
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TERNARY	90	2	2	100.00
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TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
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TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
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TERNARY	90	2	2	100.00
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TERNARY	92	2	2	100.00
TERNARY	90	1	1	100.00
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TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
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TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
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TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T26
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T26
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T26
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T28,T8
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T28,T8
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T28,T8
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T39,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T39,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T39,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T76,T35
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T76,T35
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T76,T35
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T118,T140,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T118,T140,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T118,T140,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T126,T37
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T126,T37
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T126,T37
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T33,T325
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T33,T325
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T33,T325
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T76,T35
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T76,T35
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T76,T35
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T26
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T26
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T26
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T317,T325,T326
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T317,T325,T326
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T317,T325,T326
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T126,T124,T127
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T126,T124,T127
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T126,T124,T127
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T37,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T37,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T37,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T19,T31,T122
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T19,T31,T122
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T19,T31,T122
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T325,T34
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T325,T34
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T325,T34
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T36,T325,T133
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T36,T325,T133
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T36,T325,T133
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T76,T231
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T76,T231
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T76,T231
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T26
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T26
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T26
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T154,T122,T317
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T154,T122,T317
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T154,T122,T317
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T317,T325,T326
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T317,T325,T326
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T317,T325,T326
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T124,T125,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T124,T125,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T124,T125,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T126,T127,T128
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T126,T127,T128
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T126,T127,T128
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T37,T319,T38
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T37,T319,T38
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T37,T319,T38
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T319,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T319,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T319,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T39,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T39,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T39,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T8,T122
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T8,T122
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T8,T122
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T122,T325
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T122,T325
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T122,T325
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T325,T32
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T325,T32
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T325,T32
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T325,T34
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T325,T34
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T325,T34
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T325,T34
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T325,T34
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T325,T34
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T36,T325,T133
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T36,T325,T133
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T36,T325,T133
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T35,T36,T325
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T35,T36,T325
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T35,T36,T325
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T76,T231,T348
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T76,T231,T348
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T76,T231,T348
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T319,T178
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T319,T178
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T319,T178
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T253,T332,T254
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T253,T332,T254
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T253,T332,T254
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T118,T140,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T118,T140,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T118,T140,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T154,T122,T317
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T154,T122,T317
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T154,T122,T317
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T317,T325,T326
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T317,T325,T326
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T317,T325,T326
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T124,T125,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T124,T125,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T124,T125,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T126,T127,T128
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T126,T127,T128
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T126,T127,T128
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T126,T37,T127
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T126,T37,T127
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T126,T37,T127
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T37,T319,T38
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T37,T319,T38
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T37,T319,T38
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T37,T319,T38
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T37,T319,T38
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T37,T319,T38
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T319,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T319,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T319,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T19,T122,T20
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T19,T122,T20
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T19,T122,T20
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T325,T32
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T325,T32
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T325,T32
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T325,T32
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T325,T32
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T325,T32
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T36,T325,T133
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T36,T325,T133
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T36,T325,T133
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T122,T130
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T122,T130
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T122,T130
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T76,T231,T348
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T76,T231,T348
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T76,T231,T348
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T181,T122,T325
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T181,T122,T325
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T181,T122,T325
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T319,T178
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T319,T178
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T319,T178
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T43,T134,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T43,T134,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T43,T134,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T122,T333
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T122,T333
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T169,T122,T333
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T140,T320,T325
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T140,T320,T325
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T140,T320,T325
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T321,T322,T325
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T321,T322,T325
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T321,T322,T325
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T317,T325,T326
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T317,T325,T326
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T317,T325,T326
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T317,T325,T326
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T317,T325,T326
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T317,T325,T326
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T124,T125,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T124,T125,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T124,T125,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T124,T125,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T124,T125,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T124,T125,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T124,T125,T319
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T124,T125,T319
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T124,T125,T319
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T126,T127,T128
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T126,T127,T128
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T126,T127,T128
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T126,T127,T128
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T126,T127,T128
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T126,T127,T128
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T37,T319,T38
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T37,T319,T38
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T37,T319,T38
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T37,T319,T38
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T37,T319,T38
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T37,T319,T38
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T37,T319,T38
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T37,T319,T38
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T37,T319,T38
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T319,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T319,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T319,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T319,T40
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T319,T40
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T39,T319,T40
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T325,T30
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T122,T215
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T122,T215
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T122,T215
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T325,T32
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T325,T32
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T325,T32
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T325,T34
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T325,T34
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T325,T34
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T325,T34
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T325,T34
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T33,T325,T34
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T36,T325,T133
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T36,T325,T133
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T36,T325,T133
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T122,T130
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T122,T130
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T122,T130
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T76,T231,T348
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T76,T231,T348
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T76,T231,T348
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T329,T326
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T329,T326
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T329,T326
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T319,T323,T324
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T26
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T26
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T26
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T134,T325,T331
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T134,T325,T331
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T134,T325,T331
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T253,T254,T348
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T253,T254,T348
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T253,T254,T348
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T118,T140,T320
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T118,T140,T320
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T118,T140,T320
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T140,T320,T325
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T140,T320,T325
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T140,T320,T325
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T122,T178,T179
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T317,T325,T326
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T317,T325,T326
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T317,T325,T326
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T325,T326,T327
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxComputationInvalid_A	482982954	481186523	0	0
MaxComputation_A	482982954	1691826	0	0
MaxIndexComputationInvalid_A	482982954	481186523	0	0
MaxIndexComputation_A	482982954	1691826	0	0
NumSources_A	1007	1007	0	0
ValidInImpliesValidOut_A	482982954	482878349	0	0

MaxComputationInvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	481186523	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81463	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

MaxComputation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	1691826	0	0
T4	81721	200	0	0
T5	95696	147	0	0
T6	131546	1034	0	0
T8	0	1388	0	0
T26	114156	2044	0	0
T28	201704	5411	0	0
T39	0	1227	0	0
T59	50223	0	0	0
T60	50831	0	0	0
T63	93588	0	0	0
T73	0	1072	0	0
T101	94759	0	0	0
T118	96754	1553	0	0
T140	0	9020	0	0

MaxIndexComputationInvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	481186523	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81463	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0

MaxIndexComputation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	1691826	0	0
T4	81721	200	0	0
T5	95696	147	0	0
T6	131546	1034	0	0
T8	0	1388	0	0
T26	114156	2044	0	0
T28	201704	5411	0	0
T39	0	1227	0	0
T59	50223	0	0	0
T60	50831	0	0	0
T63	93588	0	0	0
T73	0	1072	0	0
T101	94759	0	0	0
T118	96754	1553	0	0
T140	0	9020	0	0

NumSources_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1007	1007	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T25	1	1	0	0
T46	1	1	0	0
T99	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0

ValidInImpliesValidOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	482982954	482878349	0	0
T1	90199	90141	0	0
T2	96900	96845	0	0
T3	57421	57359	0	0
T4	81721	81663	0	0
T7	91544	91486	0	0
T25	94967	94905	0	0
T46	65559	65508	0	0
T99	66193	66142	0	0
T100	42210	42152	0	0
T101	94759	94701	0	0