8a1401d614| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_example_tests | chip_sw_example_flash | 4.099m | 3.213ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.462m | 2.314ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 4.528m | 2.139ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 4.719m | 3.155ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 6.993m | 5.886ms | 4 | 5 | 80.00 |
| V1 | csr_rw | chip_csr_rw | 11.007m | 5.896ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 28.138m | 13.902ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 1.779h | 37.095ms | 1 | 5 | 20.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 17.233m | 12.487ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 1.779h | 37.095ms | 1 | 5 | 20.00 |
| chip_csr_rw | 11.007m | 5.896ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 16.120s | 261.591us | 100 | 100 | 100.00 |
| V1 | chip_sw_gpio_out | chip_sw_gpio | 9.873m | 4.730ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 9.873m | 4.730ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 9.873m | 4.730ms | 3 | 3 | 100.00 |
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 12.571m | 4.514ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 12.571m | 4.514ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 10.581m | 3.784ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 10.932m | 4.247ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 12.035m | 4.380ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_baud_rate | chip_sw_uart_rand_baudrate | 45.736m | 13.774ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 49.260m | 12.918ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 19.541m | 8.670ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 215 | 220 | 97.73 | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 6.118m | 5.528ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 6.118m | 5.528ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 5.280m | 3.215ms | 1 | 3 | 33.33 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 7.006m | 5.949ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 6.056m | 3.164ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 31.828m | 15.338ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 8.967m | 5.895ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 13.295m | 7.716ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 17.236m | 10.151ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 5.593m | 2.843ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 23.106m | 9.149ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 16.530m | 6.711ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 16.530m | 6.711ms | 6 | 6 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 15.417m | 7.199ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 49.532m | 20.412ms | 2 | 3 | 66.67 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 11.471m | 4.699ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 17.523m | 5.749ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.276h | 18.027ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.873m | 2.836ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 15.879m | 6.571ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 4.713m | 2.304ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 32.413m | 9.204ms | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.503m | 3.385ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.403m | 5.147ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 3.904m | 2.302ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 4.768m | 2.593ms | 1 | 1 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 17.923m | 9.474ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 8.819m | 5.344ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 4.542m | 2.599ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 8.819m | 5.344ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 3.841m | 3.131ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 5.993m | 2.908ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 6.022m | 2.798ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 4.370m | 2.550ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 4.345m | 2.857ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 10.074m | 3.667ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 5.437m | 2.845ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 6.151m | 2.406ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 6.066m | 2.729ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 32.401m | 9.424ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 8.955m | 5.592ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 7.918m | 5.433ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 4.797m | 3.127ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 4.929m | 3.119ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 5.140m | 2.415ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 4.213m | 2.902ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 4.764m | 3.731ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_smoketest | chip_sw_otp_ctrl_smoketest | 6.159m | 3.302ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 9.167m | 4.705ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 5.273h | 81.958ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 1.222h | 14.831ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 4.835m | 5.600ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 10.546m | 4.319ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 10.323m | 10.259ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 3.399h | 63.090ms | 1 | 3 | 33.33 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 4.496h | 68.360ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 8.827m | 5.127ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 8.827m | 5.127ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 1.779h | 37.095ms | 1 | 5 | 20.00 |
| chip_same_csr_outstanding | 1.057h | 28.826ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 6.993m | 5.886ms | 4 | 5 | 80.00 | ||
| chip_csr_rw | 11.007m | 5.896ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 1.779h | 37.095ms | 1 | 5 | 20.00 |
| chip_same_csr_outstanding | 1.057h | 28.826ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 6.993m | 5.886ms | 4 | 5 | 80.00 | ||
| chip_csr_rw | 11.007m | 5.896ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.747m | 2.371ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 10.250s | 60.648us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 2.471m | 10.264ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 2.534m | 6.855ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 1.217m | 601.257us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 11.508m | 62.792ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 10.178m | 35.280ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.219m | 1.342ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.082m | 1.236ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.810m | 2.232ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.082m | 1.236ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 2.876m | 3.700ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 22.996m | 81.396ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.792m | 2.693ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 12.252m | 18.234ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 14.881m | 22.313ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 17.949m | 10.618ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 19.244m | 30.085ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 1.222h | 14.831ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 1.082h | 29.358ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 1.210h | 15.041ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 52.608m | 11.082ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 1.255h | 16.369ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 1.119h | 16.306ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 1.316h | 15.707ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 1.112h | 15.337ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 59.368m | 11.918ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 1.239h | 15.774ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 1.231h | 16.071ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 1.285h | 15.841ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 1.268h | 14.888ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 1.580h | 18.750ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 2.234h | 24.431ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 2.122h | 24.029ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 2.210h | 24.614ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 2.139h | 23.822ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 1.582h | 18.389ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 2.067h | 23.368ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 2.127h | 24.065ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 1.986h | 23.424ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 1.904h | 22.758ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 48.519m | 11.948ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 1.188h | 14.760ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 1.102h | 15.126ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 1.206h | 15.073ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 1.045h | 14.602ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 50.654m | 11.867ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 1.151h | 14.945ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 1.051h | 15.193ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 1.067h | 14.978ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 58.847m | 13.842ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 54.633m | 11.873ms | 3 | 3 | 100.00 |
| rom_e2e_asm_init_dev | 1.286h | 15.704ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod | 1.272h | 15.845ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod_end | 1.244h | 15.109ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_rma | 1.317h | 14.934ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 1.211h | 15.534ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 1.241h | 15.357ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 1.233h | 15.351ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 1.368h | 17.021ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 5.519m | 3.346ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 5.873m | 2.836ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_multi_block | chip_sw_aes_multi_block | 0 | 0 | -- | ||
| V2 | chip_sw_aes_interrupt_encryption | chip_sw_aes_interrupt_encryption | 0 | 0 | -- | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 4.716m | 2.922ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_prng_reseed | chip_sw_aes_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_force_prng_reseed | chip_sw_aes_force_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 4.098m | 2.489ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 29.144m | 9.481ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 9.386m | 19.431ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 9.386m | 19.431ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 8.088m | 4.382ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 8.955m | 5.592ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 8.088m | 4.382ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 14.320m | 9.170ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 14.320m | 9.170ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 9.151m | 6.687ms | 5 | 5 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 10.997m | 5.232ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 17.240m | 6.039ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 4.098m | 2.489ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 5.507m | 2.614ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 5.008m | 3.460ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 9.798m | 5.988ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 7.760m | 4.682ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 8.025m | 4.991ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 9.648m | 4.038ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 24.691m | 13.090ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 10.224m | 3.439ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 10.139m | 3.866ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.643m | 4.270ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 13.697m | 5.460ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.370m | 4.308ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.515m | 5.593ms | 3 | 3 | 100.00 | ||
| chip_sw_ast_clk_outputs | 15.417m | 7.199ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 16.549m | 10.352ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.643m | 4.270ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 13.697m | 5.460ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 11.471m | 4.699ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 17.523m | 5.749ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.276h | 18.027ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.873m | 2.836ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 15.879m | 6.571ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 4.713m | 2.304ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 32.413m | 9.204ms | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.503m | 3.385ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.403m | 5.147ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 3.904m | 2.302ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 3.840m | 2.816ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 11.125m | 4.807ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 17.723m | 6.818ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.392h | 24.242ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 4.555m | 3.206ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 4.429m | 2.794ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 34.447m | 13.332ms | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 5.508m | 3.693ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 9.103m | 5.215ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 37.071m | 20.774ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 1.372h | 22.142ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 15.417m | 7.199ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 10.030m | 4.291ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 7.891m | 3.735ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 14.166m | 6.185ms | 98 | 100 | 98.00 |
| V2 | chip_sw_clkmgr_alert_handler_clock_enables | chip_sw_alert_handler_lpg_clkoff | 31.615m | 8.661ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 32.179m | 8.344ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 6.959m | 3.769ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 12.344m | 6.741ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 4.431m | 2.448ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 20.976m | 7.888ms | 3 | 3 | 100.00 |
| chip_sw_sysrst_ctrl_reset | 29.071m | 21.981ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 6.003m | 3.257ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 7.463m | 3.798ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 10.461m | 4.789ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 29.071m | 21.981ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 29.071m | 21.981ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.025h | 20.997ms | 2 | 3 | 66.67 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.025h | 20.997ms | 2 | 3 | 66.67 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 10.664m | 6.726ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 9.386m | 19.431ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 2.084h | 26.038ms | 10 | 10 | 100.00 |
| chip_sw_entropy_src_ast_rng_req | 3.760m | 2.834ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs | 19.116m | 7.156ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 3.760m | 2.834ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 32.179m | 8.344ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.801m | 3.096ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fw_observe_many_contiguous | chip_sw_entropy_src_fw_observe_many_contiguous | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_fw_extract_and_insert | chip_sw_entropy_src_fw_extract_and_insert | 0 | 0 | -- | ||
| V2 | chip_sw_flash_init | chip_sw_flash_init | 35.667m | 18.936ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 17.250m | 6.060ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 17.523m | 5.749ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 12.165m | 4.552ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 11.471m | 4.699ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.835h | 44.476ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 35.667m | 18.936ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 6.877m | 3.110ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 42.522m | 12.339ms | 0 | 3 | 0.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.111m | 4.758ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.835h | 44.476ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.111m | 4.758ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.111m | 4.758ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 9.111m | 4.758ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.111m | 4.758ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 14.166m | 6.185ms | 98 | 100 | 98.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 9.037m | 13.187ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 17.689m | 5.247ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 10.911m | 5.322ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_write_clear | chip_sw_flash_crash_alert | 10.911m | 5.322ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 6.097m | 3.187ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 4.713m | 2.304ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 5.507m | 2.614ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_all_configurations | chip_sw_hmac_oneshot | 5.677m | 2.294ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_multistream_mode | chip_sw_hmac_multistream | 32.709m | 8.004ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 13.428m | 5.412ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 13.085m | 4.669ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 14.411m | 5.308ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 11.137m | 4.990ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 42.522m | 12.339ms | 0 | 3 | 0.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 32.413m | 9.204ms | 0 | 3 | 0.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 41.580m | 12.761ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 29.144m | 9.481ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 1.147h | 14.860ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 3.644m | 2.450ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 5.554m | 2.780ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.503m | 3.385ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 42.522m | 12.339ms | 0 | 3 | 0.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 21.300m | 10.600ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 5.095m | 2.445ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 5.222m | 2.613ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 5.008m | 3.460ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 10.890m | 5.380ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 31.828m | 15.338ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 13.295m | 7.716ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 17.236m | 10.151ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 6.030m | 3.307ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 21.300m | 10.600ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 21.300m | 10.600ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 21.300m | 10.600ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 42.856m | 12.108ms | 0 | 3 | 0.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 9.111m | 4.758ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.835h | 44.476ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 10.913m | 4.752ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 19.799m | 7.381ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 22.247m | 7.051ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 18.178m | 7.790ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 21.300m | 10.600ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 42.522m | 12.339ms | 0 | 3 | 0.00 | ||
| chip_sw_rom_ctrl_integrity_check | 11.042m | 8.785ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 19.251m | 10.733ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 9.037m | 13.187ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 16.549m | 10.352ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 10.224m | 3.439ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 10.139m | 3.866ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.643m | 4.270ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 13.697m | 5.460ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.370m | 4.308ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 11.515m | 5.593ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 31.828m | 15.338ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 13.295m | 7.716ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 17.236m | 10.151ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 11.848m | 16.562ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 6.534m | 4.119ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 3.695m | 4.272ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 3.259m | 3.916ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 4.375m | 3.747ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 42.106m | 33.364ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 11.848m | 16.562ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.870h | 50.826ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.943h | 51.400ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 16.266m | 9.231ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.979h | 45.578ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 42.106m | 33.364ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 2.063m | 2.920ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 2.033m | 2.329ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 2.947m | 2.747ms | 3 | 3 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 21.300m | 10.600ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 35.667m | 18.936ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 9.333m | 3.668ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 42.522m | 12.339ms | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 11.687m | 5.179ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.443m | 2.535ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 35.667m | 18.936ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 9.333m | 3.668ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 42.522m | 12.339ms | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 11.687m | 5.179ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.443m | 2.535ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 21.300m | 10.600ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 9.567m | 6.047ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 6.030m | 3.307ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 10.913m | 4.752ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 19.799m | 7.381ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 22.247m | 7.051ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 18.178m | 7.790ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 21.300m | 10.600ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 9.037m | 13.187ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 9.037m | 13.187ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_dai_lock | chip_sw_otp_ctrl_dai_lock | 1.814h | 26.873ms | 1 | 1 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 7.201m | 7.652ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 30.729m | 24.531ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 8.470m | 7.440ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_por_reset | chip_sw_pwrmgr_deep_sleep_por_reset | 13.902m | 9.337ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_por_reset | chip_sw_pwrmgr_normal_sleep_por_reset | 10.898m | 7.096ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 22.887m | 20.988ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 24.819m | 17.100ms | 3 | 3 | 100.00 |
| chip_sw_aon_timer_wdog_bite_reset | 14.320m | 9.170ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 24.620m | 10.731ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 10.506m | 5.455ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 7.201m | 7.652ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 8.567m | 4.067ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 46.017m | 27.410ms | 1 | 3 | 33.33 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 9.231m | 7.580ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 5.606m | 2.367ms | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 40.856m | 19.892ms | 2 | 3 | 66.67 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 20.976m | 7.888ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_all_reset_reqs | 28.976m | 11.899ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 54.888m | 32.626ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 4.877m | 3.445ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 14.166m | 6.185ms | 98 | 100 | 98.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 11.042m | 8.785ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 11.042m | 8.785ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_all_reset_reqs | 28.976m | 11.899ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 40.856m | 19.892ms | 2 | 3 | 66.67 | ||
| chip_sw_pwrmgr_wdog_reset | 10.506m | 5.455ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 8.955m | 5.592ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 8.463m | 5.377ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 13.939m | 6.532ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 8.528m | 4.786ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 34.975m | 14.696ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 4.885m | 2.800ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 14.166m | 6.185ms | 98 | 100 | 98.00 |
| V2 | chip_sw_rstmgr_alert_handler_reset_enables | chip_sw_alert_handler_lpg_reset_toggle | 28.192m | 7.858ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 18.648m | 6.126ms | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 9.302m | 4.350ms | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_20 | 13.587m | 5.322ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 4.465m | 3.204ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 5.776m | 3.771ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | rom_e2e_smoke | 1.222h | 14.831ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 13.786m | 8.047ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 10.139m | 4.742ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 6.459m | 3.596ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 4.343m | 2.985ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 11.687m | 5.179ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.403m | 5.147ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents_no_scramble | 11.931m | 7.432ms | 3 | 3 | 100.00 |
| chip_sw_sleep_sram_ret_contents_scramble | 13.900m | 6.596ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 19.251m | 10.733ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 14.166m | 6.185ms | 98 | 100 | 98.00 |
| chip_sw_data_integrity_escalation | 16.530m | 6.711ms | 6 | 6 | 100.00 | ||
| V2 | chip_sw_usbdev_mem | chip_sw_usbdev_mem | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_vbus | chip_sw_usbdev_vbus | 2.829m | 2.730ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pullup | chip_sw_usbdev_pullup | 3.185m | 3.001ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_aon_pullup | chip_sw_usbdev_aon_pullup | 8.194m | 3.864ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_sof | chip_sw_usbdev_sof | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_setup_rx | chip_sw_usbdev_setuprx | 8.286m | 4.109ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_config_host | chip_sw_usbdev_config_host | 26.647m | 8.266ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pincfg | chip_sw_usbdev_pincfg | 2.348h | 31.690ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_tx_rx | chip_sw_usbdev_dpi | 46.453m | 12.193ms | 1 | 1 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 6.507m | 3.920ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 10.890m | 5.380ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalation_nmi_reset | chip_sw_alert_handler_escalation_nmi_reset | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalation_methods | chip_sw_alert_handler_escalation_methods | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 14.166m | 6.185ms | 98 | 100 | 98.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 6.207m | 3.419ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 34.975m | 14.696ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 9.866m | 5.357ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 8.464m | 3.999ms | 88 | 90 | 97.78 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 26.592m | 12.781ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 31.615m | 8.661ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 28.192m | 7.858ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_ok | chip_sw_alert_handler_ping_ok | 24.911m | 8.004ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.405h | 255.028ms | 1 | 3 | 33.33 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 20.685m | 12.757ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 24.501m | 14.385ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 8.463m | 5.377ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 8.856m | 5.114ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 7.534m | 5.840ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 13.295m | 7.716ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 11.848m | 16.562ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_jtag | chip_rv_dm_jtag | 0 | 0 | -- | ||
| V2 | chip_rv_dm_dtm | chip_rv_dm_dtm | 0 | 0 | -- | ||
| V2 | chip_rv_dm_control_status | chip_rv_dm_control_status | 0 | 0 | -- | ||
| V2 | TOTAL | 2614 | 2644 | 98.87 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 5.172m | 2.457ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 0 | 1 | 0.00 | ||
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 23.672m | 5.574ms | 3 | 3 | 100.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 38.926m | 10.219ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 36.062m | 10.913ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 33.543m | 11.094ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 1.074h | 30.012ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 1.023h | 41.957ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 1.024h | 44.751ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 2.064h | 26.264ms | 3 | 3 | 100.00 |
| V3 | manuf_cp_unlock_raw | manuf_cp_unlock_raw | 0 | 0 | -- | ||
| V3 | manuf_scrap | manuf_scrap | 0 | 0 | -- | ||
| V3 | manuf_cp_yield_test | manuf_cp_yield_test | 0 | 0 | -- | ||
| V3 | manuf_cp_ast_test_execution | manuf_cp_ast_test_execution | 0 | 0 | -- | ||
| V3 | manuf_cp_device_info_flash_wr | manuf_cp_device_info_flash_wr | 0 | 0 | -- | ||
| V3 | manuf_cp_test_lock | manuf_cp_test_lock | 0 | 0 | -- | ||
| V3 | manuf_ft_exit_token | manuf_ft_exit_token | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization_preop | manuf_ft_sku_individualization_preop | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization | manuf_ft_sku_individualization | 0 | 0 | -- | ||
| V3 | manuf_ft_provision_rma_token_and_personalization | manuf_ft_provision_rma_token_and_personalization | 0 | 0 | -- | ||
| V3 | manuf_ft_load_transport_image | manuf_ft_load_transport_image | 0 | 0 | -- | ||
| V3 | manuf_ft_load_certificates | manuf_ft_load_certificates | 0 | 0 | -- | ||
| V3 | manuf_ft_eom | manuf_ft_eom | 0 | 0 | -- | ||
| V3 | manuf_rma_entry | manuf_rma_entry | 0 | 0 | -- | ||
| V3 | manuf_sram_program_crc_functest | manuf_sram_program_crc_functest | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_normal | chip_sw_adc_ctrl_normal | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_oneshot | chip_sw_adc_ctrl_oneshot | 0 | 0 | -- | ||
| V3 | chip_sw_clkmgr_jitter_cycle_measurements | chip_sw_clkmgr_jitter_frequency | 8.174m | 3.452ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_boot_mode | chip_sw_edn_boot_mode | 8.887m | 2.838ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_auto_mode | chip_sw_edn_auto_mode | 23.463m | 5.617ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_sw_mode | chip_sw_edn_sw_mode | 38.047m | 9.431ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_kat | chip_sw_edn_kat | 11.484m | 3.059ms | 3 | 3 | 100.00 |
| V3 | chip_sw_entropy_src_bypass_mode_health_tests | chip_sw_entropy_src_bypass_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_fips_mode_health_tests | chip_sw_entropy_src_fips_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_validation | chip_sw_entropy_src_validation | 0 | 0 | -- | ||
| V3 | chip_sw_flash_memory_protection | chip_sw_flash_ctrl_mem_protection | 18.439m | 5.636ms | 3 | 3 | 100.00 |
| V3 | chip_sw_hmac_sha2_stress | chip_sw_hmac_sha2_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_stress | chip_sw_hmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_endianness | chip_sw_hmac_endianness | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_secure_wipe | chip_sw_hmac_secure_wipe | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_error_conditions | chip_sw_hmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_speed | chip_sw_i2c_speed | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_override | chip_sw_i2c_override | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_clockstretching | chip_sw_i2c_clockstretching | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_nack | chip_sw_i2c_nack | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_repeatedstart | chip_sw_i2c_repeatedstart | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_attestation | chip_sw_keymgr_derive_attestation | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_sealing | chip_sw_keymgr_derive_sealing | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_sha3_stress | chip_sw_kmac_sha3_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_shake_stress | chip_sw_kmac_shake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_cshake_stress | chip_sw_kmac_cshake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_stress | chip_sw_kmac_kmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_key_sideload | chip_sw_kmac_kmac_key_sideload | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_endianess | chip_sw_kmac_endianess | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_entropy_stress | chip_sw_kmac_entropy_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_error_conditions | chip_sw_kmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_debug_access | chip_sw_lc_ctrl_debug_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 4.820m | 2.980ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 7.988m | 4.360ms | 1 | 1 | 100.00 |
| V3 | otp_ctrl_calibration | otp_ctrl_calibration | 0 | 0 | -- | ||
| V3 | otp_ctrl_partition_access_locked | otp_ctrl_partition_access_locked | 0 | 0 | -- | ||
| V3 | otp_ctrl_check_timeout | otp_ctrl_check_timeout | 0 | 0 | -- | ||
| V3 | chip_sw_sensor_ctrl_deep_sleep_wake_up | chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 9.815m | 6.076ms | 3 | 3 | 100.00 |
| V3 | chip_sw_pwrmgr_usb_clk_disabled_when_active | chip_sw_pwrmgr_usb_clk_disabled_when_active | 8.120m | 4.160ms | 3 | 3 | 100.00 |
| V3 | chip_sw_all_resets | chip_sw_pwrmgr_all_reset_reqs | 28.976m | 11.899ms | 3 | 3 | 100.00 |
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_digests | chip_sw_rom_ctrl_digests | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 14.166m | 6.185ms | 98 | 100 | 98.00 |
| V3 | tick_configuration | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | counter_wrap | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | chip_sw_spi_device_pass_through_flash_model | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_pinmux_sleep_retention | 4.890m | 3.453ms | 3 | 3 | 100.00 |
| V3 | chip_sw_spi_host_pass_through | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_configuration | //sw/device/tests:spi_host_config_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_events | chip_sw_spi_host_events | 0 | 0 | -- | ||
| V3 | chip_sw_sram_memset | chip_sw_sram_memset | 0 | 0 | -- | ||
| V3 | chip_sw_sram_readback | chip_sw_sram_readback | 0 | 0 | -- | ||
| V3 | chip_sw_sram_subword_access | chip_sw_sram_subword_access | 0 | 0 | -- | ||
| V3 | chip_sw_uart_parity | chip_sw_uart_parity | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_loopback | chip_sw_uart_line_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_system_loopback | chip_sw_uart_system_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_break | chip_sw_uart_line_break | 0 | 0 | -- | ||
| V3 | chip_sw_uart_watermarks | chip_sw_uart_tx_rx | 12.571m | 4.514ms | 5 | 5 | 100.00 |
| V3 | chip_sw_usbdev_stream | chip_sw_usbdev_stream | 1.376h | 18.815ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usbdev_iso | chip_sw_usbdev_iso | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_mixed | chip_sw_usbdev_mixed | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_suspend_resume | chip_sw_usbdev_suspend_resume | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_reset | chip_sw_usbdev_aon_wake_reset | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_disconnect | chip_sw_usbdev_aon_wake_disconnect | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_toggle_restore | chip_sw_usbdev_toggle_restore | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 38.926m | 10.219ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 36.062m | 10.913ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 33.543m | 11.094ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 11.230m | 5.195ms | 3 | 3 | 100.00 |
| V3 | TOTAL | 47 | 51 | 92.16 | |||
| Unmapped tests | chip_sival_flash_info_access | 5.186m | 3.620ms | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 12.050m | 5.962ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_ecc_error_vendor_test | 5.504m | 3.345ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_descrambling | 9.871m | 4.709ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq | 1.239h | 17.871ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_rnd | 16.621m | 5.619ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_nmi_irq | 14.652m | 5.042ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_lowpower_cancel | 6.874m | 3.615ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 8.504m | 5.561ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_address_translation | 5.058m | 3.812ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 2.455m | 2.040ms | 1 | 3 | 33.33 | ||
| chip_sw_flash_ctrl_write_clear | 5.999m | 2.713ms | 3 | 3 | 100.00 | ||
| TOTAL | 2913 | 2954 | 98.61 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 12 | 12 | 11 | 91.67 |
| V1 | 18 | 18 | 16 | 88.89 |
| V2 | 285 | 270 | 256 | 89.82 |
| V2S | 1 | 1 | 1 | 100.00 |
| V3 | 90 | 23 | 21 | 23.33 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 95.81 | 95.32 | 93.12 | 95.43 | -- | 93.85 | 97.57 | 99.57 |
Job timed out after * minutes has 13 failures:
Test chip_csr_aliasing has 4 failures.
0.chip_csr_aliasing.81999021734105902149393720554012438592706322213860522944131297873563502854562
Log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
Job timed out after 180 minutes
1.chip_csr_aliasing.8513821972112906592963302997842845127167999887365165218425263690728587791019
Log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
Job timed out after 180 minutes
... and 2 more failures.
Test chip_sw_exit_test_unlocked_bootstrap has 2 failures.
0.chip_sw_exit_test_unlocked_bootstrap.18549258421737069930734869107568693577992986983094459439924858826373355582201
Log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
Job timed out after 220 minutes
1.chip_sw_exit_test_unlocked_bootstrap.38232844540654258115835311267344951472866952122627174488239035492317573071786
Log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/1.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
Job timed out after 220 minutes
Test chip_sw_rv_timer_systick_test has 3 failures.
0.chip_sw_rv_timer_systick_test.75133795662675529525681259954486719577039057503075006992288890381325777495558
Log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
Job timed out after 120 minutes
1.chip_sw_rv_timer_systick_test.52581387863301858688848833271359311122168606343963594834784371583148160771878
Log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
Job timed out after 120 minutes
... and 1 more failures.
Test chip_sw_alert_handler_reverse_ping_in_deep_sleep has 2 failures.
0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.107218049463686603474034156084530945083809446153493222488800884683327288166239
Log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
Job timed out after 240 minutes
1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.85782267011142360339306374027471500786423720004376837863731127656770998516207
Log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
Job timed out after 240 minutes
Test chip_sw_coremark has 1 failures.
0.chip_sw_coremark.29985625505579148959091530706737391462244745656429519208073348728849334311662
Log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
Job timed out after 300 minutes
... and 1 more tests.
Offending '$stable(key_data_i)' has 12 failures:
0.chip_sw_keymgr_key_derivation.46295257851017052898966360340529437614247216365173144605913232831690830726854
Line 445, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 12339.106490 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 12339.106490 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_key_derivation.32685517700973642434687506515486436092118019433502458679317497674398778924831
Line 454, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 6244.965784 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 6244.965784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_keymgr_key_derivation_prod.91787106196311070477837792423233245145468355706308738285817187408308690646874
Line 442, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_prod/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 12736.327828 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 12736.327828 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_key_derivation_prod.41540035936704737714901641893412227218318151403619283276569625330845899735042
Line 448, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_prod/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 12108.029808 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 12108.029808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_keymgr_key_derivation_jitter_en.37221458904296010564589107675745653408851129339792968782523878378354559952798
Line 442, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 9136.249076 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 9136.249076 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_key_derivation_jitter_en.3384962538108976128623423270724954995774563586310053354212724021316948573644
Line 443, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_jitter_en/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 9664.342854 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 9664.342854 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.6007218678478479918835814439384213603547538918336132103992809382653842632872
Line 476, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 13332.230603 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 13332.230603 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.49962769964296921314557988073946903001427291327738216785623130286793379040923
Line 492, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest/run.log
Offending '$stable(key_data_i)'
UVM_ERROR @ 11623.492234 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 11623.492234 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A has 5 failures:
0.chip_sw_pwrmgr_sleep_power_glitch_reset.1975039726970734639150200176958008481488224974053585028208585070578472159330
Line 443, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 3253.973664 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 3253.973664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_pwrmgr_sleep_power_glitch_reset.50868243542798904021021088734769664029272376973776446113795827151627372334775
Line 425, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 2842.955211 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 2842.955211 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.86625152387025950119369018671866291425940574778975143685816854704381045281732
Line 453, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 4310.991098 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 4310.991098 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.8686640119989833751667435996905238729407200378537106917213377512535114401217
Line 486, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 23137.354230 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 23137.354230 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 2 failures:
1.chip_sw_sleep_pin_mio_dio_val.66905640825179481736362035370670508718440089219874379013931273606006964282880
Line 591, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_mio_dio_val/latest/run.log
UVM_ERROR @ 2779.450000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
UVM_INFO @ 2779.450000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.chip_sw_sleep_pin_mio_dio_val.60823917660196528826084652606355410535899599136806399710721602881687029588607
Line 557, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_mio_dio_val/latest/run.log
UVM_ERROR @ 3214.832000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
UVM_INFO @ 3214.832000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 2 failures:
44.chip_sw_all_escalation_resets.73571422714890130835921647040227045827030095058570003335745523588453641711926
Line 444, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/44.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 3344.576884 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3344.576884 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
85.chip_sw_all_escalation_resets.92963565952402100526533626805104911033746238721623070304858762768678436531234
Line 463, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/85.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 2777.922820 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 2777.922820 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 2 failures:
84.chip_sw_alert_handler_lpg_sleep_mode_alerts.108564122554465560964184827385197765435675981742094376271697575189988323840934
Line 477, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 3683.809772 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=2000371c MTVAL=40600800
UVM_INFO @ 3683.809772 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
86.chip_sw_alert_handler_lpg_sleep_mode_alerts.6960446568067619649397478760331212233963977562988417419838524222216550864561
Line 440, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 3650.275704 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=2000371c MTVAL=40600800
UVM_INFO @ 3650.275704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
0.chip_sw_rv_core_ibex_lockstep_glitch.58281152528247353854093009122631148611294147165910998770482551644619024269062
Line 430, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 2588.992774 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2588.992774 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.23330994926578860265280931332018492689935731216194235112557380320960635458282
Line 479, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
Offending '(pend_req[h2d.a_source].pend == 0)'
UVM_ERROR @ 15434.661256 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
UVM_INFO @ 15434.661256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_sysrst_ctrl_ec_rst_l_vseq.sv:138) [chip_sw_sysrst_ctrl_ec_rst_l_vseq] Timed out waiting for ec_rst to go high. has 1 failures:
2.chip_sw_sysrst_ctrl_ec_rst_l.29104667154573958572019930150681490842659403968240621418686061068090620322606
Line 410, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/2.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
UVM_FATAL @ 5010.240001 us: (chip_sw_sysrst_ctrl_ec_rst_l_vseq.sv:138) [uvm_test_top.env.virtual_sequencer.chip_sw_sysrst_ctrl_ec_rst_l_vseq] Timed out waiting for ec_rst to go high.
UVM_INFO @ 5010.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:708) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (x [0xx] vs * [*]) Major alert unexpectedly fired in cycle *. has 1 failures:
2.chip_sw_rv_core_ibex_lockstep_glitch.91803454672261943409532875595076568128330768779782112351988381170183101478367
Line 425, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 1393.412852 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:708) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (x [0xx] vs 0 [0x0]) Major alert unexpectedly fired in cycle 0.
UVM_INFO @ 1393.412852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' has 1 failures:
4.chip_csr_hw_reset.59214435594471324104289318444972814279609727028680101924441334425965608430657
Line 253, in log /workspaces/repo/scratch/os_regression_2024_10_11/chip_earlgrey_asic-sim-vcs/4.chip_csr_hw_reset/latest/run.log
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
UVM_ERROR @ 3760.669628 us: (alert_esc_if.sv:189) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 3760.669628 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---