25b1acbf68| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_example_tests | chip_sw_example_flash | 3.865m | 3.250ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.837m | 2.050ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 4.185m | 2.407ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 5.309m | 2.899ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 6.201m | 7.350ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 13.084m | 6.075ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 1.256h | 43.831ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 2.622h | 55.834ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 21.260m | 12.383ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.622h | 55.834ms | 5 | 5 | 100.00 |
| chip_csr_rw | 13.084m | 6.075ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 16.080s | 234.900us | 100 | 100 | 100.00 |
| V1 | chip_sw_gpio_out | chip_sw_gpio | 8.888m | 4.166ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 8.888m | 4.166ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 8.888m | 4.166ms | 3 | 3 | 100.00 |
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 10.959m | 4.483ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 10.959m | 4.483ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 11.880m | 4.587ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 10.436m | 4.189ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 12.581m | 5.084ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_baud_rate | chip_sw_uart_rand_baudrate | 47.390m | 12.719ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 47.580m | 12.898ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 30.511m | 13.639ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 220 | 220 | 100.00 | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 4.287m | 5.281ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 4.287m | 5.281ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 4.676m | 2.653ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 5.311m | 2.855ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 5.353m | 3.962ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 16.607m | 10.713ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 8.578m | 5.926ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 8.028m | 5.572ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 29.884m | 18.920ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 5.433m | 3.199ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 21.064m | 8.887ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 13.098m | 5.005ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 13.098m | 5.005ms | 6 | 6 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 16.469m | 8.321ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 47.266m | 19.175ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 10.689m | 4.714ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 16.690m | 5.620ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.230h | 18.264ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.707m | 3.302ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 19.949m | 6.413ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 4.632m | 2.633ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 26.020m | 9.510ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.814m | 2.528ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.470m | 6.226ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 5.336m | 2.438ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 5.605m | 3.340ms | 1 | 1 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 14.502m | 5.177ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 8.261m | 5.831ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 4.438m | 3.318ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 8.261m | 5.831ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 3.006m | 2.510ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 5.725m | 2.864ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 7.110m | 3.359ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 5.467m | 2.419ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 4.979m | 3.004ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 7.500m | 3.704ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 5.441m | 3.322ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 6.434m | 3.864ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 6.147m | 2.609ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 43.925m | 10.413ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 8.825m | 6.065ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 7.866m | 5.827ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 4.568m | 3.153ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 4.557m | 2.515ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 4.443m | 3.429ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 5.673m | 3.575ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 5.116m | 3.306ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_smoketest | chip_sw_otp_ctrl_smoketest | 4.518m | 2.977ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 13.236m | 5.819ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 5.286h | 81.200ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 1.246h | 15.579ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 5.787m | 4.877ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 9.049m | 4.694ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 8.000m | 11.159ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 3.443h | 62.246ms | 1 | 3 | 33.33 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 4.322h | 68.415ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 8.392m | 4.489ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 8.392m | 4.489ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.622h | 55.834ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 1.144h | 30.835ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 6.201m | 7.350ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 13.084m | 6.075ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 2.622h | 55.834ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 1.144h | 30.835ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 6.201m | 7.350ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 13.084m | 6.075ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.953m | 2.684ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 10.550s | 52.889us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 2.762m | 10.415ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 2.718m | 6.729ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 1.111m | 599.883us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 20.691m | 93.999ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 19.798m | 71.229ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.366m | 1.503ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.019m | 1.370ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.825m | 2.657ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.019m | 1.370ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 2.353m | 2.598ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 46.358m | 146.339ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.890m | 2.662ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 10.874m | 17.512ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 10.342m | 17.862ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 20.479m | 11.319ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 15.602m | 15.167ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 1.246h | 15.579ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 1.108h | 31.612ms | 2 | 3 | 66.67 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 1.185h | 14.267ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 53.713m | 10.979ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 1.186h | 15.664ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 1.187h | 15.984ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 1.290h | 15.434ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 1.136h | 14.584ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 58.315m | 11.546ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 1.108h | 15.704ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 1.199h | 15.718ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 1.203h | 16.089ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 1.121h | 14.761ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 1.640h | 18.628ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 2.155h | 25.028ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 2.087h | 24.296ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 2.042h | 24.036ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 2.126h | 23.175ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 1.601h | 18.154ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 1.884h | 23.424ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 1.895h | 24.146ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 1.823h | 24.399ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 1.955h | 22.641ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 52.998m | 11.896ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 1.102h | 14.564ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 1.084h | 14.724ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 1.108h | 14.596ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 1.150h | 14.251ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 49.182m | 10.918ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 1.189h | 15.562ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 1.088h | 15.336ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 1.087h | 14.809ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 1.118h | 14.553ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 55.061m | 11.360ms | 3 | 3 | 100.00 |
| rom_e2e_asm_init_dev | 1.359h | 15.371ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod | 1.300h | 16.204ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod_end | 1.195h | 15.747ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_rma | 1.213h | 15.432ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 1.175h | 15.095ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 1.139h | 14.993ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 1.147h | 15.092ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 1.436h | 17.480ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 5.326m | 3.103ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 5.707m | 3.302ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_multi_block | chip_sw_aes_multi_block | 0 | 0 | -- | ||
| V2 | chip_sw_aes_interrupt_encryption | chip_sw_aes_interrupt_encryption | 0 | 0 | -- | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 4.733m | 3.191ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_prng_reseed | chip_sw_aes_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_force_prng_reseed | chip_sw_aes_force_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 4.106m | 2.853ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 39.325m | 11.426ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.904m | 19.167ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.904m | 19.167ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 8.345m | 3.932ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 8.825m | 6.065ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 8.345m | 3.932ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 16.415m | 10.120ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 16.415m | 10.120ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 8.561m | 7.793ms | 5 | 5 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 11.193m | 5.107ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 16.809m | 5.954ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 4.106m | 2.853ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 4.525m | 2.842ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 5.196m | 3.044ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 8.104m | 5.196ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 6.788m | 4.693ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 9.053m | 4.731ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 8.917m | 4.706ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 21.500m | 9.210ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.332m | 4.338ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.681m | 5.570ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.004m | 3.807ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.619m | 4.747ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.352m | 4.777ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 10.608m | 5.628ms | 3 | 3 | 100.00 | ||
| chip_sw_ast_clk_outputs | 16.469m | 8.321ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 14.167m | 11.828ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.004m | 3.807ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.619m | 4.747ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 10.689m | 4.714ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 16.690m | 5.620ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.230h | 18.264ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.707m | 3.302ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 19.949m | 6.413ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 4.632m | 2.633ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 26.020m | 9.510ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.814m | 2.528ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.470m | 6.226ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 5.336m | 2.438ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 4.540m | 3.469ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 10.775m | 5.142ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 17.998m | 7.617ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.399h | 25.336ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 4.478m | 3.474ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 4.053m | 3.138ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 20.619m | 9.448ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 5.252m | 3.903ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 8.127m | 4.708ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 37.335m | 22.068ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 4.871h | 81.654ms | 1 | 3 | 33.33 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 16.469m | 8.321ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 9.248m | 4.607ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 8.000m | 3.533ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 13.192m | 5.604ms | 95 | 100 | 95.00 |
| V2 | chip_sw_clkmgr_alert_handler_clock_enables | chip_sw_alert_handler_lpg_clkoff | 28.022m | 8.073ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 25.999m | 7.756ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 8.649m | 4.945ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 12.154m | 5.540ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 6.160m | 3.195ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 20.188m | 8.021ms | 3 | 3 | 100.00 |
| chip_sw_sysrst_ctrl_reset | 32.517m | 24.247ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 5.378m | 2.891ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 7.451m | 4.132ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 11.317m | 4.528ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 32.517m | 24.247ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 32.517m | 24.247ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 56.652m | 20.592ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 56.652m | 20.592ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 7.767m | 5.950ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.904m | 19.167ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 2.089h | 26.568ms | 10 | 10 | 100.00 |
| chip_sw_entropy_src_ast_rng_req | 4.630m | 2.347ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs | 21.372m | 7.315ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 4.630m | 2.347ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 25.999m | 7.756ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.597m | 3.066ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fw_observe_many_contiguous | chip_sw_entropy_src_fw_observe_many_contiguous | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_fw_extract_and_insert | chip_sw_entropy_src_fw_extract_and_insert | 0 | 0 | -- | ||
| V2 | chip_sw_flash_init | chip_sw_flash_init | 34.247m | 23.759ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 17.237m | 5.621ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 16.690m | 5.620ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 10.764m | 4.651ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 10.689m | 4.714ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.647h | 42.985ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 34.247m | 23.759ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 6.539m | 3.834ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 39.004m | 11.178ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 7.489m | 5.072ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.647h | 42.985ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 7.489m | 5.072ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 7.489m | 5.072ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 7.489m | 5.072ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 7.489m | 5.072ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 13.192m | 5.604ms | 95 | 100 | 95.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 5.989m | 7.613ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 16.413m | 5.407ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 10.515m | 5.014ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_write_clear | chip_sw_flash_crash_alert | 10.515m | 5.014ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 4.782m | 3.176ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 4.632m | 2.633ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 4.525m | 2.842ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_all_configurations | chip_sw_hmac_oneshot | 6.100m | 3.184ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_multistream_mode | chip_sw_hmac_multistream | 28.182m | 8.130ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 11.229m | 4.847ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 14.095m | 5.179ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 12.479m | 5.131ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 11.025m | 4.318ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 39.004m | 11.178ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 26.020m | 9.510ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 42.140m | 13.261ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 39.325m | 11.426ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 1.189h | 17.329ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 4.500m | 2.817ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 5.780m | 2.858ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.814m | 2.528ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 39.004m | 11.178ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 17.870m | 9.968ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 5.283m | 2.736ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 4.710m | 3.365ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 5.196m | 3.044ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 11.056m | 5.395ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 16.607m | 10.713ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 8.028m | 5.572ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 29.884m | 18.920ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 5.599m | 3.340ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 17.870m | 9.968ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 17.870m | 9.968ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 17.870m | 9.968ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 47.749m | 13.469ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 7.489m | 5.072ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.647h | 42.985ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 11.519m | 4.519ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 23.745m | 9.192ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 23.694m | 7.497ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 22.308m | 7.249ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 17.870m | 9.968ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 39.004m | 11.178ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 9.742m | 9.878ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 13.133m | 9.148ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 5.989m | 7.613ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 14.167m | 11.828ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.332m | 4.338ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.681m | 5.570ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.004m | 3.807ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.619m | 4.747ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.352m | 4.777ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 10.608m | 5.628ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 16.607m | 10.713ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 8.028m | 5.572ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 29.884m | 18.920ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 10.107m | 12.067ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 3.792m | 3.368ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.346m | 3.478ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.973m | 3.336ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 4.554m | 2.849ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 46.741m | 36.644ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 10.107m | 12.067ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.753h | 48.415ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.666h | 49.484ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 16.092m | 10.225ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.936h | 46.718ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 46.741m | 36.644ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 2.309m | 2.332ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 2.224m | 2.565ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 2.265m | 2.499ms | 3 | 3 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 17.870m | 9.968ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 34.247m | 23.759ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.006m | 3.420ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 39.004m | 11.178ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 11.529m | 5.284ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.380m | 2.644ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 34.247m | 23.759ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.006m | 3.420ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 39.004m | 11.178ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 11.529m | 5.284ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.380m | 2.644ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 17.870m | 9.968ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 9.255m | 5.729ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 5.599m | 3.340ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 11.519m | 4.519ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 23.745m | 9.192ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 23.694m | 7.497ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 22.308m | 7.249ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 17.870m | 9.968ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 5.989m | 7.613ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 5.989m | 7.613ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_dai_lock | chip_sw_otp_ctrl_dai_lock | 1.643h | 26.061ms | 1 | 1 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 9.327m | 6.795ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 30.350m | 25.538ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 8.923m | 7.822ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_por_reset | chip_sw_pwrmgr_deep_sleep_por_reset | 13.306m | 10.323ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_por_reset | chip_sw_pwrmgr_normal_sleep_por_reset | 13.120m | 7.780ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 29.979m | 22.969ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 25.400m | 15.480ms | 3 | 3 | 100.00 |
| chip_sw_aon_timer_wdog_bite_reset | 16.415m | 10.120ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 22.817m | 11.908ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 9.922m | 4.519ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 9.327m | 6.795ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 7.527m | 3.849ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 41.895m | 27.976ms | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 9.686m | 7.077ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 4.277m | 3.302ms | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 45.656m | 23.540ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 20.188m | 8.021ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_all_reset_reqs | 26.710m | 13.085ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 38.914m | 29.660ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 6.241m | 2.879ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 13.192m | 5.604ms | 95 | 100 | 95.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 9.742m | 9.878ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 9.742m | 9.878ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_all_reset_reqs | 26.710m | 13.085ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 45.656m | 23.540ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_wdog_reset | 9.922m | 4.519ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 8.825m | 6.065ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 7.249m | 3.777ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 12.133m | 5.024ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 7.161m | 4.418ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 30.825m | 12.705ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 5.627m | 2.749ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 13.192m | 5.604ms | 95 | 100 | 95.00 |
| V2 | chip_sw_rstmgr_alert_handler_reset_enables | chip_sw_alert_handler_lpg_reset_toggle | 28.184m | 9.145ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 19.351m | 6.574ms | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 9.036m | 4.189ms | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_20 | 13.131m | 5.133ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 5.627m | 3.246ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 5.427m | 2.738ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | rom_e2e_smoke | 1.246h | 15.579ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 11.675m | 6.995ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 10.203m | 3.939ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 5.807m | 3.352ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 5.818m | 2.714ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 11.529m | 5.284ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.470m | 6.226ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents_no_scramble | 12.290m | 7.055ms | 3 | 3 | 100.00 |
| chip_sw_sleep_sram_ret_contents_scramble | 14.045m | 8.542ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 13.133m | 9.148ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 13.192m | 5.604ms | 95 | 100 | 95.00 |
| chip_sw_data_integrity_escalation | 13.098m | 5.005ms | 6 | 6 | 100.00 | ||
| V2 | chip_sw_usbdev_mem | chip_sw_usbdev_mem | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_vbus | chip_sw_usbdev_vbus | 4.179m | 3.074ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pullup | chip_sw_usbdev_pullup | 4.344m | 2.316ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_aon_pullup | chip_sw_usbdev_aon_pullup | 7.798m | 3.513ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_sof | chip_sw_usbdev_sof | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_setup_rx | chip_sw_usbdev_setuprx | 8.909m | 3.761ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_config_host | chip_sw_usbdev_config_host | 25.067m | 7.865ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pincfg | chip_sw_usbdev_pincfg | 2.345h | 31.527ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_tx_rx | chip_sw_usbdev_dpi | 48.930m | 11.599ms | 1 | 1 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 6.507m | 3.354ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 11.056m | 5.395ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalation_nmi_reset | chip_sw_alert_handler_escalation_nmi_reset | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalation_methods | chip_sw_alert_handler_escalation_methods | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 13.192m | 5.604ms | 95 | 100 | 95.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 5.734m | 2.825ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 30.825m | 12.705ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 8.586m | 4.962ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 8.506m | 3.872ms | 87 | 90 | 96.67 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 18.356m | 10.268ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 28.022m | 8.073ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 28.184m | 9.145ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_ok | chip_sw_alert_handler_ping_ok | 24.078m | 7.959ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.758h | 256.232ms | 1 | 3 | 33.33 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 36.133m | 18.758ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 21.841m | 13.867ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 7.249m | 3.777ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 7.843m | 5.175ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 9.301m | 6.439ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 8.028m | 5.572ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 10.107m | 12.067ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_jtag | chip_rv_dm_jtag | 0 | 0 | -- | ||
| V2 | chip_rv_dm_dtm | chip_rv_dm_dtm | 0 | 0 | -- | ||
| V2 | chip_rv_dm_control_status | chip_rv_dm_control_status | 0 | 0 | -- | ||
| V2 | TOTAL | 2623 | 2644 | 99.21 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 5.513m | 3.297ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 0 | 1 | 0.00 | ||
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 25.451m | 5.612ms | 3 | 3 | 100.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 35.728m | 12.334ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 27.214m | 11.540ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 38.838m | 11.334ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 47.747m | 31.979ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 1.205h | 31.799ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 54.996m | 41.844ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 2.112h | 26.804ms | 3 | 3 | 100.00 |
| V3 | manuf_cp_unlock_raw | manuf_cp_unlock_raw | 0 | 0 | -- | ||
| V3 | manuf_scrap | manuf_scrap | 0 | 0 | -- | ||
| V3 | manuf_cp_yield_test | manuf_cp_yield_test | 0 | 0 | -- | ||
| V3 | manuf_cp_ast_test_execution | manuf_cp_ast_test_execution | 0 | 0 | -- | ||
| V3 | manuf_cp_device_info_flash_wr | manuf_cp_device_info_flash_wr | 0 | 0 | -- | ||
| V3 | manuf_cp_test_lock | manuf_cp_test_lock | 0 | 0 | -- | ||
| V3 | manuf_ft_exit_token | manuf_ft_exit_token | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization_preop | manuf_ft_sku_individualization_preop | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization | manuf_ft_sku_individualization | 0 | 0 | -- | ||
| V3 | manuf_ft_provision_rma_token_and_personalization | manuf_ft_provision_rma_token_and_personalization | 0 | 0 | -- | ||
| V3 | manuf_ft_load_transport_image | manuf_ft_load_transport_image | 0 | 0 | -- | ||
| V3 | manuf_ft_load_certificates | manuf_ft_load_certificates | 0 | 0 | -- | ||
| V3 | manuf_ft_eom | manuf_ft_eom | 0 | 0 | -- | ||
| V3 | manuf_rma_entry | manuf_rma_entry | 0 | 0 | -- | ||
| V3 | manuf_sram_program_crc_functest | manuf_sram_program_crc_functest | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_normal | chip_sw_adc_ctrl_normal | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_oneshot | chip_sw_adc_ctrl_oneshot | 0 | 0 | -- | ||
| V3 | chip_sw_clkmgr_jitter_cycle_measurements | chip_sw_clkmgr_jitter_frequency | 7.617m | 3.805ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_boot_mode | chip_sw_edn_boot_mode | 9.498m | 3.332ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_auto_mode | chip_sw_edn_auto_mode | 27.215m | 6.358ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_sw_mode | chip_sw_edn_sw_mode | 36.051m | 9.543ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_kat | chip_sw_edn_kat | 10.361m | 3.404ms | 3 | 3 | 100.00 |
| V3 | chip_sw_entropy_src_bypass_mode_health_tests | chip_sw_entropy_src_bypass_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_fips_mode_health_tests | chip_sw_entropy_src_fips_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_validation | chip_sw_entropy_src_validation | 0 | 0 | -- | ||
| V3 | chip_sw_flash_memory_protection | chip_sw_flash_ctrl_mem_protection | 17.242m | 5.918ms | 3 | 3 | 100.00 |
| V3 | chip_sw_hmac_sha2_stress | chip_sw_hmac_sha2_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_stress | chip_sw_hmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_endianness | chip_sw_hmac_endianness | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_secure_wipe | chip_sw_hmac_secure_wipe | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_error_conditions | chip_sw_hmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_speed | chip_sw_i2c_speed | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_override | chip_sw_i2c_override | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_clockstretching | chip_sw_i2c_clockstretching | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_nack | chip_sw_i2c_nack | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_repeatedstart | chip_sw_i2c_repeatedstart | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_attestation | chip_sw_keymgr_derive_attestation | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_sealing | chip_sw_keymgr_derive_sealing | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_sha3_stress | chip_sw_kmac_sha3_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_shake_stress | chip_sw_kmac_shake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_cshake_stress | chip_sw_kmac_cshake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_stress | chip_sw_kmac_kmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_key_sideload | chip_sw_kmac_kmac_key_sideload | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_endianess | chip_sw_kmac_endianess | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_entropy_stress | chip_sw_kmac_entropy_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_error_conditions | chip_sw_kmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_debug_access | chip_sw_lc_ctrl_debug_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 2.608m | 2.205ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 10.780m | 5.486ms | 1 | 1 | 100.00 |
| V3 | otp_ctrl_calibration | otp_ctrl_calibration | 0 | 0 | -- | ||
| V3 | otp_ctrl_partition_access_locked | otp_ctrl_partition_access_locked | 0 | 0 | -- | ||
| V3 | otp_ctrl_check_timeout | otp_ctrl_check_timeout | 0 | 0 | -- | ||
| V3 | chip_sw_sensor_ctrl_deep_sleep_wake_up | chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 9.804m | 5.334ms | 3 | 3 | 100.00 |
| V3 | chip_sw_pwrmgr_usb_clk_disabled_when_active | chip_sw_pwrmgr_usb_clk_disabled_when_active | 10.225m | 4.887ms | 3 | 3 | 100.00 |
| V3 | chip_sw_all_resets | chip_sw_pwrmgr_all_reset_reqs | 26.710m | 13.085ms | 3 | 3 | 100.00 |
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_digests | chip_sw_rom_ctrl_digests | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 13.192m | 5.604ms | 95 | 100 | 95.00 |
| V3 | tick_configuration | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | counter_wrap | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | chip_sw_spi_device_pass_through_flash_model | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_pinmux_sleep_retention | 4.875m | 3.894ms | 3 | 3 | 100.00 |
| V3 | chip_sw_spi_host_pass_through | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_configuration | //sw/device/tests:spi_host_config_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_events | chip_sw_spi_host_events | 0 | 0 | -- | ||
| V3 | chip_sw_sram_memset | chip_sw_sram_memset | 0 | 0 | -- | ||
| V3 | chip_sw_sram_readback | chip_sw_sram_readback | 0 | 0 | -- | ||
| V3 | chip_sw_sram_subword_access | chip_sw_sram_subword_access | 0 | 0 | -- | ||
| V3 | chip_sw_uart_parity | chip_sw_uart_parity | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_loopback | chip_sw_uart_line_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_system_loopback | chip_sw_uart_system_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_break | chip_sw_uart_line_break | 0 | 0 | -- | ||
| V3 | chip_sw_uart_watermarks | chip_sw_uart_tx_rx | 10.959m | 4.483ms | 5 | 5 | 100.00 |
| V3 | chip_sw_usbdev_stream | chip_sw_usbdev_stream | 1.286h | 19.184ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usbdev_iso | chip_sw_usbdev_iso | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_mixed | chip_sw_usbdev_mixed | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_suspend_resume | chip_sw_usbdev_suspend_resume | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_reset | chip_sw_usbdev_aon_wake_reset | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_disconnect | chip_sw_usbdev_aon_wake_disconnect | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_toggle_restore | chip_sw_usbdev_toggle_restore | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 35.728m | 12.334ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 27.214m | 11.540ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 38.838m | 11.334ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 10.021m | 5.700ms | 3 | 3 | 100.00 |
| V3 | TOTAL | 47 | 51 | 92.16 | |||
| Unmapped tests | chip_sival_flash_info_access | 5.690m | 3.329ms | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 12.682m | 6.337ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_ecc_error_vendor_test | 5.454m | 2.907ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq | 1.200h | 16.990ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_rnd | 16.419m | 4.910ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_nmi_irq | 14.766m | 4.509ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_lowpower_cancel | 8.049m | 4.522ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 9.853m | 6.418ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_address_translation | 5.807m | 3.615ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 3.721m | 2.055ms | 2 | 3 | 66.67 | ||
| chip_sw_flash_ctrl_write_clear | 6.095m | 3.290ms | 3 | 3 | 100.00 | ||
| TOTAL | 2925 | 2951 | 99.12 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 11 | 11 | 10 | 90.91 |
| V1 | 18 | 18 | 18 | 100.00 |
| V2 | 285 | 270 | 262 | 91.93 |
| V2S | 1 | 1 | 1 | 100.00 |
| V3 | 90 | 23 | 21 | 23.33 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 95.97 | 95.43 | 93.69 | 95.30 | -- | 94.46 | 97.35 | 99.55 |
Job timed out after * minutes has 9 failures:
Test chip_sw_exit_test_unlocked_bootstrap has 2 failures.
0.chip_sw_exit_test_unlocked_bootstrap.38696359109058541759697105920555429974626985609502454985281054922000778755367
Log /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
Job timed out after 220 minutes
1.chip_sw_exit_test_unlocked_bootstrap.104679300199911869249082955252339249618404813699747821668751535186334358491700
Log /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
Job timed out after 220 minutes
Test chip_sw_rv_timer_systick_test has 3 failures.
0.chip_sw_rv_timer_systick_test.79397281497889755068730054723869840429902025537430067697520792974334241658254
Log /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
Job timed out after 120 minutes
1.chip_sw_rv_timer_systick_test.34634387106720545982051075674756736677800553457499581023084893001722828679606
Log /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
Job timed out after 120 minutes
... and 1 more failures.
Test chip_sw_alert_handler_reverse_ping_in_deep_sleep has 2 failures.
0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.78377407643148260885960494059109809519702040717080348745347107973630493308266
Log /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
Job timed out after 240 minutes
1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.73329575783235720045870975116553188142074222042611456546310790313569371749222
Log /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
Job timed out after 240 minutes
Test chip_sw_coremark has 1 failures.
0.chip_sw_coremark.62822968356322179681965154122487577406906992428810345922126137030559907137042
Log /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
Job timed out after 300 minutes
Test chip_sw_csrng_edn_concurrency_reduced_freq has 1 failures.
2.chip_sw_csrng_edn_concurrency_reduced_freq.96415801949106572575707630615385886871313066127090085339099126545371871871121
Log /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log
Job timed out after 480 minutes
UVM_ERROR @ * us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A has 6 failures:
0.chip_sw_pwrmgr_sleep_power_glitch_reset.92750026877546738487925595901110788602827562116619876228676470121990022504005
Line 410, in log /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 3302.037010 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 3302.037010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_pwrmgr_sleep_power_glitch_reset.92181963054268509209638270717283268929550603490558239852890957583068704939888
Line 412, in log /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 2234.580204 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 2234.580204 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.43940072660996616472013039734788184169174668572034753699190437573134365514917
Line 520, in log /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 27976.442605 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 27976.442605 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.16062668747474648179630479672936983210965156383713645146492243219710390504753
Line 408, in log /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
UVM_ERROR @ 9924.118439 us: (rom_ctrl_fsm.sv:209) [ASSERT FAILED] SecCmCFILinear_A
UVM_INFO @ 9924.118439 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 5 failures:
13.chip_sw_all_escalation_resets.11842092264785356357923977723534572030410400115192473068854464140074207339683
Line 399, in log /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/13.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 3198.784784 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3198.784784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.chip_sw_all_escalation_resets.22913275935599791862946858124607926383381474021712308985667018837719137526889
Line 399, in log /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/26.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 3033.655906 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3033.655906 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 3 failures:
12.chip_sw_alert_handler_lpg_sleep_mode_alerts.82085955501958368256329404169254411066106746470863924758752764056930196708332
Line 401, in log /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 3816.207372 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=2000371c MTVAL=40600800
UVM_INFO @ 3816.207372 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.chip_sw_alert_handler_lpg_sleep_mode_alerts.31580401736641816228277144868956790971479451556767429971667478055012096121871
Line 410, in log /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 3635.496560 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=2000371c MTVAL=40600800
UVM_INFO @ 3635.496560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [csrng_edn_concurrency_test_sim_dv(w/device/lib/testing/entropy_testutils.c:280)] end* error status. err: *, fifo_err: * has 1 failures:
0.chip_sw_csrng_edn_concurrency_reduced_freq.91706786475523516705574362940866814675671117454379635178044453398029158584417
Line 401, in log /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log
UVM_ERROR @ 81654.063957 us: (sw_logger_if.sv:526) [csrng_edn_concurrency_test_sim_dv(w/device/lib/testing/entropy_testutils.c:280)] end0 error status. err: 0x10, fifo_err: 0x2
UVM_INFO @ 81654.063957 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
0.rom_e2e_shutdown_output.6434312952917018142738866507682903428461225363969039923201684252066531376296
Line 553, in log /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log
Offending '(pend_req[h2d.a_source].pend == 0)'
UVM_ERROR @ 7934.987324 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
UVM_INFO @ 7934.987324 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
2.chip_sw_rv_core_ibex_lockstep_glitch.87983314728051303639831042807895979595955015577994314967425514283863739856107
Line 407, in log /workspaces/repo/scratch/os_regression_2024_09_10/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 2054.977134 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2054.977134 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---