Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_sm1_28

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.96 100.00 87.88 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.51 98.68 85.92 92.73 96.72


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 94.95 100.00 92.31 100.00 87.50
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[2].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 92.21 97.50 82.14 89.19 100.00



Module Instance : tb.dut.u_sm1_29

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.96 100.00 87.88 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 98.68 85.07 92.59 95.08


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[2].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_31

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.96 100.00 87.88 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 98.68 85.07 92.59 95.08


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[2].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_33

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_34

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_36

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.90 100.00 93.62 100.00 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sm1_38

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.90 100.00 93.62 100.00 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sm1_40

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.90 100.00 93.62 100.00 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sm1_42

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.90 100.00 93.62 100.00 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_sm1_43

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_44

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_45

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_46

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_47

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_48

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_49

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_50

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_51

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_52

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_53

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_54

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_55

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_56

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.97 100.00 90.91 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.54 84.87 92.31 94.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 93.39 100.00 92.31 100.00 81.25
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 91.66 97.50 80.26 88.89 100.00



Module Instance : tb.dut.u_sm1_30

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.78 100.00 98.39 100.00 96.72


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.70 100.00 100.00 98.80 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_arb_ppc.u_reqarb 94.95 100.00 92.31 100.00 87.50
gen_host_fifo[0].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[1].u_hostfifo 100.00 100.00 100.00 100.00 100.00
gen_host_fifo[2].u_hostfifo 100.00 100.00 100.00 100.00 100.00
u_devicefifo 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Line Coverage for Module self-instances :
SCORELINE
95.96 100.00
tb.dut.u_sm1_28

SCORELINE
95.96 100.00
tb.dut.u_sm1_29

SCORELINE
100.00 100.00
tb.dut.u_sm1_30

SCORELINE
95.96 100.00
tb.dut.u_sm1_31

Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Line Coverage for Module : tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Line Coverage for Module self-instances :
SCORELINE
96.97 100.00
tb.dut.u_sm1_33

SCORELINE
96.97 100.00
tb.dut.u_sm1_34

SCORELINE
96.97 100.00
tb.dut.u_sm1_36

SCORELINE
96.97 100.00
tb.dut.u_sm1_38

SCORELINE
96.97 100.00
tb.dut.u_sm1_40

SCORELINE
96.97 100.00
tb.dut.u_sm1_42

SCORELINE
96.97 100.00
tb.dut.u_sm1_43

SCORELINE
96.97 100.00
tb.dut.u_sm1_44

SCORELINE
96.97 100.00
tb.dut.u_sm1_45

SCORELINE
96.97 100.00
tb.dut.u_sm1_46

SCORELINE
96.97 100.00
tb.dut.u_sm1_47

SCORELINE
96.97 100.00
tb.dut.u_sm1_48

SCORELINE
96.97 100.00
tb.dut.u_sm1_49

SCORELINE
96.97 100.00
tb.dut.u_sm1_50

SCORELINE
96.97 100.00
tb.dut.u_sm1_51

SCORELINE
96.97 100.00
tb.dut.u_sm1_52

SCORELINE
96.97 100.00
tb.dut.u_sm1_53

SCORELINE
96.97 100.00
tb.dut.u_sm1_54

SCORELINE
96.97 100.00
tb.dut.u_sm1_55

SCORELINE
96.97 100.00
tb.dut.u_sm1_56

Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Module : tlul_socket_m1 ( parameter M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=2 + M=3,HReqPass=7,HRspPass=7,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=2 )
Cond Coverage for Module self-instances :
SCORECOND
95.96 87.88
tb.dut.u_sm1_28

SCORECOND
95.96 87.88
tb.dut.u_sm1_29

SCORECOND
95.96 87.88
tb.dut.u_sm1_31

SCORECOND
100.00 100.00
tb.dut.u_sm1_30

TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : tlul_socket_m1 ( parameter M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=0,DRspPass=0,DReqDepth=1,DRspDepth=1,IDW=8,STIDW=1 + M=2,HReqPass=3,HRspPass=3,HReqDepth=0,HRspDepth=0,DReqPass=1,DRspPass=1,DReqDepth=0,DRspDepth=0,IDW=8,STIDW=1 )
Cond Coverage for Module self-instances :
SCORECOND
96.97 90.91
tb.dut.u_sm1_33

SCORECOND
96.97 90.91
tb.dut.u_sm1_34

SCORECOND
96.97 90.91
tb.dut.u_sm1_43

SCORECOND
96.97 90.91
tb.dut.u_sm1_44

SCORECOND
96.97 90.91
tb.dut.u_sm1_45

SCORECOND
96.97 90.91
tb.dut.u_sm1_46

SCORECOND
96.97 90.91
tb.dut.u_sm1_47

SCORECOND
96.97 90.91
tb.dut.u_sm1_48

SCORECOND
96.97 90.91
tb.dut.u_sm1_49

SCORECOND
96.97 90.91
tb.dut.u_sm1_50

SCORECOND
96.97 90.91
tb.dut.u_sm1_51

SCORECOND
96.97 90.91
tb.dut.u_sm1_52

SCORECOND
96.97 90.91
tb.dut.u_sm1_53

SCORECOND
96.97 90.91
tb.dut.u_sm1_54

SCORECOND
96.97 90.91
tb.dut.u_sm1_55

SCORECOND
96.97 90.91
tb.dut.u_sm1_56

SCORECOND
96.97 90.91
tb.dut.u_sm1_36

SCORECOND
96.97 90.91
tb.dut.u_sm1_38

SCORECOND
96.97 90.91
tb.dut.u_sm1_40

SCORECOND
96.97 90.91
tb.dut.u_sm1_42

TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Module : tlul_socket_m1
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 2147483647 22295036 0 0
gen_host_fifo[1].idInRange 2147483647 12486912 0 0
gen_host_fifo[2].idInRange 1658572820 3657409 0 0
maxM 21600 21600 0 0
rspIdInRange 2147483647 169895192 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 22295036 0 0
T1 409800 8702 0 0
T2 209112 375 0 0
T3 67896 598 0 0
T4 7421208 300135 0 0
T7 310776 631 0 0
T8 42048 300 0 0
T9 56544 327 0 0
T10 635136 13671 0 0
T11 6864264 592 0 0
T12 1387944 4972 0 0
T13 0 227 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 12486912 0 0
T1 409800 4790 0 0
T2 209112 251 0 0
T3 67896 177 0 0
T4 7421208 123901 0 0
T7 310776 391 0 0
T8 42048 122 0 0
T9 56544 167 0 0
T10 635136 7918 0 0
T11 6864264 319 0 0
T12 1387944 2263 0 0
T13 0 4706 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 1658572820 3657409 0 0
T1 68300 278 0 0
T2 34852 92 0 0
T3 11316 23 0 0
T4 1236868 51227 0 0
T7 51796 92 0 0
T8 7008 14 0 0
T9 9424 39 0 0
T10 105856 596 0 0
T11 1144044 53 0 0
T12 231324 651 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 21600 21600 0 0
T1 24 24 0 0
T2 24 24 0 0
T3 24 24 0 0
T4 24 24 0 0
T7 24 24 0 0
T8 24 24 0 0
T9 24 24 0 0
T10 24 24 0 0
T11 24 24 0 0
T12 24 24 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 169895192 0 0
T1 409800 9903 0 0
T2 209112 1334 0 0
T3 67896 675 0 0
T4 7421208 942158 0 0
T7 310776 1977 0 0
T8 42048 390 0 0
T9 56544 464 0 0
T10 635136 16697 0 0
T11 6864264 45121 0 0
T12 1387944 13625 0 0

Line Coverage for Instance : tb.dut.u_sm1_28
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Cond Coverage for Instance : tb.dut.u_sm1_28
TotalCoveredPercent
Conditions332987.88
Logical332987.88
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T4,T12
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_28
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 1627649 0 0
gen_host_fifo[1].idInRange 414643205 429290 0 0
gen_host_fifo[2].idInRange 414643205 547606 0 0
maxM 900 900 0 0
rspIdInRange 414643205 20767400 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 1627649 0 0
T1 17075 951 0 0
T2 8713 66 0 0
T3 2829 44 0 0
T4 309217 22293 0 0
T7 12949 94 0 0
T8 1752 47 0 0
T9 2356 38 0 0
T10 26464 1602 0 0
T11 286011 90 0 0
T12 57831 443 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 429290 0 0
T1 17075 86 0 0
T2 8713 5 0 0
T3 2829 1 0 0
T4 309217 3444 0 0
T7 12949 13 0 0
T8 1752 6 0 0
T9 2356 7 0 0
T10 26464 151 0 0
T11 286011 5 0 0
T12 57831 88 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 547606 0 0
T1 17075 69 0 0
T2 8713 2 0 0
T3 2829 2 0 0
T4 309217 4936 0 0
T7 12949 11 0 0
T8 1752 3 0 0
T9 2356 12 0 0
T10 26464 141 0 0
T11 286011 7 0 0
T12 57831 71 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 20767400 0 0
T1 17075 1101 0 0
T2 8713 136 0 0
T3 2829 88 0 0
T4 309217 201994 0 0
T7 12949 451 0 0
T8 1752 56 0 0
T9 2356 57 0 0
T10 26464 1864 0 0
T11 286011 10482 0 0
T12 57831 1186 0 0

Line Coverage for Instance : tb.dut.u_sm1_29
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Cond Coverage for Instance : tb.dut.u_sm1_29
TotalCoveredPercent
Conditions332987.88
Logical332987.88
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT4,T22,T17
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_29
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 1805131 0 0
gen_host_fifo[1].idInRange 414643205 515810 0 0
gen_host_fifo[2].idInRange 414643205 662563 0 0
maxM 900 900 0 0
rspIdInRange 414643205 21297671 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 1805131 0 0
T1 17075 1157 0 0
T2 8713 43 0 0
T3 2829 57 0 0
T4 309217 21465 0 0
T7 12949 47 0 0
T8 1752 63 0 0
T9 2356 34 0 0
T10 26464 2018 0 0
T11 286011 60 0 0
T12 57831 462 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 515810 0 0
T1 17075 122 0 0
T2 8713 4 0 0
T3 2829 4 0 0
T4 309217 2474 0 0
T7 12949 28 0 0
T8 1752 5 0 0
T9 2356 14 0 0
T10 26464 212 0 0
T11 286011 4 0 0
T12 57831 81 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 662563 0 0
T1 17075 67 0 0
T2 8713 8 0 0
T3 2829 2 0 0
T4 309217 8612 0 0
T7 12949 8 0 0
T8 1752 6 0 0
T9 2356 5 0 0
T10 26464 168 0 0
T11 286011 4 0 0
T12 57831 39 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 21297671 0 0
T1 17075 1088 0 0
T2 8713 95 0 0
T3 2829 80 0 0
T4 309217 198096 0 0
T7 12949 346 0 0
T8 1752 56 0 0
T9 2356 44 0 0
T10 26464 1908 0 0
T11 286011 7658 0 0
T12 57831 1093 0 0

Line Coverage for Instance : tb.dut.u_sm1_31
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Cond Coverage for Instance : tb.dut.u_sm1_31
TotalCoveredPercent
Conditions332987.88
Logical332987.88
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T8

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T7,T4
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T8

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT4,T13,T17
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_31
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 1680398 0 0
gen_host_fifo[1].idInRange 414643205 422746 0 0
gen_host_fifo[2].idInRange 414643205 530242 0 0
maxM 900 900 0 0
rspIdInRange 414643205 21371060 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 1680398 0 0
T1 17075 1148 0 0
T2 8713 36 0 0
T3 2829 33 0 0
T4 309217 20716 0 0
T7 12949 62 0 0
T8 1752 43 0 0
T9 2356 35 0 0
T10 26464 2067 0 0
T11 286011 65 0 0
T12 57831 441 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 422746 0 0
T1 17075 99 0 0
T2 8713 5 0 0
T3 2829 0 0 0
T4 309217 3845 0 0
T7 12949 17 0 0
T8 1752 2 0 0
T9 2356 5 0 0
T10 26464 154 0 0
T11 286011 7 0 0
T12 57831 74 0 0
T13 0 654 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 530242 0 0
T1 17075 78 0 0
T2 8713 10 0 0
T3 2829 2 0 0
T4 309217 3850 0 0
T7 12949 5 0 0
T8 1752 3 0 0
T9 2356 12 0 0
T10 26464 145 0 0
T11 286011 6 0 0
T12 57831 95 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 21371060 0 0
T1 17075 1093 0 0
T2 8713 138 0 0
T3 2829 77 0 0
T4 309217 189954 0 0
T7 12949 238 0 0
T8 1752 39 0 0
T9 2356 42 0 0
T10 26464 1881 0 0
T11 286011 13621 0 0
T12 57831 1307 0 0

Line Coverage for Instance : tb.dut.u_sm1_33
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_33
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T7,T4
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_33
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 298850 0 0
gen_host_fifo[1].idInRange 414643205 402977 0 0
maxM 900 900 0 0
rspIdInRange 414643205 3053702 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 298850 0 0
T1 17075 110 0 0
T2 8713 4 0 0
T3 2829 3 0 0
T4 309217 363 0 0
T7 12949 3 0 0
T8 1752 6 0 0
T9 2356 7 0 0
T10 26464 547 0 0
T11 286011 18 0 0
T12 57831 61 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 402977 0 0
T1 17075 82 0 0
T2 8713 26 0 0
T3 2829 4 0 0
T4 309217 3523 0 0
T7 12949 10 0 0
T8 1752 5 0 0
T9 2356 3 0 0
T10 26464 614 0 0
T11 286011 7 0 0
T12 57831 78 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 3053702 0 0
T1 17075 188 0 0
T2 8713 37 0 0
T3 2829 32 0 0
T4 309217 10398 0 0
T7 12949 18 0 0
T8 1752 10 0 0
T9 2356 10 0 0
T10 26464 803 0 0
T11 286011 17 0 0
T12 57831 495 0 0

Line Coverage for Instance : tb.dut.u_sm1_34
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_34
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T8
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T8

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T7,T4
101CoveredT1,T2,T8
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T4,T12
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T8

Assert Coverage for Instance : tb.dut.u_sm1_34
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 305984 0 0
gen_host_fifo[1].idInRange 414643205 400446 0 0
maxM 900 900 0 0
rspIdInRange 414643205 4734320 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 305984 0 0
T1 17075 68 0 0
T2 8713 5 0 0
T3 2829 1 0 0
T4 309217 1462 0 0
T7 12949 4 0 0
T8 1752 7 0 0
T9 2356 9 0 0
T10 26464 146 0 0
T11 286011 7 0 0
T12 57831 81 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 400446 0 0
T1 17075 77 0 0
T2 8713 18 0 0
T3 2829 0 0 0
T4 309217 2197 0 0
T7 12949 17 0 0
T8 1752 2 0 0
T9 2356 7 0 0
T10 26464 138 0 0
T11 286011 17 0 0
T12 57831 70 0 0
T13 0 5 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 4734320 0 0
T1 17075 142 0 0
T2 8713 31 0 0
T3 2829 1 0 0
T4 309217 14456 0 0
T7 12949 19 0 0
T8 1752 9 0 0
T9 2356 15 0 0
T10 26464 279 0 0
T11 286011 16 0 0
T12 57831 578 0 0

Line Coverage for Instance : tb.dut.u_sm1_36
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_36
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T7,T4
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT3,T4,T13
101CoveredT1,T2,T8
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_36
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 778250 0 0
gen_host_fifo[1].idInRange 414643205 946304 0 0
maxM 900 900 0 0
rspIdInRange 414643205 4781988 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 778250 0 0
T1 17075 108 0 0
T2 8713 4 0 0
T3 2829 2 0 0
T4 309217 2641 0 0
T7 12949 10 0 0
T8 1752 6 0 0
T9 2356 14 0 0
T10 26464 178 0 0
T11 286011 4 0 0
T12 57831 54 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 946304 0 0
T1 17075 60 0 0
T2 8713 30 0 0
T3 2829 9 0 0
T4 309217 5838 0 0
T7 12949 6 0 0
T8 1752 5 0 0
T9 2356 19 0 0
T10 26464 185 0 0
T11 286011 4 0 0
T12 57831 95 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 4781988 0 0
T1 17075 133 0 0
T2 8713 30 0 0
T3 2829 12 0 0
T4 309217 8799 0 0
T7 12949 58 0 0
T8 1752 11 0 0
T9 2356 16 0 0
T10 26464 296 0 0
T11 286011 8 0 0
T12 57831 350 0 0

Line Coverage for Instance : tb.dut.u_sm1_38
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_38
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T7,T4
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T4,T13
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_38
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 585087 0 0
gen_host_fifo[1].idInRange 414643205 666431 0 0
maxM 900 900 0 0
rspIdInRange 414643205 5134602 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 585087 0 0
T1 17075 506 0 0
T2 8713 6 0 0
T3 2829 1 0 0
T4 309217 7975 0 0
T7 12949 4 0 0
T8 1752 2 0 0
T9 2356 13 0 0
T10 26464 538 0 0
T11 286011 4 0 0
T12 57831 50 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 666431 0 0
T1 17075 964 0 0
T2 8713 4 0 0
T3 2829 3 0 0
T4 309217 9671 0 0
T7 12949 9 0 0
T8 1752 3 0 0
T9 2356 2 0 0
T10 26464 939 0 0
T11 286011 21 0 0
T12 57831 56 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 5134602 0 0
T1 17075 357 0 0
T2 8713 32 0 0
T3 2829 4 0 0
T4 309217 1727 0 0
T7 12949 15 0 0
T8 1752 5 0 0
T9 2356 10 0 0
T10 26464 521 0 0
T11 286011 13 0 0
T12 57831 324 0 0

Line Coverage for Instance : tb.dut.u_sm1_40
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_40
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT4,T13,T22
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_40
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 540925 0 0
gen_host_fifo[1].idInRange 414643205 591453 0 0
maxM 900 900 0 0
rspIdInRange 414643205 4740183 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 540925 0 0
T1 17075 82 0 0
T2 8713 12 0 0
T3 2829 2 0 0
T4 309217 712 0 0
T7 12949 7 0 0
T8 1752 1 0 0
T9 2356 18 0 0
T10 26464 140 0 0
T11 286011 13 0 0
T12 57831 59 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 591453 0 0
T1 17075 115 0 0
T2 8713 4 0 0
T3 2829 3 0 0
T4 309217 6079 0 0
T7 12949 4 0 0
T8 1752 9 0 0
T9 2356 7 0 0
T10 26464 162 0 0
T11 286011 18 0 0
T12 57831 127 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 4740183 0 0
T1 17075 162 0 0
T2 8713 67 0 0
T3 2829 11 0 0
T4 309217 7344 0 0
T7 12949 11 0 0
T8 1752 7 0 0
T9 2356 15 0 0
T10 26464 255 0 0
T11 286011 19 0 0
T12 57831 375 0 0

Line Coverage for Instance : tb.dut.u_sm1_42
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_42
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T4,T12
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_42
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 693148 0 0
gen_host_fifo[1].idInRange 414643205 827413 0 0
maxM 900 900 0 0
rspIdInRange 414643205 4696767 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 693148 0 0
T1 17075 81 0 0
T2 8713 2 0 0
T3 2829 5 0 0
T4 309217 4437 0 0
T7 12949 7 0 0
T8 1752 13 0 0
T9 2356 5 0 0
T10 26464 1401 0 0
T11 286011 3 0 0
T12 57831 94 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 827413 0 0
T1 17075 76 0 0
T2 8713 23 0 0
T3 2829 3 0 0
T4 309217 2628 0 0
T7 12949 11 0 0
T8 1752 6 0 0
T9 2356 13 0 0
T10 26464 1716 0 0
T11 286011 5 0 0
T12 57831 77 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 4696767 0 0
T1 17075 129 0 0
T2 8713 19 0 0
T3 2829 19 0 0
T4 309217 6983 0 0
T7 12949 29 0 0
T8 1752 8 0 0
T9 2356 13 0 0
T10 26464 950 0 0
T11 286011 8 0 0
T12 57831 482 0 0

Line Coverage for Instance : tb.dut.u_sm1_43
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_43
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T3,T8
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T4,T12
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_43
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 340321 0 0
gen_host_fifo[1].idInRange 414643205 457244 0 0
maxM 900 900 0 0
rspIdInRange 414643205 4260212 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 340321 0 0
T1 17075 81 0 0
T2 8713 4 0 0
T3 2829 2 0 0
T4 309217 393 0 0
T7 12949 8 0 0
T8 1752 5 0 0
T9 2356 5 0 0
T10 26464 121 0 0
T11 286011 5 0 0
T12 57831 57 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 457244 0 0
T1 17075 67 0 0
T2 8713 5 0 0
T3 2829 4 0 0
T4 309217 3076 0 0
T7 12949 19 0 0
T8 1752 6 0 0
T9 2356 6 0 0
T10 26464 140 0 0
T11 286011 12 0 0
T12 57831 74 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 4260212 0 0
T1 17075 143 0 0
T2 8713 18 0 0
T3 2829 10 0 0
T4 309217 11309 0 0
T7 12949 38 0 0
T8 1752 11 0 0
T9 2356 11 0 0
T10 26464 257 0 0
T11 286011 14 0 0
T12 57831 338 0 0

Line Coverage for Instance : tb.dut.u_sm1_44
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_44
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT4,T12,T22
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_44
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 238603 0 0
gen_host_fifo[1].idInRange 414643205 317663 0 0
maxM 900 900 0 0
rspIdInRange 414643205 4065666 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 238603 0 0
T1 17075 98 0 0
T2 8713 4 0 0
T3 2829 5 0 0
T4 309217 280 0 0
T7 12949 18 0 0
T8 1752 5 0 0
T9 2356 8 0 0
T10 26464 186 0 0
T11 286011 20 0 0
T12 57831 85 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 317663 0 0
T1 17075 63 0 0
T2 8713 4 0 0
T3 2829 3 0 0
T4 309217 3472 0 0
T7 12949 6 0 0
T8 1752 5 0 0
T9 2356 10 0 0
T10 26464 124 0 0
T11 286011 12 0 0
T12 57831 54 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 4065666 0 0
T1 17075 158 0 0
T2 8713 39 0 0
T3 2829 14 0 0
T4 309217 7224 0 0
T7 12949 22 0 0
T8 1752 10 0 0
T9 2356 17 0 0
T10 26464 297 0 0
T11 286011 118 0 0
T12 57831 404 0 0

Line Coverage for Instance : tb.dut.u_sm1_45
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_45
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T8
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T8

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T8
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT4,T22,T17
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T8

Assert Coverage for Instance : tb.dut.u_sm1_45
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 278935 0 0
gen_host_fifo[1].idInRange 414643205 376708 0 0
maxM 900 900 0 0
rspIdInRange 414643205 4359410 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 278935 0 0
T1 17075 121 0 0
T2 8713 16 0 0
T3 2829 1 0 0
T4 309217 131 0 0
T7 12949 3 0 0
T8 1752 1 0 0
T9 2356 17 0 0
T10 26464 158 0 0
T11 286011 3 0 0
T12 57831 80 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 376708 0 0
T1 17075 77 0 0
T2 8713 3 0 0
T3 2829 0 0 0
T4 309217 2164 0 0
T7 12949 6 0 0
T8 1752 9 0 0
T9 2356 8 0 0
T10 26464 136 0 0
T11 286011 17 0 0
T12 57831 54 0 0
T13 0 3 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 4359410 0 0
T1 17075 184 0 0
T2 8713 79 0 0
T3 2829 1 0 0
T4 309217 8000 0 0
T7 12949 27 0 0
T8 1752 10 0 0
T9 2356 20 0 0
T10 26464 286 0 0
T11 286011 12 0 0
T12 57831 491 0 0

Line Coverage for Instance : tb.dut.u_sm1_46
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_46
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T8
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T7,T4
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T4,T12
101CoveredT1,T2,T8
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_46
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 299206 0 0
gen_host_fifo[1].idInRange 414643205 417384 0 0
maxM 900 900 0 0
rspIdInRange 414643205 4453539 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 299206 0 0
T1 17075 83 0 0
T2 8713 7 0 0
T3 2829 0 0 0
T4 309217 102 0 0
T7 12949 5 0 0
T8 1752 4 0 0
T9 2356 6 0 0
T10 26464 146 0 0
T11 286011 2 0 0
T12 57831 89 0 0
T13 0 216 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 417384 0 0
T1 17075 77 0 0
T2 8713 4 0 0
T3 2829 3 0 0
T4 309217 3903 0 0
T7 12949 21 0 0
T8 1752 4 0 0
T9 2356 2 0 0
T10 26464 148 0 0
T11 286011 7 0 0
T12 57831 85 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 4453539 0 0
T1 17075 147 0 0
T2 8713 50 0 0
T3 2829 3 0 0
T4 309217 8232 0 0
T7 12949 30 0 0
T8 1752 8 0 0
T9 2356 8 0 0
T10 26464 289 0 0
T11 286011 9 0 0
T12 57831 488 0 0

Line Coverage for Instance : tb.dut.u_sm1_47
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_47
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T8
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T4,T12
101CoveredT1,T2,T8
110CoveredT1,T2,T3
111CoveredT1,T2,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T4,T12
101CoveredT1,T2,T8
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_47
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 280549 0 0
gen_host_fifo[1].idInRange 414643205 391115 0 0
maxM 900 900 0 0
rspIdInRange 414643205 4688688 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 280549 0 0
T1 17075 79 0 0
T2 8713 5 0 0
T3 2829 0 0 0
T4 309217 2000 0 0
T7 12949 8 0 0
T8 1752 3 0 0
T9 2356 9 0 0
T10 26464 449 0 0
T11 286011 4 0 0
T12 57831 41 0 0
T13 0 11 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 391115 0 0
T1 17075 59 0 0
T2 8713 9 0 0
T3 2829 1 0 0
T4 309217 3125 0 0
T7 12949 7 0 0
T8 1752 6 0 0
T9 2356 5 0 0
T10 26464 392 0 0
T11 286011 5 0 0
T12 57831 92 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 4688688 0 0
T1 17075 137 0 0
T2 8713 55 0 0
T3 2829 1 0 0
T4 309217 11406 0 0
T7 12949 17 0 0
T8 1752 9 0 0
T9 2356 13 0 0
T10 26464 720 0 0
T11 286011 9 0 0
T12 57831 386 0 0

Line Coverage for Instance : tb.dut.u_sm1_48
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_48
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T7,T4
101CoveredT1,T2,T8
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T4,T13
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_48
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 315821 0 0
gen_host_fifo[1].idInRange 414643205 434471 0 0
maxM 900 900 0 0
rspIdInRange 414643205 4092789 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 315821 0 0
T1 17075 71 0 0
T2 8713 3 0 0
T3 2829 1 0 0
T4 309217 1999 0 0
T7 12949 9 0 0
T8 1752 12 0 0
T9 2356 9 0 0
T10 26464 216 0 0
T11 286011 6 0 0
T12 57831 42 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 434471 0 0
T1 17075 82 0 0
T2 8713 6 0 0
T3 2829 2 0 0
T4 309217 1047 0 0
T7 12949 7 0 0
T8 1752 2 0 0
T9 2356 4 0 0
T10 26464 439 0 0
T11 286011 17 0 0
T12 57831 80 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 4092789 0 0
T1 17075 152 0 0
T2 8713 33 0 0
T3 2829 3 0 0
T4 309217 8460 0 0
T7 12949 27 0 0
T8 1752 12 0 0
T9 2356 12 0 0
T10 26464 521 0 0
T11 286011 14 0 0
T12 57831 374 0 0

Line Coverage for Instance : tb.dut.u_sm1_49
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_49
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT4,T12,T13
101CoveredT1,T2,T8
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_49
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 290647 0 0
gen_host_fifo[1].idInRange 414643205 379900 0 0
maxM 900 900 0 0
rspIdInRange 414643205 4084430 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 290647 0 0
T1 17075 1016 0 0
T2 8713 8 0 0
T3 2829 1 0 0
T4 309217 1428 0 0
T7 12949 8 0 0
T8 1752 2 0 0
T9 2356 6 0 0
T10 26464 167 0 0
T11 286011 2 0 0
T12 57831 55 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 379900 0 0
T1 17075 827 0 0
T2 8713 6 0 0
T3 2829 2 0 0
T4 309217 2608 0 0
T7 12949 12 0 0
T8 1752 3 0 0
T9 2356 5 0 0
T10 26464 146 0 0
T11 286011 10 0 0
T12 57831 48 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 4084430 0 0
T1 17075 649 0 0
T2 8713 39 0 0
T3 2829 4 0 0
T4 309217 11357 0 0
T7 12949 35 0 0
T8 1752 5 0 0
T9 2356 11 0 0
T10 26464 304 0 0
T11 286011 10 0 0
T12 57831 420 0 0

Line Coverage for Instance : tb.dut.u_sm1_50
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_50
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T3,T8
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_50
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 279215 0 0
gen_host_fifo[1].idInRange 414643205 365600 0 0
maxM 900 900 0 0
rspIdInRange 414643205 3877068 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 279215 0 0
T1 17075 200 0 0
T2 8713 5 0 0
T3 2829 105 0 0
T4 309217 724 0 0
T7 12949 7 0 0
T8 1752 7 0 0
T9 2356 3 0 0
T10 26464 476 0 0
T11 286011 6 0 0
T12 57831 52 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 365600 0 0
T1 17075 154 0 0
T2 8713 6 0 0
T3 2829 115 0 0
T4 309217 2436 0 0
T7 12949 12 0 0
T8 1752 8 0 0
T9 2356 8 0 0
T10 26464 482 0 0
T11 286011 22 0 0
T12 57831 44 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 3877068 0 0
T1 17075 305 0 0
T2 8713 27 0 0
T3 2829 107 0 0
T4 309217 9729 0 0
T7 12949 27 0 0
T8 1752 14 0 0
T9 2356 11 0 0
T10 26464 756 0 0
T11 286011 17 0 0
T12 57831 398 0 0

Line Coverage for Instance : tb.dut.u_sm1_51
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_51
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT7,T4,T12
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_51
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 297170 0 0
gen_host_fifo[1].idInRange 414643205 396957 0 0
maxM 900 900 0 0
rspIdInRange 414643205 4621607 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 297170 0 0
T1 17075 96 0 0
T2 8713 7 0 0
T3 2829 2 0 0
T4 309217 1844 0 0
T7 12949 12 0 0
T8 1752 5 0 0
T9 2356 11 0 0
T10 26464 169 0 0
T11 286011 2 0 0
T12 57831 126 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 396957 0 0
T1 17075 91 0 0
T2 8713 6 0 0
T3 2829 5 0 0
T4 309217 1198 0 0
T7 12949 5 0 0
T8 1752 2 0 0
T9 2356 8 0 0
T10 26464 120 0 0
T11 286011 7 0 0
T12 57831 126 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 4621607 0 0
T1 17075 179 0 0
T2 8713 48 0 0
T3 2829 15 0 0
T4 309217 12003 0 0
T7 12949 24 0 0
T8 1752 7 0 0
T9 2356 18 0 0
T10 26464 284 0 0
T11 286011 9 0 0
T12 57831 744 0 0

Line Coverage for Instance : tb.dut.u_sm1_52
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_52
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT4,T22,T17
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_52
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 274081 0 0
gen_host_fifo[1].idInRange 414643205 369102 0 0
maxM 900 900 0 0
rspIdInRange 414643205 4475136 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 274081 0 0
T1 17075 87 0 0
T2 8713 4 0 0
T3 2829 2 0 0
T4 309217 878 0 0
T7 12949 8 0 0
T8 1752 6 0 0
T9 2356 11 0 0
T10 26464 131 0 0
T11 286011 3 0 0
T12 57831 88 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 369102 0 0
T1 17075 82 0 0
T2 8713 27 0 0
T3 2829 1 0 0
T4 309217 4297 0 0
T7 12949 36 0 0
T8 1752 3 0 0
T9 2356 6 0 0
T10 26464 148 0 0
T11 286011 10 0 0
T12 57831 57 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 4475136 0 0
T1 17075 162 0 0
T2 8713 58 0 0
T3 2829 3 0 0
T4 309217 12986 0 0
T7 12949 44 0 0
T8 1752 9 0 0
T9 2356 16 0 0
T10 26464 274 0 0
T11 286011 13 0 0
T12 57831 515 0 0

Line Coverage for Instance : tb.dut.u_sm1_53
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_53
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T8
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT4,T12,T22
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_53
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 310465 0 0
gen_host_fifo[1].idInRange 414643205 412960 0 0
maxM 900 900 0 0
rspIdInRange 414643205 3743634 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 310465 0 0
T1 17075 1061 0 0
T2 8713 13 0 0
T3 2829 4 0 0
T4 309217 1619 0 0
T7 12949 8 0 0
T8 1752 4 0 0
T9 2356 4 0 0
T10 26464 160 0 0
T11 286011 5 0 0
T12 57831 48 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 412960 0 0
T1 17075 913 0 0
T2 8713 6 0 0
T3 2829 2 0 0
T4 309217 3709 0 0
T7 12949 44 0 0
T8 1752 8 0 0
T9 2356 3 0 0
T10 26464 136 0 0
T11 286011 15 0 0
T12 57831 75 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 3743634 0 0
T1 17075 1248 0 0
T2 8713 84 0 0
T3 2829 18 0 0
T4 309217 7035 0 0
T7 12949 49 0 0
T8 1752 12 0 0
T9 2356 7 0 0
T10 26464 290 0 0
T11 286011 13 0 0
T12 57831 358 0 0

Line Coverage for Instance : tb.dut.u_sm1_54
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_54
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T7,T4
101CoveredT1,T8,T9
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT4,T22,T17
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_54
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 281080 0 0
gen_host_fifo[1].idInRange 414643205 383439 0 0
maxM 900 900 0 0
rspIdInRange 414643205 4554229 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 281080 0 0
T1 17075 89 0 0
T2 8713 2 0 0
T3 2829 2 0 0
T4 309217 1578 0 0
T7 12949 14 0 0
T8 1752 2 0 0
T9 2356 8 0 0
T10 26464 449 0 0
T11 286011 6 0 0
T12 57831 83 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 383439 0 0
T1 17075 75 0 0
T2 8713 3 0 0
T3 2829 1 0 0
T4 309217 3215 0 0
T7 12949 6 0 0
T8 1752 4 0 0
T9 2356 4 0 0
T10 26464 487 0 0
T11 286011 7 0 0
T12 57831 77 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 4554229 0 0
T1 17075 158 0 0
T2 8713 10 0 0
T3 2829 3 0 0
T4 309217 8114 0 0
T7 12949 35 0 0
T8 1752 6 0 0
T9 2356 11 0 0
T10 26464 749 0 0
T11 286011 13 0 0
T12 57831 389 0 0

Line Coverage for Instance : tb.dut.u_sm1_55
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_55
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T8
101CoveredT1,T3,T8
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT4,T12,T13
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_55
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 266689 0 0
gen_host_fifo[1].idInRange 414643205 347975 0 0
maxM 900 900 0 0
rspIdInRange 414643205 3922908 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 266689 0 0
T1 17075 409 0 0
T2 8713 5 0 0
T3 2829 3 0 0
T4 309217 2590 0 0
T7 12949 7 0 0
T8 1752 6 0 0
T9 2356 9 0 0
T10 26464 186 0 0
T11 286011 11 0 0
T12 57831 65 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 347975 0 0
T1 17075 411 0 0
T2 8713 6 0 0
T3 2829 6 0 0
T4 309217 4054 0 0
T7 12949 12 0 0
T8 1752 10 0 0
T9 2356 7 0 0
T10 26464 146 0 0
T11 286011 22 0 0
T12 57831 70 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 3922908 0 0
T1 17075 698 0 0
T2 8713 33 0 0
T3 2829 17 0 0
T4 309217 10265 0 0
T7 12949 31 0 0
T8 1752 15 0 0
T9 2356 15 0 0
T10 26464 323 0 0
T11 286011 20 0 0
T12 57831 403 0 0

Line Coverage for Instance : tb.dut.u_sm1_56
Line No.TotalCoveredPercent
TOTAL1818100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 2 2
105 2 2
108 2 2
163 2 2
166 1 1
212 1 1
213 1 1
231 1 1
236 2 2
238 2 2
242 2 2


Cond Coverage for Instance : tb.dut.u_sm1_56
TotalCoveredPercent
Conditions222090.91
Logical222090.91
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT4,T12,T22
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_56
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 299988 0 0
gen_host_fifo[1].idInRange 414643205 382469 0 0
maxM 900 900 0 0
rspIdInRange 414643205 3452842 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 299988 0 0
T1 17075 63 0 0
T2 8713 7 0 0
T3 2829 11 0 0
T4 309217 444 0 0
T7 12949 15 0 0
T8 1752 6 0 0
T9 2356 8 0 0
T10 26464 447 0 0
T11 286011 16 0 0
T12 57831 49 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 382469 0 0
T1 17075 59 0 0
T2 8713 5 0 0
T3 2829 5 0 0
T4 309217 2224 0 0
T7 12949 19 0 0
T8 1752 5 0 0
T9 2356 8 0 0
T10 26464 439 0 0
T11 286011 6 0 0
T12 57831 62 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 3452842 0 0
T1 17075 120 0 0
T2 8713 57 0 0
T3 2829 46 0 0
T4 309217 10169 0 0
T7 12949 78 0 0
T8 1752 11 0 0
T9 2356 16 0 0
T10 26464 732 0 0
T11 286011 14 0 0
T12 57831 373 0 0

Line Coverage for Instance : tb.dut.u_sm1_30
Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21311100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
CONT_ASSIGN24211100.00
WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' or '../src/lowrisc_tlul_socket_m1_0.1/rtl/tlul_socket_m1.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
96 3 3
105 3 3
108 3 3
163 3 3
166 1 1
212 1 1
213 1 1
231 1 1
236 3 3
238 3 3
242 3 3


Cond Coverage for Instance : tb.dut.u_sm1_30
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 0))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 1))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T8

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       236
 EXPRESSION (drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == 2))
             ---------1---------   ------------------2------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       236
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[0].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 0) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 0)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[1].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 1) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT2,T8,T7
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T8

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 1)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       238
 EXPRESSION (hreq_fifo_o[2].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == 2) & drsp_fifo_o.d_valid)
             -----------1----------   ------------------2------------------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       238
 SUB-EXPRESSION (drsp_fifo_o.d_source[0+:STIDW] == 2)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_sm1_30
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_host_fifo[0].idInRange 414643205 9926844 0 0
gen_host_fifo[1].idInRange 414643205 1851055 0 0
gen_host_fifo[2].idInRange 414643205 1916998 0 0
maxM 900 900 0 0
rspIdInRange 414643205 20665341 0 0


gen_host_fifo[0].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 9926844 0 0
T1 17075 937 0 0
T2 8713 107 0 0
T3 2829 311 0 0
T4 309217 202061 0 0
T7 12949 263 0 0
T8 1752 44 0 0
T9 2356 40 0 0
T10 26464 1573 0 0
T11 286011 237 0 0
T12 57831 2267 0 0

gen_host_fifo[1].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 1851055 0 0
T1 17075 72 0 0
T2 8713 36 0 0
T3 2829 0 0 0
T4 309217 43674 0 0
T7 12949 64 0 0
T8 1752 4 0 0
T9 2356 6 0 0
T10 26464 164 0 0
T11 286011 62 0 0
T12 57831 519 0 0
T13 0 4044 0 0

gen_host_fifo[2].idInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 1916998 0 0
T1 17075 64 0 0
T2 8713 72 0 0
T3 2829 17 0 0
T4 309217 33829 0 0
T7 12949 68 0 0
T8 1752 2 0 0
T9 2356 10 0 0
T10 26464 142 0 0
T11 286011 36 0 0
T12 57831 446 0 0

maxM
NameAttemptsReal SuccessesFailuresIncomplete
Total 900 900 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0

rspIdInRange
NameAttemptsReal SuccessesFailuresIncomplete
Total 414643205 20665341 0 0
T1 17075 1070 0 0
T2 8713 119 0 0
T3 2829 106 0 0
T4 309217 166118 0 0
T7 12949 308 0 0
T8 1752 50 0 0
T9 2356 56 0 0
T10 26464 1858 0 0
T11 286011 12994 0 0
T12 57831 1354 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%