Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Source File(s) :
/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb	93.39	100.00	92.31			100.00	81.25
tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50
tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb	94.95	100.00	92.31			100.00	87.50

---

Module Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_29

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_31

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_33

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_34

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_36

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_38

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_40

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_42

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_43

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_44

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_45

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_46

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_47

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_48

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_49

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_50

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_51

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_52

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_53

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_54

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_55

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.39	100.00	92.31			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.97	100.00	90.91				100.00	u_sm1_56

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.96	100.00	87.88				100.00	u_sm1_28

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.95	100.00	92.31			100.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_sm1_30

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Line Coverage for Module self-instances :

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	LINE
94.95	100.00

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	LINE
93.39	100.00

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=109,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
94.95	92.31

tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

SCORE	COND
94.95	92.31

tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=109,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.39	92.31

tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

SCORE	COND
93.39	92.31

tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	2147483647	2147483647	0	0
CheckNGreaterZero_A	21600	21600	0	0
GntImpliesReady_A	2147483647	7210772	0	0
GntImpliesValid_A	2147483647	7210772	0	0
GrantKnown_A	2147483647	2147483647	0	0
IdxKnown_A	2147483647	2147483647	0	0
IndexIsCorrect_A	2147483647	7210772	0	0
LockArbDecision_A	2147483647	0	0	0
NoReadyValidNoGrant_A	2147483647	452492474	0	0
ReadyAndValidImplyGrant_A	2147483647	7210772	0	0
ReqAndReadyImplyGrant_A	2147483647	7210772	0	0
ReqImpliesValid_A	2147483647	33463363	0	0
ReqStaysHighUntilGranted0_M	2147483647	0	0	0
RoundRobin_A	2147483647	34144	0	21600
ValidKnown_A	2147483647	2147483647	0	0
gen_data_port_assertion.DataFlow_A	2147483647	7210772	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	409800	390528	0	0
T2	209112	208728	0	0
T3	67896	64320	0	0
T4	7421208	7421064	0	0
T7	310776	309792	0	0
T8	42048	40992	0	0
T9	56544	54816	0	0
T10	635136	612648	0	0
T11	6864264	6863688	0	0
T12	1387944	1387176	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21600	21600	0	0
T1	24	24	0	0
T2	24	24	0	0
T3	24	24	0	0
T4	24	24	0	0
T7	24	24	0	0
T8	24	24	0	0
T9	24	24	0	0
T10	24	24	0	0
T11	24	24	0	0
T12	24	24	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7210772	0	0
T1	409800	9921	0	0
T2	209112	378	0	0
T3	67896	307	0	0
T4	7421208	7537	0	0
T7	310776	540	0	0
T8	42048	390	0	0
T9	56544	464	0	0
T10	635136	16718	0	0
T11	6864264	517	0	0
T12	1387944	3828	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7210772	0	0
T1	409800	9921	0	0
T2	209112	378	0	0
T3	67896	307	0	0
T4	7421208	7537	0	0
T7	310776	540	0	0
T8	42048	390	0	0
T9	56544	464	0	0
T10	635136	16718	0	0
T11	6864264	517	0	0
T12	1387944	3828	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	409800	390528	0	0
T2	209112	208728	0	0
T3	67896	64320	0	0
T4	7421208	7421064	0	0
T7	310776	309792	0	0
T8	42048	40992	0	0
T9	56544	54816	0	0
T10	635136	612648	0	0
T11	6864264	6863688	0	0
T12	1387944	1387176	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	409800	390528	0	0
T2	209112	208728	0	0
T3	67896	64320	0	0
T4	7421208	7421064	0	0
T7	310776	309792	0	0
T8	42048	40992	0	0
T9	56544	54816	0	0
T10	635136	612648	0	0
T11	6864264	6863688	0	0
T12	1387944	1387176	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7210772	0	0
T1	409800	9921	0	0
T2	209112	378	0	0
T3	67896	307	0	0
T4	7421208	7537	0	0
T7	310776	540	0	0
T8	42048	390	0	0
T9	56544	464	0	0
T10	635136	16718	0	0
T11	6864264	517	0	0
T12	1387944	3828	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	452492474	0	0
T1	392725	8913	0	0
T2	209112	10227	0	0
T3	67896	4134	0	0
T4	7421208	2743054	0	0
T7	310776	14941	0	0
T8	42048	442	0	0
T9	56544	634	0	0
T10	635136	15900	0	0
T11	6864264	239808	0	0
T12	1387944	78080	0	0
T13	461861	441887	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7210772	0	0
T1	409800	9921	0	0
T2	209112	378	0	0
T3	67896	307	0	0
T4	7421208	7537	0	0
T7	310776	540	0	0
T8	42048	390	0	0
T9	56544	464	0	0
T10	635136	16718	0	0
T11	6864264	517	0	0
T12	1387944	3828	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7210772	0	0
T1	409800	9921	0	0
T2	209112	378	0	0
T3	67896	307	0	0
T4	7421208	7537	0	0
T7	310776	540	0	0
T8	42048	390	0	0
T9	56544	464	0	0
T10	635136	16718	0	0
T11	6864264	517	0	0
T12	1387944	3828	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33463363	0	0
T1	409800	12371	0	0
T2	209112	718	0	0
T3	67896	786	0	0
T4	7421208	461529	0	0
T7	310776	1114	0	0
T8	42048	436	0	0
T9	56544	533	0	0
T10	635136	20821	0	0
T11	6864264	964	0	0
T12	1387944	7781	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34144	0	21600
T1	34150	15	0	2
T2	17426	0	0	2
T3	5658	0	0	2
T4	618434	0	0	2
T7	25898	0	0	2
T8	3504	0	0	2
T9	4712	0	0	2
T10	52928	57	0	2
T11	572022	0	0	2
T12	115662	0	0	2
T14	0	4	0	0
T15	0	19	0	0
T16	0	3	0	0
T17	0	5	0	0
T18	0	26	0	0
T19	0	27	0	0
T20	0	11	0	0
T21	0	19	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	409800	390528	0	0
T2	209112	208728	0	0
T3	67896	64320	0	0
T4	7421208	7421064	0	0
T7	310776	309792	0	0
T8	42048	40992	0	0
T9	56544	54816	0	0
T10	635136	612648	0	0
T11	6864264	6863688	0	0
T12	1387944	1387176	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7210772	0	0
T1	409800	9921	0	0
T2	209112	378	0	0
T3	67896	307	0	0
T4	7421208	7537	0	0
T7	310776	540	0	0
T8	42048	390	0	0
T9	56544	464	0	0
T10	635136	16718	0	0
T11	6864264	517	0	0
T12	1387944	3828	0	0

Line Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_29.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	813193	0	0
GntImpliesValid_A	414643205	813193	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	813193	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	11712641	0	0
ReadyAndValidImplyGrant_A	414643205	813193	0	0
ReqAndReadyImplyGrant_A	414643205	813193	0	0
ReqImpliesValid_A	414643205	2443362	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	0	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	813193	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	813193	0	0
T1	17075	1091	0	0
T2	8713	39	0	0
T3	2829	32	0	0
T4	309217	826	0	0
T7	12949	57	0	0
T8	1752	56	0	0
T9	2356	44	0	0
T10	26464	1909	0	0
T11	286011	43	0	0
T12	57831	394	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	813193	0	0
T1	17075	1091	0	0
T2	8713	39	0	0
T3	2829	32	0	0
T4	309217	826	0	0
T7	12949	57	0	0
T8	1752	56	0	0
T9	2356	44	0	0
T10	26464	1909	0	0
T11	286011	43	0	0
T12	57831	394	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	813193	0	0
T1	17075	1091	0	0
T2	8713	39	0	0
T3	2829	32	0	0
T4	309217	826	0	0
T7	12949	57	0	0
T8	1752	56	0	0
T9	2356	44	0	0
T10	26464	1909	0	0
T11	286011	43	0	0
T12	57831	394	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	11712641	0	0
T1	17075	869	0	0
T2	8713	294	0	0
T3	2829	240	0	0
T4	309217	277919	0	0
T7	12949	391	0	0
T8	1752	39	0	0
T9	2356	36	0	0
T10	26464	1489	0	0
T11	286011	206	0	0
T12	57831	2868	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	813193	0	0
T1	17075	1091	0	0
T2	8713	39	0	0
T3	2829	32	0	0
T4	309217	826	0	0
T7	12949	57	0	0
T8	1752	56	0	0
T9	2356	44	0	0
T10	26464	1909	0	0
T11	286011	43	0	0
T12	57831	394	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	813193	0	0
T1	17075	1091	0	0
T2	8713	39	0	0
T3	2829	32	0	0
T4	309217	826	0	0
T7	12949	57	0	0
T8	1752	56	0	0
T9	2356	44	0	0
T10	26464	1909	0	0
T11	286011	43	0	0
T12	57831	394	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	2443362	0	0
T1	17075	1323	0	0
T2	8713	55	0	0
T3	2829	63	0	0
T4	309217	30393	0	0
T7	12949	83	0	0
T8	1752	74	0	0
T9	2356	53	0	0
T10	26464	2345	0	0
T11	286011	68	0	0
T12	57831	582	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	813193	0	0
T1	17075	1091	0	0
T2	8713	39	0	0
T3	2829	32	0	0
T4	309217	826	0	0
T7	12949	57	0	0
T8	1752	56	0	0
T9	2356	44	0	0
T10	26464	1909	0	0
T11	286011	43	0	0
T12	57831	394	0	0

Line Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_31.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	793461	0	0
GntImpliesValid_A	414643205	793461	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	793461	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	11580241	0	0
ReadyAndValidImplyGrant_A	414643205	793461	0	0
ReqAndReadyImplyGrant_A	414643205	793461	0	0
ReqImpliesValid_A	414643205	2252575	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	0	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	793461	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	793461	0	0
T1	17075	1095	0	0
T2	8713	42	0	0
T3	2829	30	0	0
T4	309217	794	0	0
T7	12949	45	0	0
T8	1752	39	0	0
T9	2356	42	0	0
T10	26464	1884	0	0
T11	286011	60	0	0
T12	57831	415	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	793461	0	0
T1	17075	1095	0	0
T2	8713	42	0	0
T3	2829	30	0	0
T4	309217	794	0	0
T7	12949	45	0	0
T8	1752	39	0	0
T9	2356	42	0	0
T10	26464	1884	0	0
T11	286011	60	0	0
T12	57831	415	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	793461	0	0
T1	17075	1095	0	0
T2	8713	42	0	0
T3	2829	30	0	0
T4	309217	794	0	0
T7	12949	45	0	0
T8	1752	39	0	0
T9	2356	42	0	0
T10	26464	1884	0	0
T11	286011	60	0	0
T12	57831	415	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	11580241	0	0
T1	17075	887	0	0
T2	8713	247	0	0
T3	2829	235	0	0
T4	309217	253307	0	0
T7	12949	375	0	0
T8	1752	31	0	0
T9	2356	33	0	0
T10	26464	1451	0	0
T11	286011	247	0	0
T12	57831	3018	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	793461	0	0
T1	17075	1095	0	0
T2	8713	42	0	0
T3	2829	30	0	0
T4	309217	794	0	0
T7	12949	45	0	0
T8	1752	39	0	0
T9	2356	42	0	0
T10	26464	1884	0	0
T11	286011	60	0	0
T12	57831	415	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	793461	0	0
T1	17075	1095	0	0
T2	8713	42	0	0
T3	2829	30	0	0
T4	309217	794	0	0
T7	12949	45	0	0
T8	1752	39	0	0
T9	2356	42	0	0
T10	26464	1884	0	0
T11	286011	60	0	0
T12	57831	415	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	2252575	0	0
T1	17075	1314	0	0
T2	8713	51	0	0
T3	2829	35	0	0
T4	309217	27277	0	0
T7	12949	84	0	0
T8	1752	48	0	0
T9	2356	52	0	0
T10	26464	2332	0	0
T11	286011	78	0	0
T12	57831	610	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	793461	0	0
T1	17075	1095	0	0
T2	8713	42	0	0
T3	2829	30	0	0
T4	309217	794	0	0
T7	12949	45	0	0
T8	1752	39	0	0
T9	2356	42	0	0
T10	26464	1884	0	0
T11	286011	60	0	0
T12	57831	415	0	0

Line Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_33.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	198361	0	0
GntImpliesValid_A	414643205	198361	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	198361	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	2899074	0	0
ReadyAndValidImplyGrant_A	414643205	198361	0	0
ReqAndReadyImplyGrant_A	414643205	198361	0	0
ReqImpliesValid_A	414643205	579683	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	0	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	198361	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	198361	0	0
T1	17075	188	0	0
T2	8713	10	0	0
T3	2829	7	0	0
T4	309217	213	0	0
T7	12949	12	0	0
T8	1752	10	0	0
T9	2356	10	0	0
T10	26464	804	0	0
T11	286011	17	0	0
T12	57831	120	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	198361	0	0
T1	17075	188	0	0
T2	8713	10	0	0
T3	2829	7	0	0
T4	309217	213	0	0
T7	12949	12	0	0
T8	1752	10	0	0
T9	2356	10	0	0
T10	26464	804	0	0
T11	286011	17	0	0
T12	57831	120	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	198361	0	0
T1	17075	188	0	0
T2	8713	10	0	0
T3	2829	7	0	0
T4	309217	213	0	0
T7	12949	12	0	0
T8	1752	10	0	0
T9	2356	10	0	0
T10	26464	804	0	0
T11	286011	17	0	0
T12	57831	120	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	2899074	0	0
T1	17075	195	0	0
T2	8713	78	0	0
T3	2829	71	0	0
T4	309217	69455	0	0
T7	12949	76	0	0
T8	1752	10	0	0
T9	2356	11	0	0
T10	26464	644	0	0
T11	286011	64	0	0
T12	57831	951	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	198361	0	0
T1	17075	188	0	0
T2	8713	10	0	0
T3	2829	7	0	0
T4	309217	213	0	0
T7	12949	12	0	0
T8	1752	10	0	0
T9	2356	10	0	0
T10	26464	804	0	0
T11	286011	17	0	0
T12	57831	120	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	198361	0	0
T1	17075	188	0	0
T2	8713	10	0	0
T3	2829	7	0	0
T4	309217	213	0	0
T7	12949	12	0	0
T8	1752	10	0	0
T9	2356	10	0	0
T10	26464	804	0	0
T11	286011	17	0	0
T12	57831	120	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	579683	0	0
T1	17075	192	0	0
T2	8713	30	0	0
T3	2829	7	0	0
T4	309217	3886	0	0
T7	12949	13	0	0
T8	1752	11	0	0
T9	2356	10	0	0
T10	26464	979	0	0
T11	286011	25	0	0
T12	57831	139	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	198361	0	0
T1	17075	188	0	0
T2	8713	10	0	0
T3	2829	7	0	0
T4	309217	213	0	0
T7	12949	12	0	0
T8	1752	10	0	0
T9	2356	10	0	0
T10	26464	804	0	0
T11	286011	17	0	0
T12	57831	120	0	0

Line Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_34.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	201193	0	0
GntImpliesValid_A	414643205	201193	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	201193	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	2933781	0	0
ReadyAndValidImplyGrant_A	414643205	201193	0	0
ReqAndReadyImplyGrant_A	414643205	201193	0	0
ReqImpliesValid_A	414643205	583965	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	0	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	201193	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	201193	0	0
T1	17075	143	0	0
T2	8713	10	0	0
T3	2829	1	0	0
T4	309217	227	0	0
T7	12949	12	0	0
T8	1752	9	0	0
T9	2356	15	0	0
T10	26464	279	0	0
T11	286011	16	0	0
T12	57831	130	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	201193	0	0
T1	17075	143	0	0
T2	8713	10	0	0
T3	2829	1	0	0
T4	309217	227	0	0
T7	12949	12	0	0
T8	1752	9	0	0
T9	2356	15	0	0
T10	26464	279	0	0
T11	286011	16	0	0
T12	57831	130	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	201193	0	0
T1	17075	143	0	0
T2	8713	10	0	0
T3	2829	1	0	0
T4	309217	227	0	0
T7	12949	12	0	0
T8	1752	9	0	0
T9	2356	15	0	0
T10	26464	279	0	0
T11	286011	16	0	0
T12	57831	130	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	2933781	0	0
T1	17075	152	0	0
T2	8713	53	0	0
T3	2829	7	0	0
T4	309217	73555	0	0
T7	12949	67	0	0
T8	1752	10	0	0
T9	2356	15	0	0
T10	26464	290	0	0
T11	286011	53	0	0
T12	57831	1012	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	201193	0	0
T1	17075	143	0	0
T2	8713	10	0	0
T3	2829	1	0	0
T4	309217	227	0	0
T7	12949	12	0	0
T8	1752	9	0	0
T9	2356	15	0	0
T10	26464	279	0	0
T11	286011	16	0	0
T12	57831	130	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	201193	0	0
T1	17075	143	0	0
T2	8713	10	0	0
T3	2829	1	0	0
T4	309217	227	0	0
T7	12949	12	0	0
T8	1752	9	0	0
T9	2356	15	0	0
T10	26464	279	0	0
T11	286011	16	0	0
T12	57831	130	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	583965	0	0
T1	17075	145	0	0
T2	8713	23	0	0
T3	2829	1	0	0
T4	309217	3659	0	0
T7	12949	21	0	0
T8	1752	9	0	0
T9	2356	16	0	0
T10	26464	284	0	0
T11	286011	24	0	0
T12	57831	151	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	201193	0	0
T1	17075	143	0	0
T2	8713	10	0	0
T3	2829	1	0	0
T4	309217	227	0	0
T7	12949	12	0	0
T8	1752	9	0	0
T9	2356	15	0	0
T10	26464	279	0	0
T11	286011	16	0	0
T12	57831	130	0	0

Line Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_36.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	205914	0	0
GntImpliesValid_A	414643205	205914	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	205914	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	5722818	0	0
ReadyAndValidImplyGrant_A	414643205	205914	0	0
ReqAndReadyImplyGrant_A	414643205	205914	0	0
ReqImpliesValid_A	414643205	1323536	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	0	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	205914	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	205914	0	0
T1	17075	133	0	0
T2	8713	11	0	0
T3	2829	11	0	0
T4	309217	234	0	0
T7	12949	16	0	0
T8	1752	11	0	0
T9	2356	16	0	0
T10	26464	298	0	0
T11	286011	8	0	0
T12	57831	84	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	205914	0	0
T1	17075	133	0	0
T2	8713	11	0	0
T3	2829	11	0	0
T4	309217	234	0	0
T7	12949	16	0	0
T8	1752	11	0	0
T9	2356	16	0	0
T10	26464	298	0	0
T11	286011	8	0	0
T12	57831	84	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	205914	0	0
T1	17075	133	0	0
T2	8713	11	0	0
T3	2829	11	0	0
T4	309217	234	0	0
T7	12949	16	0	0
T8	1752	11	0	0
T9	2356	16	0	0
T10	26464	298	0	0
T11	286011	8	0	0
T12	57831	84	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	5722818	0	0
T1	17075	916	0	0
T2	8713	178	0	0
T3	2829	80	0	0
T4	309217	105315	0	0
T7	12949	209	0	0
T8	1752	81	0	0
T9	2356	103	0	0
T10	26464	1258	0	0
T11	286011	77	0	0
T12	57831	1129	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	205914	0	0
T1	17075	133	0	0
T2	8713	11	0	0
T3	2829	11	0	0
T4	309217	234	0	0
T7	12949	16	0	0
T8	1752	11	0	0
T9	2356	16	0	0
T10	26464	298	0	0
T11	286011	8	0	0
T12	57831	84	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	205914	0	0
T1	17075	133	0	0
T2	8713	11	0	0
T3	2829	11	0	0
T4	309217	234	0	0
T7	12949	16	0	0
T8	1752	11	0	0
T9	2356	16	0	0
T10	26464	298	0	0
T11	286011	8	0	0
T12	57831	84	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	1323536	0	0
T1	17075	168	0	0
T2	8713	34	0	0
T3	2829	11	0	0
T4	309217	8240	0	0
T7	12949	16	0	0
T8	1752	11	0	0
T9	2356	33	0	0
T10	26464	352	0	0
T11	286011	8	0	0
T12	57831	149	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	205914	0	0
T1	17075	133	0	0
T2	8713	11	0	0
T3	2829	11	0	0
T4	309217	234	0	0
T7	12949	16	0	0
T8	1752	11	0	0
T9	2356	16	0	0
T10	26464	298	0	0
T11	286011	8	0	0
T12	57831	84	0	0

Line Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_38.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	185128	0	0
GntImpliesValid_A	414643205	185128	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	185128	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	5298640	0	0
ReadyAndValidImplyGrant_A	414643205	185128	0	0
ReqAndReadyImplyGrant_A	414643205	185128	0	0
ReqImpliesValid_A	414643205	1014398	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	0	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	185128	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	185128	0	0
T1	17075	357	0	0
T2	8713	10	0	0
T3	2829	4	0	0
T4	309217	242	0	0
T7	12949	13	0	0
T8	1752	5	0	0
T9	2356	10	0	0
T10	26464	522	0	0
T11	286011	13	0	0
T12	57831	91	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	185128	0	0
T1	17075	357	0	0
T2	8713	10	0	0
T3	2829	4	0	0
T4	309217	242	0	0
T7	12949	13	0	0
T8	1752	5	0	0
T9	2356	10	0	0
T10	26464	522	0	0
T11	286011	13	0	0
T12	57831	91	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	185128	0	0
T1	17075	357	0	0
T2	8713	10	0	0
T3	2829	4	0	0
T4	309217	242	0	0
T7	12949	13	0	0
T8	1752	5	0	0
T9	2356	10	0	0
T10	26464	522	0	0
T11	286011	13	0	0
T12	57831	91	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	5298640	0	0
T1	17075	797	0	0
T2	8713	50	0	0
T3	2829	47	0	0
T4	309217	269910	0	0
T7	12949	140	0	0
T8	1752	25	0	0
T9	2356	51	0	0
T10	26464	1504	0	0
T11	286011	87	0	0
T12	57831	919	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	185128	0	0
T1	17075	357	0	0
T2	8713	10	0	0
T3	2829	4	0	0
T4	309217	242	0	0
T7	12949	13	0	0
T8	1752	5	0	0
T9	2356	10	0	0
T10	26464	522	0	0
T11	286011	13	0	0
T12	57831	91	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	185128	0	0
T1	17075	357	0	0
T2	8713	10	0	0
T3	2829	4	0	0
T4	309217	242	0	0
T7	12949	13	0	0
T8	1752	5	0	0
T9	2356	10	0	0
T10	26464	522	0	0
T11	286011	13	0	0
T12	57831	91	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	1014398	0	0
T1	17075	1145	0	0
T2	8713	10	0	0
T3	2829	4	0	0
T4	309217	17646	0	0
T7	12949	13	0	0
T8	1752	5	0	0
T9	2356	15	0	0
T10	26464	1285	0	0
T11	286011	25	0	0
T12	57831	106	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	185128	0	0
T1	17075	357	0	0
T2	8713	10	0	0
T3	2829	4	0	0
T4	309217	242	0	0
T7	12949	13	0	0
T8	1752	5	0	0
T9	2356	10	0	0
T10	26464	522	0	0
T11	286011	13	0	0
T12	57831	91	0	0

Line Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_40.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	191337	0	0
GntImpliesValid_A	414643205	191337	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	191337	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	5145112	0	0
ReadyAndValidImplyGrant_A	414643205	191337	0	0
ReqAndReadyImplyGrant_A	414643205	191337	0	0
ReqImpliesValid_A	414643205	920429	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	0	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	191337	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	191337	0	0
T1	17075	163	0	0
T2	8713	12	0	0
T3	2829	5	0	0
T4	309217	224	0	0
T7	12949	11	0	0
T8	1752	7	0	0
T9	2356	15	0	0
T10	26464	255	0	0
T11	286011	19	0	0
T12	57831	89	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	191337	0	0
T1	17075	163	0	0
T2	8713	12	0	0
T3	2829	5	0	0
T4	309217	224	0	0
T7	12949	11	0	0
T8	1752	7	0	0
T9	2356	15	0	0
T10	26464	255	0	0
T11	286011	19	0	0
T12	57831	89	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	191337	0	0
T1	17075	163	0	0
T2	8713	12	0	0
T3	2829	5	0	0
T4	309217	224	0	0
T7	12949	11	0	0
T8	1752	7	0	0
T9	2356	15	0	0
T10	26464	255	0	0
T11	286011	19	0	0
T12	57831	89	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	5145112	0	0
T1	17075	750	0	0
T2	8713	135	0	0
T3	2829	32	0	0
T4	309217	88192	0	0
T7	12949	116	0	0
T8	1752	29	0	0
T9	2356	113	0	0
T10	26464	1019	0	0
T11	286011	119	0	0
T12	57831	2892	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	191337	0	0
T1	17075	163	0	0
T2	8713	12	0	0
T3	2829	5	0	0
T4	309217	224	0	0
T7	12949	11	0	0
T8	1752	7	0	0
T9	2356	15	0	0
T10	26464	255	0	0
T11	286011	19	0	0
T12	57831	89	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	191337	0	0
T1	17075	163	0	0
T2	8713	12	0	0
T3	2829	5	0	0
T4	309217	224	0	0
T7	12949	11	0	0
T8	1752	7	0	0
T9	2356	15	0	0
T10	26464	255	0	0
T11	286011	19	0	0
T12	57831	89	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	920429	0	0
T1	17075	197	0	0
T2	8713	16	0	0
T3	2829	5	0	0
T4	309217	6791	0	0
T7	12949	11	0	0
T8	1752	10	0	0
T9	2356	25	0	0
T10	26464	301	0	0
T11	286011	31	0	0
T12	57831	186	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	191337	0	0
T1	17075	163	0	0
T2	8713	12	0	0
T3	2829	5	0	0
T4	309217	224	0	0
T7	12949	11	0	0
T8	1752	7	0	0
T9	2356	15	0	0
T10	26464	255	0	0
T11	286011	19	0	0
T12	57831	89	0	0

Line Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_42.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	194205	0	0
GntImpliesValid_A	414643205	194205	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	194205	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	5349208	0	0
ReadyAndValidImplyGrant_A	414643205	194205	0	0
ReqAndReadyImplyGrant_A	414643205	194205	0	0
ReqImpliesValid_A	414643205	1188129	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	0	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	194205	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	194205	0	0
T1	17075	131	0	0
T2	8713	15	0	0
T3	2829	8	0	0
T4	309217	210	0	0
T7	12949	16	0	0
T8	1752	8	0	0
T9	2356	13	0	0
T10	26464	952	0	0
T11	286011	8	0	0
T12	57831	118	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	194205	0	0
T1	17075	131	0	0
T2	8713	15	0	0
T3	2829	8	0	0
T4	309217	210	0	0
T7	12949	16	0	0
T8	1752	8	0	0
T9	2356	13	0	0
T10	26464	952	0	0
T11	286011	8	0	0
T12	57831	118	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	194205	0	0
T1	17075	131	0	0
T2	8713	15	0	0
T3	2829	8	0	0
T4	309217	210	0	0
T7	12949	16	0	0
T8	1752	8	0	0
T9	2356	13	0	0
T10	26464	952	0	0
T11	286011	8	0	0
T12	57831	118	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	5349208	0	0
T1	17075	847	0	0
T2	8713	97	0	0
T3	2829	71	0	0
T4	309217	98424	0	0
T7	12949	184	0	0
T8	1752	66	0	0
T9	2356	82	0	0
T10	26464	2426	0	0
T11	286011	37	0	0
T12	57831	835	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	194205	0	0
T1	17075	131	0	0
T2	8713	15	0	0
T3	2829	8	0	0
T4	309217	210	0	0
T7	12949	16	0	0
T8	1752	8	0	0
T9	2356	13	0	0
T10	26464	952	0	0
T11	286011	8	0	0
T12	57831	118	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	194205	0	0
T1	17075	131	0	0
T2	8713	15	0	0
T3	2829	8	0	0
T4	309217	210	0	0
T7	12949	16	0	0
T8	1752	8	0	0
T9	2356	13	0	0
T10	26464	952	0	0
T11	286011	8	0	0
T12	57831	118	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	1188129	0	0
T1	17075	157	0	0
T2	8713	25	0	0
T3	2829	8	0	0
T4	309217	7065	0	0
T7	12949	18	0	0
T8	1752	19	0	0
T9	2356	18	0	0
T10	26464	2617	0	0
T11	286011	8	0	0
T12	57831	161	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	194205	0	0
T1	17075	131	0	0
T2	8713	15	0	0
T3	2829	8	0	0
T4	309217	210	0	0
T7	12949	16	0	0
T8	1752	8	0	0
T9	2356	13	0	0
T10	26464	952	0	0
T11	286011	8	0	0
T12	57831	118	0	0

Line Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T10,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T10,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_43.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	205373	0	0
GntImpliesValid_A	414643205	205373	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	205373	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	2917062	0	0
ReadyAndValidImplyGrant_A	414643205	205373	0	0
ReqAndReadyImplyGrant_A	414643205	205373	0	0
ReqImpliesValid_A	414643205	643610	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	0	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	205373	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	205373	0	0
T1	17075	144	0	0
T2	8713	9	0	0
T3	2829	6	0	0
T4	309217	203	0	0
T7	12949	18	0	0
T8	1752	11	0	0
T9	2356	11	0	0
T10	26464	257	0	0
T11	286011	14	0	0
T12	57831	93	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	205373	0	0
T1	17075	144	0	0
T2	8713	9	0	0
T3	2829	6	0	0
T4	309217	203	0	0
T7	12949	18	0	0
T8	1752	11	0	0
T9	2356	11	0	0
T10	26464	257	0	0
T11	286011	14	0	0
T12	57831	93	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	205373	0	0
T1	17075	144	0	0
T2	8713	9	0	0
T3	2829	6	0	0
T4	309217	203	0	0
T7	12949	18	0	0
T8	1752	11	0	0
T9	2356	11	0	0
T10	26464	257	0	0
T11	286011	14	0	0
T12	57831	93	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	2917062	0	0
T1	17075	150	0	0
T2	8713	90	0	0
T3	2829	71	0	0
T4	309217	68856	0	0
T7	12949	111	0	0
T8	1752	12	0	0
T9	2356	12	0	0
T10	26464	269	0	0
T11	286011	65	0	0
T12	57831	683	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	205373	0	0
T1	17075	144	0	0
T2	8713	9	0	0
T3	2829	6	0	0
T4	309217	203	0	0
T7	12949	18	0	0
T8	1752	11	0	0
T9	2356	11	0	0
T10	26464	257	0	0
T11	286011	14	0	0
T12	57831	93	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	205373	0	0
T1	17075	144	0	0
T2	8713	9	0	0
T3	2829	6	0	0
T4	309217	203	0	0
T7	12949	18	0	0
T8	1752	11	0	0
T9	2356	11	0	0
T10	26464	257	0	0
T11	286011	14	0	0
T12	57831	93	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	643610	0	0
T1	17075	148	0	0
T2	8713	9	0	0
T3	2829	6	0	0
T4	309217	3469	0	0
T7	12949	27	0	0
T8	1752	11	0	0
T9	2356	11	0	0
T10	26464	261	0	0
T11	286011	17	0	0
T12	57831	131	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	205373	0	0
T1	17075	144	0	0
T2	8713	9	0	0
T3	2829	6	0	0
T4	309217	203	0	0
T7	12949	18	0	0
T8	1752	11	0	0
T9	2356	11	0	0
T10	26464	257	0	0
T11	286011	14	0	0
T12	57831	93	0	0

Line Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_44.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	190880	0	0
GntImpliesValid_A	414643205	190880	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	190880	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	2863973	0	0
ReadyAndValidImplyGrant_A	414643205	190880	0	0
ReqAndReadyImplyGrant_A	414643205	190880	0	0
ReqImpliesValid_A	414643205	485553	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	0	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	190880	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	190880	0	0
T1	17075	158	0	0
T2	8713	8	0	0
T3	2829	8	0	0
T4	309217	191	0	0
T7	12949	17	0	0
T8	1752	10	0	0
T9	2356	17	0	0
T10	26464	297	0	0
T11	286011	19	0	0
T12	57831	117	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	190880	0	0
T1	17075	158	0	0
T2	8713	8	0	0
T3	2829	8	0	0
T4	309217	191	0	0
T7	12949	17	0	0
T8	1752	10	0	0
T9	2356	17	0	0
T10	26464	297	0	0
T11	286011	19	0	0
T12	57831	117	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	190880	0	0
T1	17075	158	0	0
T2	8713	8	0	0
T3	2829	8	0	0
T4	309217	191	0	0
T7	12949	17	0	0
T8	1752	10	0	0
T9	2356	17	0	0
T10	26464	297	0	0
T11	286011	19	0	0
T12	57831	117	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	2863973	0	0
T1	17075	166	0	0
T2	8713	67	0	0
T3	2829	51	0	0
T4	309217	61157	0	0
T7	12949	124	0	0
T8	1752	11	0	0
T9	2356	17	0	0
T10	26464	301	0	0
T11	286011	56	0	0
T12	57831	819	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	190880	0	0
T1	17075	158	0	0
T2	8713	8	0	0
T3	2829	8	0	0
T4	309217	191	0	0
T7	12949	17	0	0
T8	1752	10	0	0
T9	2356	17	0	0
T10	26464	297	0	0
T11	286011	19	0	0
T12	57831	117	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	190880	0	0
T1	17075	158	0	0
T2	8713	8	0	0
T3	2829	8	0	0
T4	309217	191	0	0
T7	12949	17	0	0
T8	1752	10	0	0
T9	2356	17	0	0
T10	26464	297	0	0
T11	286011	19	0	0
T12	57831	117	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	485553	0	0
T1	17075	161	0	0
T2	8713	8	0	0
T3	2829	8	0	0
T4	309217	3752	0	0
T7	12949	24	0	0
T8	1752	10	0	0
T9	2356	18	0	0
T10	26464	309	0	0
T11	286011	32	0	0
T12	57831	139	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	190880	0	0
T1	17075	158	0	0
T2	8713	8	0	0
T3	2829	8	0	0
T4	309217	191	0	0
T7	12949	17	0	0
T8	1752	10	0	0
T9	2356	17	0	0
T10	26464	297	0	0
T11	286011	19	0	0
T12	57831	117	0	0

Line Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_45.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	197883	0	0
GntImpliesValid_A	414643205	197883	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	197883	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	2950706	0	0
ReadyAndValidImplyGrant_A	414643205	197883	0	0
ReqAndReadyImplyGrant_A	414643205	197883	0	0
ReqImpliesValid_A	414643205	552937	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	0	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	197883	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	197883	0	0
T1	17075	185	0	0
T2	8713	15	0	0
T3	2829	1	0	0
T4	309217	198	0	0
T7	12949	9	0	0
T8	1752	10	0	0
T9	2356	20	0	0
T10	26464	287	0	0
T11	286011	12	0	0
T12	57831	113	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	197883	0	0
T1	17075	185	0	0
T2	8713	15	0	0
T3	2829	1	0	0
T4	309217	198	0	0
T7	12949	9	0	0
T8	1752	10	0	0
T9	2356	20	0	0
T10	26464	287	0	0
T11	286011	12	0	0
T12	57831	113	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	197883	0	0
T1	17075	185	0	0
T2	8713	15	0	0
T3	2829	1	0	0
T4	309217	198	0	0
T7	12949	9	0	0
T8	1752	10	0	0
T9	2356	20	0	0
T10	26464	287	0	0
T11	286011	12	0	0
T12	57831	113	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	2950706	0	0
T1	17075	187	0	0
T2	8713	95	0	0
T3	2829	7	0	0
T4	309217	70019	0	0
T7	12949	116	0	0
T8	1752	11	0	0
T9	2356	16	0	0
T10	26464	298	0	0
T11	286011	43	0	0
T12	57831	879	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	197883	0	0
T1	17075	185	0	0
T2	8713	15	0	0
T3	2829	1	0	0
T4	309217	198	0	0
T7	12949	9	0	0
T8	1752	10	0	0
T9	2356	20	0	0
T10	26464	287	0	0
T11	286011	12	0	0
T12	57831	113	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	197883	0	0
T1	17075	185	0	0
T2	8713	15	0	0
T3	2829	1	0	0
T4	309217	198	0	0
T7	12949	9	0	0
T8	1752	10	0	0
T9	2356	20	0	0
T10	26464	287	0	0
T11	286011	12	0	0
T12	57831	113	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	552937	0	0
T1	17075	194	0	0
T2	8713	19	0	0
T3	2829	1	0	0
T4	309217	2295	0	0
T7	12949	9	0	0
T8	1752	10	0	0
T9	2356	25	0	0
T10	26464	292	0	0
T11	286011	20	0	0
T12	57831	134	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	197883	0	0
T1	17075	185	0	0
T2	8713	15	0	0
T3	2829	1	0	0
T4	309217	198	0	0
T7	12949	9	0	0
T8	1752	10	0	0
T9	2356	20	0	0
T10	26464	287	0	0
T11	286011	12	0	0
T12	57831	113	0	0

Line Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T10,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T10,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_46.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	202131	0	0
GntImpliesValid_A	414643205	202131	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	202131	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	2957210	0	0
ReadyAndValidImplyGrant_A	414643205	202131	0	0
ReqAndReadyImplyGrant_A	414643205	202131	0	0
ReqImpliesValid_A	414643205	599251	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	0	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	202131	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	202131	0	0
T1	17075	148	0	0
T2	8713	11	0	0
T3	2829	3	0	0
T4	309217	192	0	0
T7	12949	13	0	0
T8	1752	8	0	0
T9	2356	8	0	0
T10	26464	290	0	0
T11	286011	9	0	0
T12	57831	121	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	202131	0	0
T1	17075	148	0	0
T2	8713	11	0	0
T3	2829	3	0	0
T4	309217	192	0	0
T7	12949	13	0	0
T8	1752	8	0	0
T9	2356	8	0	0
T10	26464	290	0	0
T11	286011	9	0	0
T12	57831	121	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	202131	0	0
T1	17075	148	0	0
T2	8713	11	0	0
T3	2829	3	0	0
T4	309217	192	0	0
T7	12949	13	0	0
T8	1752	8	0	0
T9	2356	8	0	0
T10	26464	290	0	0
T11	286011	9	0	0
T12	57831	121	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	2957210	0	0
T1	17075	150	0	0
T2	8713	111	0	0
T3	2829	27	0	0
T4	309217	64633	0	0
T7	12949	93	0	0
T8	1752	9	0	0
T9	2356	9	0	0
T10	26464	302	0	0
T11	286011	45	0	0
T12	57831	785	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	202131	0	0
T1	17075	148	0	0
T2	8713	11	0	0
T3	2829	3	0	0
T4	309217	192	0	0
T7	12949	13	0	0
T8	1752	8	0	0
T9	2356	8	0	0
T10	26464	290	0	0
T11	286011	9	0	0
T12	57831	121	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	202131	0	0
T1	17075	148	0	0
T2	8713	11	0	0
T3	2829	3	0	0
T4	309217	192	0	0
T7	12949	13	0	0
T8	1752	8	0	0
T9	2356	8	0	0
T10	26464	290	0	0
T11	286011	9	0	0
T12	57831	121	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	599251	0	0
T1	17075	156	0	0
T2	8713	11	0	0
T3	2829	3	0	0
T4	309217	4005	0	0
T7	12949	26	0	0
T8	1752	8	0	0
T9	2356	8	0	0
T10	26464	294	0	0
T11	286011	9	0	0
T12	57831	174	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	202131	0	0
T1	17075	148	0	0
T2	8713	11	0	0
T3	2829	3	0	0
T4	309217	192	0	0
T7	12949	13	0	0
T8	1752	8	0	0
T9	2356	8	0	0
T10	26464	290	0	0
T11	286011	9	0	0
T12	57831	121	0	0

Line Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_47.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	198886	0	0
GntImpliesValid_A	414643205	198886	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	198886	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	2905584	0	0
ReadyAndValidImplyGrant_A	414643205	198886	0	0
ReqAndReadyImplyGrant_A	414643205	198886	0	0
ReqImpliesValid_A	414643205	563129	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	0	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	198886	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	198886	0	0
T1	17075	137	0	0
T2	8713	12	0	0
T3	2829	1	0	0
T4	309217	226	0	0
T7	12949	15	0	0
T8	1752	9	0	0
T9	2356	13	0	0
T10	26464	721	0	0
T11	286011	9	0	0
T12	57831	107	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	198886	0	0
T1	17075	137	0	0
T2	8713	12	0	0
T3	2829	1	0	0
T4	309217	226	0	0
T7	12949	15	0	0
T8	1752	9	0	0
T9	2356	13	0	0
T10	26464	721	0	0
T11	286011	9	0	0
T12	57831	107	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	198886	0	0
T1	17075	137	0	0
T2	8713	12	0	0
T3	2829	1	0	0
T4	309217	226	0	0
T7	12949	15	0	0
T8	1752	9	0	0
T9	2356	13	0	0
T10	26464	721	0	0
T11	286011	9	0	0
T12	57831	107	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	2905584	0	0
T1	17075	147	0	0
T2	8713	62	0	0
T3	2829	18	0	0
T4	309217	67743	0	0
T7	12949	107	0	0
T8	1752	10	0	0
T9	2356	13	0	0
T10	26464	654	0	0
T11	286011	34	0	0
T12	57831	804	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	198886	0	0
T1	17075	137	0	0
T2	8713	12	0	0
T3	2829	1	0	0
T4	309217	226	0	0
T7	12949	15	0	0
T8	1752	9	0	0
T9	2356	13	0	0
T10	26464	721	0	0
T11	286011	9	0	0
T12	57831	107	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	198886	0	0
T1	17075	137	0	0
T2	8713	12	0	0
T3	2829	1	0	0
T4	309217	226	0	0
T7	12949	15	0	0
T8	1752	9	0	0
T9	2356	13	0	0
T10	26464	721	0	0
T11	286011	9	0	0
T12	57831	107	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	563129	0	0
T1	17075	138	0	0
T2	8713	14	0	0
T3	2829	1	0	0
T4	309217	5125	0	0
T7	12949	15	0	0
T8	1752	9	0	0
T9	2356	14	0	0
T10	26464	804	0	0
T11	286011	9	0	0
T12	57831	133	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	198886	0	0
T1	17075	137	0	0
T2	8713	12	0	0
T3	2829	1	0	0
T4	309217	226	0	0
T7	12949	15	0	0
T8	1752	9	0	0
T9	2356	13	0	0
T10	26464	721	0	0
T11	286011	9	0	0
T12	57831	107	0	0

Line Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_48.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	204347	0	0
GntImpliesValid_A	414643205	204347	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	204347	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	2925911	0	0
ReadyAndValidImplyGrant_A	414643205	204347	0	0
ReqAndReadyImplyGrant_A	414643205	204347	0	0
ReqImpliesValid_A	414643205	616279	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	0	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	204347	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	204347	0	0
T1	17075	152	0	0
T2	8713	9	0	0
T3	2829	3	0	0
T4	309217	221	0	0
T7	12949	16	0	0
T8	1752	12	0	0
T9	2356	12	0	0
T10	26464	523	0	0
T11	286011	14	0	0
T12	57831	102	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	204347	0	0
T1	17075	152	0	0
T2	8713	9	0	0
T3	2829	3	0	0
T4	309217	221	0	0
T7	12949	16	0	0
T8	1752	12	0	0
T9	2356	12	0	0
T10	26464	523	0	0
T11	286011	14	0	0
T12	57831	102	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	204347	0	0
T1	17075	152	0	0
T2	8713	9	0	0
T3	2829	3	0	0
T4	309217	221	0	0
T7	12949	16	0	0
T8	1752	12	0	0
T9	2356	12	0	0
T10	26464	523	0	0
T11	286011	14	0	0
T12	57831	102	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	2925911	0	0
T1	17075	162	0	0
T2	8713	64	0	0
T3	2829	11	0	0
T4	309217	77386	0	0
T7	12949	116	0	0
T8	1752	11	0	0
T9	2356	12	0	0
T10	26464	469	0	0
T11	286011	57	0	0
T12	57831	828	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	204347	0	0
T1	17075	152	0	0
T2	8713	9	0	0
T3	2829	3	0	0
T4	309217	221	0	0
T7	12949	16	0	0
T8	1752	12	0	0
T9	2356	12	0	0
T10	26464	523	0	0
T11	286011	14	0	0
T12	57831	102	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	204347	0	0
T1	17075	152	0	0
T2	8713	9	0	0
T3	2829	3	0	0
T4	309217	221	0	0
T7	12949	16	0	0
T8	1752	12	0	0
T9	2356	12	0	0
T10	26464	523	0	0
T11	286011	14	0	0
T12	57831	102	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	616279	0	0
T1	17075	153	0	0
T2	8713	9	0	0
T3	2829	3	0	0
T4	309217	3046	0	0
T7	12949	16	0	0
T8	1752	14	0	0
T9	2356	13	0	0
T10	26464	593	0	0
T11	286011	23	0	0
T12	57831	122	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	204347	0	0
T1	17075	152	0	0
T2	8713	9	0	0
T3	2829	3	0	0
T4	309217	221	0	0
T7	12949	16	0	0
T8	1752	12	0	0
T9	2356	12	0	0
T10	26464	523	0	0
T11	286011	14	0	0
T12	57831	102	0	0

Line Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_49.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	203381	0	0
GntImpliesValid_A	414643205	203381	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	203381	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	2899828	0	0
ReadyAndValidImplyGrant_A	414643205	203381	0	0
ReqAndReadyImplyGrant_A	414643205	203381	0	0
ReqImpliesValid_A	414643205	560428	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	0	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	203381	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	203381	0	0
T1	17075	650	0	0
T2	8713	10	0	0
T3	2829	3	0	0
T4	309217	205	0	0
T7	12949	15	0	0
T8	1752	5	0	0
T9	2356	11	0	0
T10	26464	305	0	0
T11	286011	10	0	0
T12	57831	101	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	203381	0	0
T1	17075	650	0	0
T2	8713	10	0	0
T3	2829	3	0	0
T4	309217	205	0	0
T7	12949	15	0	0
T8	1752	5	0	0
T9	2356	11	0	0
T10	26464	305	0	0
T11	286011	10	0	0
T12	57831	101	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	203381	0	0
T1	17075	650	0	0
T2	8713	10	0	0
T3	2829	3	0	0
T4	309217	205	0	0
T7	12949	15	0	0
T8	1752	5	0	0
T9	2356	11	0	0
T10	26464	305	0	0
T11	286011	10	0	0
T12	57831	101	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	2899828	0	0
T1	17075	183	0	0
T2	8713	84	0	0
T3	2829	29	0	0
T4	309217	65660	0	0
T7	12949	105	0	0
T8	1752	6	0	0
T9	2356	12	0	0
T10	26464	312	0	0
T11	286011	41	0	0
T12	57831	676	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	203381	0	0
T1	17075	650	0	0
T2	8713	10	0	0
T3	2829	3	0	0
T4	309217	205	0	0
T7	12949	15	0	0
T8	1752	5	0	0
T9	2356	11	0	0
T10	26464	305	0	0
T11	286011	10	0	0
T12	57831	101	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	203381	0	0
T1	17075	650	0	0
T2	8713	10	0	0
T3	2829	3	0	0
T4	309217	205	0	0
T7	12949	15	0	0
T8	1752	5	0	0
T9	2356	11	0	0
T10	26464	305	0	0
T11	286011	10	0	0
T12	57831	101	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	560428	0	0
T1	17075	1128	0	0
T2	8713	14	0	0
T3	2829	3	0	0
T4	309217	4036	0	0
T7	12949	20	0	0
T8	1752	5	0	0
T9	2356	11	0	0
T10	26464	313	0	0
T11	286011	12	0	0
T12	57831	103	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	203381	0	0
T1	17075	650	0	0
T2	8713	10	0	0
T3	2829	3	0	0
T4	309217	205	0	0
T7	12949	15	0	0
T8	1752	5	0	0
T9	2356	11	0	0
T10	26464	305	0	0
T11	286011	10	0	0
T12	57831	101	0	0

Line Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_50.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	198225	0	0
GntImpliesValid_A	414643205	198225	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	198225	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	2876716	0	0
ReadyAndValidImplyGrant_A	414643205	198225	0	0
ReqAndReadyImplyGrant_A	414643205	198225	0	0
ReqImpliesValid_A	414643205	535402	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	0	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	198225	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	198225	0	0
T1	17075	305	0	0
T2	8713	11	0	0
T3	2829	72	0	0
T4	309217	226	0	0
T7	12949	19	0	0
T8	1752	14	0	0
T9	2356	11	0	0
T10	26464	757	0	0
T11	286011	17	0	0
T12	57831	94	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	198225	0	0
T1	17075	305	0	0
T2	8713	11	0	0
T3	2829	72	0	0
T4	309217	226	0	0
T7	12949	19	0	0
T8	1752	14	0	0
T9	2356	11	0	0
T10	26464	757	0	0
T11	286011	17	0	0
T12	57831	94	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	198225	0	0
T1	17075	305	0	0
T2	8713	11	0	0
T3	2829	72	0	0
T4	309217	226	0	0
T7	12949	19	0	0
T8	1752	14	0	0
T9	2356	11	0	0
T10	26464	757	0	0
T11	286011	17	0	0
T12	57831	94	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	2876716	0	0
T1	17075	282	0	0
T2	8713	76	0	0
T3	2829	453	0	0
T4	309217	72595	0	0
T7	12949	142	0	0
T8	1752	14	0	0
T9	2356	12	0	0
T10	26464	660	0	0
T11	286011	63	0	0
T12	57831	742	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	198225	0	0
T1	17075	305	0	0
T2	8713	11	0	0
T3	2829	72	0	0
T4	309217	226	0	0
T7	12949	19	0	0
T8	1752	14	0	0
T9	2356	11	0	0
T10	26464	757	0	0
T11	286011	17	0	0
T12	57831	94	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	198225	0	0
T1	17075	305	0	0
T2	8713	11	0	0
T3	2829	72	0	0
T4	309217	226	0	0
T7	12949	19	0	0
T8	1752	14	0	0
T9	2356	11	0	0
T10	26464	757	0	0
T11	286011	17	0	0
T12	57831	94	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	535402	0	0
T1	17075	339	0	0
T2	8713	11	0	0
T3	2829	208	0	0
T4	309217	3160	0	0
T7	12949	19	0	0
T8	1752	15	0	0
T9	2356	11	0	0
T10	26464	870	0	0
T11	286011	28	0	0
T12	57831	96	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	198225	0	0
T1	17075	305	0	0
T2	8713	11	0	0
T3	2829	72	0	0
T4	309217	226	0	0
T7	12949	19	0	0
T8	1752	14	0	0
T9	2356	11	0	0
T10	26464	757	0	0
T11	286011	17	0	0
T12	57831	94	0	0

Line Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_51.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	220851	0	0
GntImpliesValid_A	414643205	220851	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	220851	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	3037339	0	0
ReadyAndValidImplyGrant_A	414643205	220851	0	0
ReqAndReadyImplyGrant_A	414643205	220851	0	0
ReqImpliesValid_A	414643205	579057	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	0	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	220851	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	220851	0	0
T1	17075	180	0	0
T2	8713	13	0	0
T3	2829	7	0	0
T4	309217	215	0	0
T7	12949	13	0	0
T8	1752	7	0	0
T9	2356	18	0	0
T10	26464	284	0	0
T11	286011	9	0	0
T12	57831	191	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	220851	0	0
T1	17075	180	0	0
T2	8713	13	0	0
T3	2829	7	0	0
T4	309217	215	0	0
T7	12949	13	0	0
T8	1752	7	0	0
T9	2356	18	0	0
T10	26464	284	0	0
T11	286011	9	0	0
T12	57831	191	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	220851	0	0
T1	17075	180	0	0
T2	8713	13	0	0
T3	2829	7	0	0
T4	309217	215	0	0
T7	12949	13	0	0
T8	1752	7	0	0
T9	2356	18	0	0
T10	26464	284	0	0
T11	286011	9	0	0
T12	57831	191	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	3037339	0	0
T1	17075	185	0	0
T2	8713	106	0	0
T3	2829	79	0	0
T4	309217	68245	0	0
T7	12949	97	0	0
T8	1752	8	0	0
T9	2356	18	0	0
T10	26464	296	0	0
T11	286011	43	0	0
T12	57831	1509	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	220851	0	0
T1	17075	180	0	0
T2	8713	13	0	0
T3	2829	7	0	0
T4	309217	215	0	0
T7	12949	13	0	0
T8	1752	7	0	0
T9	2356	18	0	0
T10	26464	284	0	0
T11	286011	9	0	0
T12	57831	191	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	220851	0	0
T1	17075	180	0	0
T2	8713	13	0	0
T3	2829	7	0	0
T4	309217	215	0	0
T7	12949	13	0	0
T8	1752	7	0	0
T9	2356	18	0	0
T10	26464	284	0	0
T11	286011	9	0	0
T12	57831	191	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	579057	0	0
T1	17075	186	0	0
T2	8713	13	0	0
T3	2829	7	0	0
T4	309217	3042	0	0
T7	12949	17	0	0
T8	1752	7	0	0
T9	2356	19	0	0
T10	26464	288	0	0
T11	286011	9	0	0
T12	57831	252	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	220851	0	0
T1	17075	180	0	0
T2	8713	13	0	0
T3	2829	7	0	0
T4	309217	215	0	0
T7	12949	13	0	0
T8	1752	7	0	0
T9	2356	18	0	0
T10	26464	284	0	0
T11	286011	9	0	0
T12	57831	191	0	0

Line Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_52.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	192642	0	0
GntImpliesValid_A	414643205	192642	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	192642	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	2891904	0	0
ReadyAndValidImplyGrant_A	414643205	192642	0	0
ReqAndReadyImplyGrant_A	414643205	192642	0	0
ReqImpliesValid_A	414643205	538185	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	0	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	192642	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	192642	0	0
T1	17075	163	0	0
T2	8713	21	0	0
T3	2829	3	0	0
T4	309217	231	0	0
T7	12949	21	0	0
T8	1752	9	0	0
T9	2356	16	0	0
T10	26464	274	0	0
T11	286011	13	0	0
T12	57831	120	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	192642	0	0
T1	17075	163	0	0
T2	8713	21	0	0
T3	2829	3	0	0
T4	309217	231	0	0
T7	12949	21	0	0
T8	1752	9	0	0
T9	2356	16	0	0
T10	26464	274	0	0
T11	286011	13	0	0
T12	57831	120	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	192642	0	0
T1	17075	163	0	0
T2	8713	21	0	0
T3	2829	3	0	0
T4	309217	231	0	0
T7	12949	21	0	0
T8	1752	9	0	0
T9	2356	16	0	0
T10	26464	274	0	0
T11	286011	13	0	0
T12	57831	120	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	2891904	0	0
T1	17075	168	0	0
T2	8713	125	0	0
T3	2829	32	0	0
T4	309217	64447	0	0
T7	12949	161	0	0
T8	1752	10	0	0
T9	2356	16	0	0
T10	26464	286	0	0
T11	286011	49	0	0
T12	57831	894	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	192642	0	0
T1	17075	163	0	0
T2	8713	21	0	0
T3	2829	3	0	0
T4	309217	231	0	0
T7	12949	21	0	0
T8	1752	9	0	0
T9	2356	16	0	0
T10	26464	274	0	0
T11	286011	13	0	0
T12	57831	120	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	192642	0	0
T1	17075	163	0	0
T2	8713	21	0	0
T3	2829	3	0	0
T4	309217	231	0	0
T7	12949	21	0	0
T8	1752	9	0	0
T9	2356	16	0	0
T10	26464	274	0	0
T11	286011	13	0	0
T12	57831	120	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	538185	0	0
T1	17075	168	0	0
T2	8713	31	0	0
T3	2829	3	0	0
T4	309217	4941	0	0
T7	12949	44	0	0
T8	1752	9	0	0
T9	2356	17	0	0
T10	26464	278	0	0
T11	286011	13	0	0
T12	57831	145	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	192642	0	0
T1	17075	163	0	0
T2	8713	21	0	0
T3	2829	3	0	0
T4	309217	231	0	0
T7	12949	21	0	0
T8	1752	9	0	0
T9	2356	16	0	0
T10	26464	274	0	0
T11	286011	13	0	0
T12	57831	120	0	0

Line Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_53.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	207565	0	0
GntImpliesValid_A	414643205	207565	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	207565	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	2977142	0	0
ReadyAndValidImplyGrant_A	414643205	207565	0	0
ReqAndReadyImplyGrant_A	414643205	207565	0	0
ReqImpliesValid_A	414643205	598651	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	0	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	207565	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	207565	0	0
T1	17075	1249	0	0
T2	8713	15	0	0
T3	2829	6	0	0
T4	309217	188	0	0
T7	12949	22	0	0
T8	1752	12	0	0
T9	2356	7	0	0
T10	26464	291	0	0
T11	286011	13	0	0
T12	57831	115	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	207565	0	0
T1	17075	1249	0	0
T2	8713	15	0	0
T3	2829	6	0	0
T4	309217	188	0	0
T7	12949	22	0	0
T8	1752	12	0	0
T9	2356	7	0	0
T10	26464	291	0	0
T11	286011	13	0	0
T12	57831	115	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	207565	0	0
T1	17075	1249	0	0
T2	8713	15	0	0
T3	2829	6	0	0
T4	309217	188	0	0
T7	12949	22	0	0
T8	1752	12	0	0
T9	2356	7	0	0
T10	26464	291	0	0
T11	286011	13	0	0
T12	57831	115	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	2977142	0	0
T1	17075	796	0	0
T2	8713	103	0	0
T3	2829	65	0	0
T4	309217	55702	0	0
T7	12949	144	0	0
T8	1752	13	0	0
T9	2356	8	0	0
T10	26464	302	0	0
T11	286011	54	0	0
T12	57831	870	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	207565	0	0
T1	17075	1249	0	0
T2	8713	15	0	0
T3	2829	6	0	0
T4	309217	188	0	0
T7	12949	22	0	0
T8	1752	12	0	0
T9	2356	7	0	0
T10	26464	291	0	0
T11	286011	13	0	0
T12	57831	115	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	207565	0	0
T1	17075	1249	0	0
T2	8713	15	0	0
T3	2829	6	0	0
T4	309217	188	0	0
T7	12949	22	0	0
T8	1752	12	0	0
T9	2356	7	0	0
T10	26464	291	0	0
T11	286011	13	0	0
T12	57831	115	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	598651	0	0
T1	17075	1713	0	0
T2	8713	19	0	0
T3	2829	6	0	0
T4	309217	5328	0	0
T7	12949	52	0	0
T8	1752	12	0	0
T9	2356	7	0	0
T10	26464	296	0	0
T11	286011	20	0	0
T12	57831	123	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	207565	0	0
T1	17075	1249	0	0
T2	8713	15	0	0
T3	2829	6	0	0
T4	309217	188	0	0
T7	12949	22	0	0
T8	1752	12	0	0
T9	2356	7	0	0
T10	26464	291	0	0
T11	286011	13	0	0
T12	57831	115	0	0

Line Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T8

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T10
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T9,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_54.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	203145	0	0
GntImpliesValid_A	414643205	203145	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	203145	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	2906914	0	0
ReadyAndValidImplyGrant_A	414643205	203145	0	0
ReqAndReadyImplyGrant_A	414643205	203145	0	0
ReqImpliesValid_A	414643205	561912	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	0	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	203145	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	203145	0	0
T1	17075	160	0	0
T2	8713	5	0	0
T3	2829	3	0	0
T4	309217	218	0	0
T7	12949	18	0	0
T8	1752	6	0	0
T9	2356	11	0	0
T10	26464	749	0	0
T11	286011	13	0	0
T12	57831	100	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	203145	0	0
T1	17075	160	0	0
T2	8713	5	0	0
T3	2829	3	0	0
T4	309217	218	0	0
T7	12949	18	0	0
T8	1752	6	0	0
T9	2356	11	0	0
T10	26464	749	0	0
T11	286011	13	0	0
T12	57831	100	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	203145	0	0
T1	17075	160	0	0
T2	8713	5	0	0
T3	2829	3	0	0
T4	309217	218	0	0
T7	12949	18	0	0
T8	1752	6	0	0
T9	2356	11	0	0
T10	26464	749	0	0
T11	286011	13	0	0
T12	57831	100	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	2906914	0	0
T1	17075	166	0	0
T2	8713	43	0	0
T3	2829	29	0	0
T4	309217	69952	0	0
T7	12949	178	0	0
T8	1752	7	0	0
T9	2356	11	0	0
T10	26464	663	0	0
T11	286011	72	0	0
T12	57831	731	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	203145	0	0
T1	17075	160	0	0
T2	8713	5	0	0
T3	2829	3	0	0
T4	309217	218	0	0
T7	12949	18	0	0
T8	1752	6	0	0
T9	2356	11	0	0
T10	26464	749	0	0
T11	286011	13	0	0
T12	57831	100	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	203145	0	0
T1	17075	160	0	0
T2	8713	5	0	0
T3	2829	3	0	0
T4	309217	218	0	0
T7	12949	18	0	0
T8	1752	6	0	0
T9	2356	11	0	0
T10	26464	749	0	0
T11	286011	13	0	0
T12	57831	100	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	561912	0	0
T1	17075	164	0	0
T2	8713	5	0	0
T3	2829	3	0	0
T4	309217	4793	0	0
T7	12949	20	0	0
T8	1752	6	0	0
T9	2356	12	0	0
T10	26464	851	0	0
T11	286011	13	0	0
T12	57831	160	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	203145	0	0
T1	17075	160	0	0
T2	8713	5	0	0
T3	2829	3	0	0
T4	309217	218	0	0
T7	12949	18	0	0
T8	1752	6	0	0
T9	2356	11	0	0
T10	26464	749	0	0
T11	286011	13	0	0
T12	57831	100	0	0

Line Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T8,T9
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_55.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	200373	0	0
GntImpliesValid_A	414643205	200373	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	200373	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	2856299	0	0
ReadyAndValidImplyGrant_A	414643205	200373	0	0
ReqAndReadyImplyGrant_A	414643205	200373	0	0
ReqImpliesValid_A	414643205	520738	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	0	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	200373	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	200373	0	0
T1	17075	698	0	0
T2	8713	11	0	0
T3	2829	9	0	0
T4	309217	222	0	0
T7	12949	16	0	0
T8	1752	15	0	0
T9	2356	15	0	0
T10	26464	324	0	0
T11	286011	20	0	0
T12	57831	105	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	200373	0	0
T1	17075	698	0	0
T2	8713	11	0	0
T3	2829	9	0	0
T4	309217	222	0	0
T7	12949	16	0	0
T8	1752	15	0	0
T9	2356	15	0	0
T10	26464	324	0	0
T11	286011	20	0	0
T12	57831	105	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	200373	0	0
T1	17075	698	0	0
T2	8713	11	0	0
T3	2829	9	0	0
T4	309217	222	0	0
T7	12949	16	0	0
T8	1752	15	0	0
T9	2356	15	0	0
T10	26464	324	0	0
T11	286011	20	0	0
T12	57831	105	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	2856299	0	0
T1	17075	618	0	0
T2	8713	84	0	0
T3	2829	78	0	0
T4	309217	73619	0	0
T7	12949	105	0	0
T8	1752	15	0	0
T9	2356	15	0	0
T10	26464	331	0	0
T11	286011	81	0	0
T12	57831	833	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	200373	0	0
T1	17075	698	0	0
T2	8713	11	0	0
T3	2829	9	0	0
T4	309217	222	0	0
T7	12949	16	0	0
T8	1752	15	0	0
T9	2356	15	0	0
T10	26464	324	0	0
T11	286011	20	0	0
T12	57831	105	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	200373	0	0
T1	17075	698	0	0
T2	8713	11	0	0
T3	2829	9	0	0
T4	309217	222	0	0
T7	12949	16	0	0
T8	1752	15	0	0
T9	2356	15	0	0
T10	26464	324	0	0
T11	286011	20	0	0
T12	57831	105	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	520738	0	0
T1	17075	789	0	0
T2	8713	11	0	0
T3	2829	9	0	0
T4	309217	6644	0	0
T7	12949	19	0	0
T8	1752	16	0	0
T9	2356	16	0	0
T10	26464	332	0	0
T11	286011	33	0	0
T12	57831	135	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	200373	0	0
T1	17075	698	0	0
T2	8713	11	0	0
T3	2829	9	0	0
T4	309217	222	0	0
T7	12949	16	0	0
T8	1752	15	0	0
T9	2356	15	0	0
T10	26464	324	0	0
T11	286011	20	0	0
T12	57831	105	0	0

Line Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T10,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T10,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_56.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	193721	0	0
GntImpliesValid_A	414643205	193721	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	193721	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	2857479	0	0
ReadyAndValidImplyGrant_A	414643205	193721	0	0
ReqAndReadyImplyGrant_A	414643205	193721	0	0
ReqImpliesValid_A	414643205	559481	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	0	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	193721	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	193721	0	0
T1	17075	120	0	0
T2	8713	12	0	0
T3	2829	16	0	0
T4	309217	210	0	0
T7	12949	24	0	0
T8	1752	11	0	0
T9	2356	16	0	0
T10	26464	732	0	0
T11	286011	14	0	0
T12	57831	107	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	193721	0	0
T1	17075	120	0	0
T2	8713	12	0	0
T3	2829	16	0	0
T4	309217	210	0	0
T7	12949	24	0	0
T8	1752	11	0	0
T9	2356	16	0	0
T10	26464	732	0	0
T11	286011	14	0	0
T12	57831	107	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	193721	0	0
T1	17075	120	0	0
T2	8713	12	0	0
T3	2829	16	0	0
T4	309217	210	0	0
T7	12949	24	0	0
T8	1752	11	0	0
T9	2356	16	0	0
T10	26464	732	0	0
T11	286011	14	0	0
T12	57831	107	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	2857479	0	0
T1	17075	129	0	0
T2	8713	105	0	0
T3	2829	157	0	0
T4	309217	67065	0	0
T7	12949	128	0	0
T8	1752	12	0	0
T9	2356	17	0	0
T10	26464	659	0	0
T11	286011	54	0	0
T12	57831	770	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	193721	0	0
T1	17075	120	0	0
T2	8713	12	0	0
T3	2829	16	0	0
T4	309217	210	0	0
T7	12949	24	0	0
T8	1752	11	0	0
T9	2356	16	0	0
T10	26464	732	0	0
T11	286011	14	0	0
T12	57831	107	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	193721	0	0
T1	17075	120	0	0
T2	8713	12	0	0
T3	2829	16	0	0
T4	309217	210	0	0
T7	12949	24	0	0
T8	1752	11	0	0
T9	2356	16	0	0
T10	26464	732	0	0
T11	286011	14	0	0
T12	57831	107	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	559481	0	0
T1	17075	122	0	0
T2	8713	12	0	0
T3	2829	16	0	0
T4	309217	2668	0	0
T7	12949	34	0	0
T8	1752	11	0	0
T9	2356	16	0	0
T10	26464	821	0	0
T11	286011	22	0	0
T12	57831	111	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	900

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	193721	0	0
T1	17075	120	0	0
T2	8713	12	0	0
T3	2829	16	0	0
T4	309217	210	0	0
T7	12949	24	0	0
T8	1752	11	0	0
T9	2356	16	0	0
T10	26464	732	0	0
T11	286011	14	0	0
T12	57831	107	0	0

Line Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_28.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	809974	0	0
GntImpliesValid_A	414643205	809974	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	809974	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	11182236	0	0
ReadyAndValidImplyGrant_A	414643205	809974	0	0
ReqAndReadyImplyGrant_A	414643205	809974	0	0
ReqImpliesValid_A	414643205	2224423	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	13227	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	809974	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	809974	0	0
T1	17075	1101	0	0
T2	8713	34	0	0
T3	2829	30	0	0
T4	309217	859	0	0
T7	12949	66	0	0
T8	1752	56	0	0
T9	2356	57	0	0
T10	26464	1866	0	0
T11	286011	68	0	0
T12	57831	413	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	809974	0	0
T1	17075	1101	0	0
T2	8713	34	0	0
T3	2829	30	0	0
T4	309217	859	0	0
T7	12949	66	0	0
T8	1752	56	0	0
T9	2356	57	0	0
T10	26464	1866	0	0
T11	286011	68	0	0
T12	57831	413	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	809974	0	0
T1	17075	1101	0	0
T2	8713	34	0	0
T3	2829	30	0	0
T4	309217	859	0	0
T7	12949	66	0	0
T8	1752	56	0	0
T9	2356	57	0	0
T10	26464	1866	0	0
T11	286011	68	0	0
T12	57831	413	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	11182236	0	0
T1	17075	11	0	0
T2	8713	270	0	0
T3	2829	181	0	0
T4	309217	278284	0	0
T7	12949	443	0	0
T8	1752	1	0	0
T9	2356	1	0	0
T10	26464	16	0	0
T11	286011	269	0	0
T12	57831	2757	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	809974	0	0
T1	17075	1101	0	0
T2	8713	34	0	0
T3	2829	30	0	0
T4	309217	859	0	0
T7	12949	66	0	0
T8	1752	56	0	0
T9	2356	57	0	0
T10	26464	1866	0	0
T11	286011	68	0	0
T12	57831	413	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	809974	0	0
T1	17075	1101	0	0
T2	8713	34	0	0
T3	2829	30	0	0
T4	309217	859	0	0
T7	12949	66	0	0
T8	1752	56	0	0
T9	2356	57	0	0
T10	26464	1866	0	0
T11	286011	68	0	0
T12	57831	413	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	2224423	0	0
T1	17075	1101	0	0
T2	8713	73	0	0
T3	2829	47	0	0
T4	309217	29679	0	0
T7	12949	118	0	0
T8	1752	56	0	0
T9	2356	57	0	0
T10	26464	1866	0	0
T11	286011	102	0	0
T12	57831	601	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	13227	0	900
T1	17075	10	0	1
T2	8713	0	0	1
T3	2829	0	0	1
T4	309217	0	0	1
T7	12949	0	0	1
T8	1752	0	0	1
T9	2356	0	0	1
T10	26464	36	0	1
T11	286011	0	0	1
T12	57831	0	0	1
T14	0	2	0	0
T15	0	7	0	0
T16	0	1	0	0
T17	0	3	0	0
T18	0	19	0	0
T19	0	12	0	0
T20	0	6	0	0
T21	0	8	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	809974	0	0
T1	17075	1101	0	0
T2	8713	34	0	0
T3	2829	30	0	0
T4	309217	859	0	0
T7	12949	66	0	0
T8	1752	56	0	0
T9	2356	57	0	0
T10	26464	1866	0	0
T11	286011	68	0	0
T12	57831	413	0	0

Line Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	6	6	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103	1	1
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T8
1	0	Not Covered
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	76	2	2	100.00
TERNARY	90	2	2	100.00
IF	96	4	4	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/xbar_build_mode/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T2,T3,T7
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sm1_30.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414643205	414523610	0	0
CheckNGreaterZero_A	900	900	0	0
GntImpliesReady_A	414643205	798603	0	0
GntImpliesValid_A	414643205	798603	0	0
GrantKnown_A	414643205	414523610	0	0
IdxKnown_A	414643205	414523610	0	0
IndexIsCorrect_A	414643205	798603	0	0
LockArbDecision_A	414643205	0	0	0
NoReadyValidNoGrant_A	414643205	349844656	0	0
ReadyAndValidImplyGrant_A	414643205	798603	0	0
ReqAndReadyImplyGrant_A	414643205	798603	0	0
ReqImpliesValid_A	414643205	13018250	0	0
ReqStaysHighUntilGranted0_M	414643205	0	0	0
RoundRobin_A	414643205	20917	0	900
ValidKnown_A	414643205	414523610	0	0
gen_data_port_assertion.DataFlow_A	414643205	798603	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	900	900	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	798603	0	0
T1	17075	1070	0	0
T2	8713	33	0	0
T3	2829	38	0	0
T4	309217	762	0	0
T7	12949	56	0	0
T8	1752	50	0	0
T9	2356	56	0	0
T10	26464	1858	0	0
T11	286011	79	0	0
T12	57831	388	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	798603	0	0
T1	17075	1070	0	0
T2	8713	33	0	0
T3	2829	38	0	0
T4	309217	762	0	0
T7	12949	56	0	0
T8	1752	50	0	0
T9	2356	56	0	0
T10	26464	1858	0	0
T11	286011	79	0	0
T12	57831	388	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	798603	0	0
T1	17075	1070	0	0
T2	8713	33	0	0
T3	2829	38	0	0
T4	309217	762	0	0
T7	12949	56	0	0
T8	1752	50	0	0
T9	2356	56	0	0
T10	26464	1858	0	0
T11	286011	79	0	0
T12	57831	388	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	349844656	0	0
T2	8713	7610	0	0
T3	2829	2063	0	0
T4	309217	281614	0	0
T7	12949	11213	0	0
T8	1752	1	0	0
T9	2356	1	0	0
T10	26464	1	0	0
T11	286011	237892	0	0
T12	57831	49876	0	0
T13	461861	441887	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	798603	0	0
T1	17075	1070	0	0
T2	8713	33	0	0
T3	2829	38	0	0
T4	309217	762	0	0
T7	12949	56	0	0
T8	1752	50	0	0
T9	2356	56	0	0
T10	26464	1858	0	0
T11	286011	79	0	0
T12	57831	388	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	798603	0	0
T1	17075	1070	0	0
T2	8713	33	0	0
T3	2829	38	0	0
T4	309217	762	0	0
T7	12949	56	0	0
T8	1752	50	0	0
T9	2356	56	0	0
T10	26464	1858	0	0
T11	286011	79	0	0
T12	57831	388	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	13018250	0	0
T1	17075	1070	0	0
T2	8713	215	0	0
T3	2829	328	0	0
T4	309217	270589	0	0
T7	12949	395	0	0
T8	1752	50	0	0
T9	2356	56	0	0
T10	26464	1858	0	0
T11	286011	335	0	0
T12	57831	3138	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	20917	0	900
T1	17075	5	0	1
T2	8713	0	0	1
T3	2829	0	0	1
T4	309217	0	0	1
T7	12949	0	0	1
T8	1752	0	0	1
T9	2356	0	0	1
T10	26464	21	0	1
T11	286011	0	0	1
T12	57831	0	0	1
T14	0	2	0	0
T15	0	12	0	0
T16	0	2	0	0
T17	0	2	0	0
T18	0	7	0	0
T19	0	15	0	0
T20	0	5	0	0
T21	0	11	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	414523610	0	0
T1	17075	16272	0	0
T2	8713	8697	0	0
T3	2829	2680	0	0
T4	309217	309211	0	0
T7	12949	12908	0	0
T8	1752	1708	0	0
T9	2356	2284	0	0
T10	26464	25527	0	0
T11	286011	285987	0	0
T12	57831	57799	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414643205	798603	0	0
T1	17075	1070	0	0
T2	8713	33	0	0
T3	2829	38	0	0
T4	309217	762	0	0
T7	12949	56	0	0
T8	1752	50	0	0
T9	2356	56	0	0
T10	26464	1858	0	0
T11	286011	79	0	0
T12	57831	388	0	0